DE19742389A1 - Power on reset signal generation circuit - Google Patents

Abstract

The reset signal generation circuit provides a reset signal signalling switching in of the supply voltage. The circuit nodes (VB,VC) have a potential which affects the duration and/or amplitude of the reset signal, which is coupled via capacitive elements (C2,C3) for initial discharge and/or parasitic capacitance compensation, to the supply voltage terminals. An inverter (I1) is coupled between a first supply terminal (VSS) and one circuit node (VA), with its input coupled to a second circuit node (VB) and its output coupled to a third circuit node (VC), with an initialising circuit (INIT) between both supply terminals (VDDx,VSS).

Description

The present invention relates to a device according to the Preamble of claim 1, d. H. a circuit for Generation of switching on a supply voltage signaling reset signal.

When switching on the supply voltage of complex circuits conditions, in particular complex integrated circuits the risk that individual circuit parts have an undefined Take state. Undefined conditions can cause malfunction or damage to these circuits or the result in these connected facilities.

In order to be able to rule this out, circuits for Generation of switching on a supply voltage signaling reset signal (so-called power-on-reset scarf tions) provided. Such circuits produce the Switching on the supply voltage a reset signal in the form a mostly single signal pulse, which with respect to the Switching on the supply voltage critical circuits or circuit parts specifically in a defined output state to solve the problems mentioned at the beginning avoid.

Circuits designed to generate reset signals are known, for example, from EP 0 496 018 B1. One of the circuits known from this document is shown in Fig. 4 ge and will be described below with reference to it.

The circuit shown in FIG. 4 has connections for a first (VDDx) and a second (VSS) supply potential. The first supply potential VDDx is, for example, 5 V; the second supply potential is, for example, 0 V (ground potential). Of course, the first and second supply potentials can also assume any other values and polarities. The difference between the first supply potential VDDx and the second supply potential VSS is the supply voltage, the switching on of which is to be signaled by the reset signal.

Between the connections for the supply potential VDDx and VSS is one of a series connection of an ohmic Resistor R1 and a capacitance C1 existing serial RC network RC provided. In the example considered, in which chem the circuit as an integrated circuit or as The Kapa is part of such a project frequency C1 preferably implemented by a MOS transistor, whose drain and source connections are interconnected are; the capacity C1 can of course also be formed by a "normal" capacitor. Between the resistor R1 and the capacitor C1 is a he most node VA.

Also between the connections for the supply points tial VDDx and VSS, i.e. parallel to the RC network RC is one Initialization circuit INIT provided. The initial The circuit consists of a series connection of an ohm 's resistance R2 and two diodes D1 and D2, the Resistor R2 with the connection for the first supply potential VDDx and the diode D2 with the connection for the second supply potential VSS are connected. The diodes D1 and D2 are in the example considered by NMOS-Transisto ren realized, their gate and drain connections with each other are connected; however, the diodes can also be replaced by "normal" discrete diodes are formed. The initialization scarf device INIT generates an output signal that is between the resistor stood R2 and the diodes D1 and D2 tapped and one second node VB is performed.  

This occurs during the operation of the circuit at the node VB setting potential is a maximum of VSS plus the flux voltage of the first diode D1 plus the forward voltage of the two th diode D2. For example, if VSS is 0 V, the flow voltage of the first diode D1 is 1 V, and the forward voltage the second diode p2 is equal to 1.4 V, so can be at the node point VB, set a maximum voltage of 2.4 V.

Between the first node VA and the connection for the second supply potential VSS is an inverter circuit I1 arranged. The inverter circuit I1 is in the case under consideration play one of two transistors T1 and T2 of opposite existing cable type of existing CMOS inverters. The entrance Connection of the inverter circuit I1 is with the second node point connected to VB; the output connection falls with a third node VC together.

Between the second node VB and the connection for the second supply potential VSS is an NMOS transistor T3 arranged with its canal route; the gate connection of the Transistor T3 is connected to the third node VC.

The third node VC also coincides with the input of a second inverter circuit I2, which is connected in terms of supply voltage to the connections for the two supply potentials VDDx and VSS. The output of the second inverter circuit I2 coincides with a fourth node point VD; at this fourth node VD, the reset signal to be generated by the circuit according to FIG. 4 is produced.

The fourth node VD can be one in the figures Downstream delay circuit, not shown, wel in operation, the rear one (in the example under consideration output edge of the reset signal with a time delay. In order to the duration of the reset signal can be increased.  

The function of the circuit of Fig. 4 will be described hereinafter un ter reference to Fig. 6. It is assumed that the supply potentials VDDx and VSS each have values of 0 V at the beginning (at switch-on time t1), the first supply potential VDDx rising from this up to a time t5 to a nominal value VDD of 5 V for example. With the increase in the supply potential VDDx, the potential at the node VA increases up to the nominal value VDD. Because of the RC effect of the RC network RC (charging the capacitance C1), however, this increase takes place significantly more slowly than that of the first supply potential VDDx, the exact course of time depending on the dimensioning of the resistor R1 and the capacitance C1.

A potential increase also occurs at the second node VB. This increase in potential is significantly faster than the increase in potential at node VA, but is limited by the diodes D1 and D2 to the maximum value already mentioned. As already mentioned above, the maximum value is a sum, referred to below as U _{D1 + D2} , of the voltage drops U _D1 and U _{D2 occurring} at the diodes D1 and _D2 . This maximum value is reached at a time t2 and remains until a time t4.

Because of the different rapid changes in potential at the Nodes VA and VB are at (up to) time t2 Potential at the first node VA lower than the potential tial at the second node VB. Reduce from time t2 is concerned about the constancy of the potential that then occurs at the second node VB the difference between the pots tials at the nodes VA and VB. The potential at he Most node VA reaches the potential at the second node point VB and then even exceeds it.

At time t3, at which the second node VB still has the potential U _{D1 + D2} , the potential at the first node VA has a value of U _{D1 + D2,} hereinafter referred to as U _{D1 + D2 + T1} , plus the value of the threshold voltage V _{T1 of} the (PMOS) transistor T1 of the CMOS inverter of the inverter circuit I1. Up to this point, the PMOS transistor T1 is blocked, while the NMOS transistor T2 of the CMOS inverter of the inverter circuit I1 is conductive (the potential at the second node VB is greater than the threshold voltage V _{T2 of} the NMOS transistor T2). Accordingly, the third node VC has the value of the second supply potential VSS (0 V) up to the time t3. As a result of this, the potential at the fourth node VD (the output of the second inverter circuit I2) has the current value of the first supply potential VDDx in the period between the times t1 and t3.

From time t3, the potential at the first node VA becomes greater than U _{D1 + D2 + T1} ; the potential at the second node remains unchanged U _{D1 + D2} . As a result, the PMOS transistor T1 of the inverter circuit I1 becomes increasingly conductive. The potential at the third circuit node VC thus rises to the current potential at the first node VA.

When the potential at the third circuit node VC rises above the value of the threshold voltage V _{T3 of} the (NMOS) transistor T3, the latter becomes conductive (time t4) and thereby pulls the potential of the second node VB to the second supply potential VSS (0 V). As a result, the transistor T2 of the first inverter circuit I1 blocks and the transistor T1 becomes even more conductive.

Doing so achieves more and more increasing Potential at the third node VC the threshold voltage of the second inverter circuit I2, so this switches and gives henceforth the second supply potential VSS at the output (on fourth node VD), with which the generation of the Re set signal has ended.  

The reset signal at the fourth node VD accordingly shows fol current course; First, H. increases from time t1 the reset signal coincides with the time course of the first supply potential VDDx. This continues until continues at the time when the potential at the input of the second inverter circuit I2 (the potential at the third node point VC) corresponds to the potential at which the second Inverter circuit I2 switches. By switching the two Inverter circuit I2, the reset signal drops more or less quickly to its original value (VSS) from. The rear flank (falling in the example considered) of the reset signal can, as already mentioned at the beginning, are outputted delayed by a delay circuit.

To prevent that after generating the reset signal between the connections for the supply potentials VDDx and VSS via resistor R2 and the then conductive Tran sistor T3 a current flows continuously, can be between the resistor stood R2 and the transistor T3 an additional transistor be provided, which is designed and attached controlled that it is conductive, if and as long as the Tran sistor T3 blocks, and which blocks if and as long as the Transistor T3 is conductive.

Such a modified circuit is illustrated in FIG. 5; the additional transistor is designated by the reference character T4.

The circuits described above with reference to FIGS. 4 and 5 are circuits according to the preamble of claim 1.

Such circuits allow the required Re Usually generate set signals reliably. The reset signals are created in a way that is relative simple and reliable evaluation of the same or reaction on the same.  

Experience shows, however, that under certain unfavorable Under certain circumstances no reset signal or at least not sufficient long and / or high reset signal is generated.

The present invention is therefore based on the object the circuit according to the preamble of claim 1 to further develop such that the generation of reset signals works properly even under unfavorable circumstances.

According to the invention, this object is characterized by the solved the part of claim 1 claimed features.

Accordingly, it is provided that those nodes of the Circuit whose potential has a decisive influence on the duration and / or the level of the reset signal to be generated, at least in part for initial discharge and / or com compensation of parasitic capacitances kende elements with one of the supply voltage connections are connected.

By providing such capacitive elements can prevent be changed that at the relevant nodes Set potentials or potential courses that one counteract the intended reset signal generation.

This can ensure that the generation of Reset signals properly even under unfavorable circumstances is working.

The invention is described below with reference to the Drawing explained in more detail using exemplary embodiments. Show it

Fig. 1 tung an embodiment of the formwork according to the invention,

Fig. 2 are timing charts illustrating the reset Sig nal generating at a particularly slow to increase the supply voltage,

Fig. 3 are timing charts illustrating the reset Sig nal-generation in a short successive switching on and off the supply voltage,

Fig. 4, a conventional supply circuit for reset signal Erzeu,

Fig. 5 shows another conventional circuit for reset signal generation, and

Fig. 6 are timing charts illustrating the reset Sig nal-generation by the circuit according to Fig. 4.

The circuit for reset signal generation described below with reference to FIGS. 1 to 3 is an integrated circuit or part of an integrated circuit. However, there is no restriction to this; the circuit can also be implemented as a "normal" circuit using discrete components.

The structure of the circuit described below is illustrated in FIG. 1.

The circuit according to FIG. 1 is based on the circuits according to FIGS. 4 and 5. Unless expressly stated otherwise, all explanations apply, which are at the beginning of the circuits according to FIGS . 4 and 5 and of the control flow diagrams according to FIG. 6 were made, also for the circuit described below according to FIG. 1; Corresponding components of the circuits according to FIGS. 1, 4 and 5 are identified by the same reference numerals.

Ie., The circuit of FIG. 1 has an inverter circuit I1, starting in particular because of the self-adjusting at nodes VA and VB potential profiles until some time after switching on the power clamping voltage to work properly. As long as the potential at the node VA does not exceed the potential at the node VB by at least the threshold voltage U _{T1 of} the transistor T1, the output of the inverter circuit I1 remains independent of the input signal at VSS potential. Only when the potential at node VA, the rise of which is slowed down again by the RC network RC, does the potential at node VB rise sufficiently far does the (PMOS) transistor T1 of the inverter circuit conduct and thus ensure an increase in the potential at Output of the inverter circuit I1 (at the node VC). With rising potential at the node VA, the transistor T1 (which is constantly controlled by the diodes D1 and D2) becomes increasingly low-ohmic, as a result of which the potential which arises at the node VC continues to increase. As soon as the potential which arises at the node VC reaches the threshold voltage V _{T3 of} the transistor T3, the latter becomes conductive, as a result of which the potential which arises at the node VB drops. The drop in the potential occurring at the node VB causes the transistor T1 to become more conductive and the transistor T2 to block. This promotes the increase in the potential that arises at node VC. More or less simultaneously with the opening of the transistor T3 it follows a blocking of the transistor T4, so that stood over the opposing R2 and the transistor T3 no cross current can flow. Since the transistor T4 primarily prevents the flow of a cross current, it can also be omitted under certain circumstances. As long as the potential occurring at the node VC does not reach the switchover point of the inverter circuit I2, the reset signal issued by it increases approximately like the first supply potential VDDx; As soon as the potential at the node VC reaches the switchover point of the inverter circuit I2, the reset signal output by it drops sharply.

In contrast to the conventional circuits for reset signal generation, the circuit according to FIG. 1 has additional capacitances C2 and C3, the capacitance C2 between the node VC and the second supply potential VSS, and the capacitance C3 between the Node VB and the first supply potential VDDx is arranged.

By providing the additional capacity C2 at the node point VC this is coupled to VSS, which in turn - depending at least if the Kapa is sufficiently large Zitat C2 - a Kopp over parasitic capacitances VC node according to VDD eliminated or prevented can be. This proves to be extremely advantageous because a coupling of the node VC to VDDx would result in that the inverter circuit I2 after a very short time tilts and therefore no proper, d. H. no or only one would generate short and low reset signal. A para municipal capacity through which the node VC according to VDDx can be drawn, for example, but without two not only the relatively high gate-source capacitance act of transistor T4.

By providing the additional capacity C3 at the node VB, this is coupled to VDDx, which is particularly important in the first phase of the VDDx increase. As long as VDDx is still below the threshold voltage of the (PMOS) transistor T4, the node VB is not actively driven, which, with a slow rise in VDDx, can lead to the transistor T1 of the inverter circuit I1 not being relatively late but already in this early initial phase is switched through. This, in turn, can lead to a correspondingly early tilting of the inverter circuit I2, where the reset signal generated by this turns out to be extremely short and / or low. The provision of the capacitance C3 is particularly important in the case of rapid successive switch-off and switch-on operations and also when the transistor T4 is not provided, because in this case there is a not inconsiderable probability that residual charges remain at the node VB which ensure this that there at least for a certain time after switching on the supply voltage set potentials which conflict with the intended function of the circuit for reset signal generation. The same applies to the additional capacity C2 at the node VC. The capacitances C2 and C3 and, if appropriate, further capacitances at other nodes of the circuits shown in FIG. 1 or constructed differently, cause the nodes to be initialized when the supply voltage is switched on by coupling the nodes to VDD or VSS. As a result, the circuit in question can be put into a defi ned initial state each time the supply voltage is switched on, which is essentially independent of the state in which the circuit was more or less long before.

The effect of the additional provision of the capacitances C2 and C3 can be seen from the timing diagrams shown in FIGS . 2 and 3.

FIG. 2 illustrates the situation when the supply voltage is switched on "normally", whereby

• - the top of the three curves the course of the first Versor potential VDDx shows
• - The middle curve shows the reset signal course, which to is observed if there is no capacitance C2 at the node VC is provided, and
• - The bottom curve shows the reset signal course that is closed is observed when the capacitance C2 at the node VC is provided.

As can be clearly seen from FIG. 2, the additional provision of the capacitance C2 leads to the fact that a long and highly developed reset signal is obtained, which is not the case when the circuit is operated without the capacitance C2. Only by providing the capacitance C2 at the node VC can it be ensured that a reset signal which can be evaluated easily and reliably is generated even under unfavorable circumstances when the supply voltage is switched on.

Fig. 3 illustrates the situation when the supply voltage is switched on, which immediately follows the same when it is switched off, wherein

• - the top of the three curves the course of the first Versor potential VDDx shows
• - The middle curve shows the reset signal course, which to is observed if there is no capacitance C3 at the node VB is provided, and
• - The bottom curve shows the reset signal course that is closed is observed when the capacitance C3 at the node VB is provided.

As can be clearly seen from FIG. 3, the additional provision of the capacitance C3 leads to the fact that a long and highly developed reset signal is obtained, which is not the case when the circuit is operated without the capacitance C3 . Only by providing the capacitance C3 at the node VB can it be ensured that, even under unfavorable circumstances, when the supply voltage is switched off and on relatively quickly in succession, a reset signal which can be evaluated easily and reliably is generated.

The provision of capacities C2 and C3 therefore enables that the generation of reset signals even under unfavorable May work properly.  

Reference list

VDDx first supply potential
VSS second supply potential
RC RC network
R1 resistance of the RC network
C1 capacitor of the RC network
INIT initialization circuit
R2 resistance of the initialization circuit
T4 transistor of the initialization circuit
D1 diode of the initialization circuit
D2 diode of the initialization circuit
I1 first inverter circuit
T1 transistor of the first inverter circuit
T2 transistor of the first inverter circuit
I2 second inverter circuit
T3 transistor
C2 capacitor
C3 capacitor
VA first node
VB second node
VC third node
VD fourth node

Claims (9)

1. Circuit for generating a switch-on of a supply voltage signaling reset signal (RESET), characterized in that those nodes (VB, VC) of the circuit, their potential significant influence on the duration and / or amount of the reset signal to be generated has, at least partially via capacitively acting elements (C2, C3) designed for initial discharge and / or for compensating parasitic capacitances, are connected to one of the supply voltage connections. 2. Circuit according to claim 1, characterized in

• - That it has connections for a first and a second supply potential (VDDx, VSS),
• - That it comprises an inverter circuit (I1), which is arranged in terms of supply voltage between a first node (VA) and the connection for the second supply potential (VSS),
• - That the input of the inverter circuit (I1) is connected to a second node (VB) and its output represents a third node (VC),
• - That an initialization circuit (INIT) is arranged between the connections for the first and the second supply potential (VDDx, VSS), the output of the initialization circuit forming the second node (VB) and detecting a potential with one when the supply voltage is switched on the dimensioning of the initialization circuit assumes the predetermined maximum value,
• that a transistor (T3) with its source-drain path is arranged between the second node (VB) and the connection for the second supply potential (VSS), the gate of this transistor being connected to the third node (VC),
• that a serial RC network (RC) is arranged between the connections for the first and the second supply potential (VDDx, VSS), between whose ohmic (R1) and its capacitive (C1) component lies the first node (VA), wherein the potential at the first node (VA) is the voltage drop across the capacitive component (C1) of the RC network (RC), and
• - That the third node (VC) forms the input of a second inverter circuit (I2), which is in terms of supply voltage between the connections for the first and the second supply voltage potential (VDDx, VSS), and at its output as a fourth node (VD) in Operation the reset signal to be generated by the circuit arises.

3. Circuit according to claim 2, characterized, that the fourth node (VD) has a delay circuit is subordinate, which in operation is a trailing edge of the Reset signal outputs delayed. 4. Circuit according to claim 2 or 3, characterized, that the initialization circuit (INIT) at least one contains ohmic resistance (R2) between the connector for the first supply potential (VDDx) and the second Node (VB) is arranged. 5. Circuit according to claim 4, characterized, that the initialization circuit (INIT) is a transistor (T4) contains, with its source-drain path between the ohmic resistor R2 and the second node (VB) is arranged, the gate with the third node (VC) connected, and which is designed to conduct when and as long as that between the second node (VB) and the connection for the second supply potential (VSS)  ordered transistor (T3) blocks and which is designed to to lock if and as long as the one between the second kno tenpunkt (VB) and the connection for the second supply potential (VSS) arranged transistor (T3) conducts. 6. Circuit according to one of claims 2 to 5, characterized, that the initialization circuit (INIT) one or more in Series connected diodes (D1, D2) contains between the second node (VB) and the connection for the second Ver care potential (VSS) are arranged. 7. Circuit according to one of claims 2 to 6, characterized, that the inverter circuit (I1) has at least two transistors (T1, T2) of the opposite conduction type. 8. Circuit according to one of claims 2 to 7, characterized, that the second node (VB) with a capacity (C3) with the connection for the first supply potential (VDDx) ver is bound. 9. Circuit according to one of claims 2 to 8, characterized, that the third node (VC) with a capacity (C2) with the connection for the second supply potential (VSS) ver is bound.