DE19742125A1 - Static random-access memory cell for non-volatile memory - Google Patents

Abstract

The memory cell has two floating gate transistors (TF1,TF2) each coupled to a supply voltage (VDD) at its drain via a switch (S1,S2) and a positive. MOS transistor (TP1,TP2). The sources of the floating gate transistors are coupled together. The gates of the positive. MOS transistors are each coupled to the junction of the other transistor and the series switch and to a respective circuit output terminal (A1,A2). The coupled sources of the floating gate transistors are connected to a programming and/or erasure voltage terminal (P/L).

Description

It is often required with integrated semiconductor circuits Lich, operating conditions such. B. Capture test modes, too when the operating voltage is switched off. With semiconductors chips with a non-volatile memory it lends itself such settings in memory cells of this non-volatile storage.

The storage can be done in several ways. So you can e.g. B. reserve certain memory cells in the memory field, which save the operating status. However, this has the Disadvantage that the user no longer goes through the memory gig because the test bits given as an example interrupt memory addressing.

The bits used do not contain any ver for the user valuable information that cannot be changed. So it does not work for a user of the semiconductor chip Use if z. B. is stored whether a chip is still under test mode is as it is required when the chip is in the Outgoing inspection after production is checked because for test mode is always switched off for the chip user. He has less free space.

When the chip is put into operation, the chip logic must be closed only these memory bits through normal addressing of the memory Read out to determine the condition of the Chip should be.

Alternatively, in addition to the memory field, additional memory cells are built in, which immediately provide their information Can provide. The individual cells are over a load element z. B. a resistor or a De pletion MOS transistor connected.  

If a 0V signal is stored in such a memory cell is saved, d. H. the memory transistor is conductive, pulls the memory cell the node between itself and the Lastele ment to 0V and a current flows continuously.

The problem underlying the invention is therefore a Non-volatile memory cell indicate these disadvantages avoids.

The problem is solved by a memory cell according to claim 1 solved.

The static non-volatile memory cell according to the invention has the advantage of being outside of the user's memory field because it is structured differently and therefore the information immediately after switching on the operating voltage of the semiconductor can provide chips. Nevertheless, no cross flows electricity.

The invention is illustrated below with the aid of an embodiment game described with the help of a figure.

There are two series in the memory cell according to the invention circuits each consisting of a PNOS transistor TP1 or TP2, a switch S1 or S2 and a NOS transistor TF1 or TF2 with an insulated gate electrode, in the following floa called ting gate transistor, connected in parallel. The drain Connections of the PMOS transistors TP1 and TP2 are with the Connection for a first, positive supply voltage VDD and the source connections of the floating gate transistors TF1 or TF2 via a third switch S3 with the connection for one second supply voltage GND, preferably the ground conclusion, connected. The gate port of the first PMOS transistor TP1 is connected to the connection node of the second PMOS transistor TP2 and the second switch S2 connected. The gate terminal of the second PMOS transistor TP2 is connected to the  Connection node of the first PMOS transistor TP1 and he Most switches S1 connected. The two connection nodes bil the respective output connections A1, A2. The source connections of the floating gate transistors TF1 and TF2 form an on final P / L for a programming and / or erase voltage.

The switches S1. . .S3 are due to the control logic of the half lead techips on which the memory cell (s) according to the invention are formed, can be controlled and can by transistors be educated.

The operating modes of the memory cell should be in the following be written.

The three switches S1 are in read mode. . .S3 closed. On the control gate connections G1, G2 of the floating gate transistor ren TF1, TF2 is typi for floating gate transistors read voltage. Depending on how the floating gate tran sistors TF1, TF2 can be programmed to the output conclude A2, A1 the memory content of the memory cell will read.

In the off state, the first floating gate transistor TF1 conducts and thereby draws the potential of the second output connection ses A2 to 0V. This is the gate of the second PMOS train transistor TP2 also at 0V, which makes it conductive and it most output terminal A1 to the potential of the first Versor voltage VDD pulls. The first PMOS transistor TP1 is thereby locked. Since the second floating gate transistor TF2 is blocked, both branches are between the Versor voltage voltages VDD, GND interrupted, so that no cross current can flow.

The transistors and voltages behave in the on state exactly mirror image. It can also be the off state written state can be interpreted as an on state and vice versa.  

If both transistors are conducting, this is called an idle state designated. This state is when the sta through the memory cell. It may also be that the static memory cell after leaving production is in this state. Since both floating gate transisto If TF1, TF2 are conductive, both PMOS transistors are also used ren TP1, TP2 turned on so that there is a current flow in two branches between the supply voltages VDD, GND is coming. The PMOS transistors are therefore more advantageous Designed in such a way that they limit the current flow that the circuit function is not affected.

In a fourth state, both are floating gate transistors locking TF1, TF2. This state is called the Fab state designated. The fab state can only occur when the chip production (Fab) leaves. It cannot be predicted whether the static memory cell in idle or Fab Condition is. It is only certain that they are not or off state because the isolated gates of the floating Gate transistors TF1, TF2 have the same charge. Is the State of the memory cell when switched on for the first time Manufacturing important, so you can by asymmetrical design of the PMOS transistors TP1, TP2 or provision of a load define a preferred situation. The memory cell tips over then when switching on either in idle, on or the off state.

To program the memory cell, both are first Floating gate transistors TF1, TF2 in the conductive state brought. All three switches S1. . .S3 open, the output connections G1, G2 are set to 0V and to the An for a programming or erase voltage P / L the Pro gramming voltage applied. After a process-specific time are both floating gate transistors TF1, TF2, which Memory cell is idle.  

If the "on" state is now to be programmed, at open switches S1. . .S3 to the connection for a programming or erase voltage P / L and the gate terminal G2 of the second Floating gate transistor TF2 0V and connected to the gate circuit G1 of the first floating gate transistor TF1 the Pro grammage tension. To program the off state are instead the gate terminal G1 of the second floating gate To set transistor TF1 to 0V, and the gate terminal G2 of the second floating gate transistor TF2 on Program voltage potential.

Claims (1)

1. Static non-volatile memory cell

• - With a first floating gate transistor (TF1), the drain connection of which is connected via a first switch (S1) and a first PMOS transistor (TP1) to the connection for a first supply voltage (VDD),
• - With a second floating gate transistor (TF2), the drain connection of which is connected via a second switch (S2) and a second PMOS transistor (TP2) to the connection for the positive supply voltage (VDD),
• - The gate terminal of the first PMOS transistor is connected to the connection point of the second switch (S2) and the second PMOS transistor (TP2) forming a first output terminal (A1),
• - The gate terminal of the second PMOS transistor is connected to the connection point of the first switch (S1) and the first PMOS transistor (TP1) forming a second output terminal (A2),
• - The source connections of the floating gate transistors (TF1, TF2) are connected to one another and via a third switch (S3) to the connection for a second supply voltage (GND) and
• - The connection point of the source connections of the floating gate transistors (TF1, TF2) forms a connection (P / L) for a programming and / or an erase voltage.