DE19741928C1 - Semiconductor component e.g. silicon carbide MOS transistor for smart power integrated circuit - Google Patents

Semiconductor component e.g. silicon carbide MOS transistor for smart power integrated circuit

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Publication number
DE19741928C1
DE19741928C1 DE19741928A DE19741928A DE19741928C1 DE 19741928 C1 DE19741928 C1 DE 19741928C1 DE 19741928 A DE19741928 A DE 19741928A DE 19741928 A DE19741928 A DE 19741928A DE 19741928 C1 DE19741928 C1 DE 19741928C1
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semiconductor component
component according
layer
sic
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DE19741928A
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Inventor
Heinz Dr Rer Nat Mitlehner
Michael Dr Phil Stoisiek
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Infineon Technologies AG
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Siemens AG
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Priority to DE19741928A priority Critical patent/DE19741928C1/en
Priority to EP98954124A priority patent/EP1018163A1/en
Priority to KR1020007002556A priority patent/KR20010023873A/en
Priority to JP2000511196A priority patent/JP2001516156A/en
Priority to PCT/DE1998/002625 priority patent/WO1999013512A1/en
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Publication of DE19741928C1 publication Critical patent/DE19741928C1/en
Priority to US09/523,232 priority patent/US6388271B1/en
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Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7436—Lateral thyristors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical

Abstract

In known high voltage smart-power integrated circuits, the power semiconductor component often takes up more than half of the entire chip surface. In order to produce integrated circuits more cost effectively, the consumption of material, especially the drift zone surfaces of power semiconductor components, clearly need to be reduced. Silicon carbide contains an approximately electric breakdown field strength which is ten times higher than that of silicon. The integration of parts of a semiconductor component which receive voltage with silicon carbide enables the production of considerably smaller drift zones which have identical blocking voltage. In a lateral current conducting SiC-MOS-transistor, the SiC layer (6) which is approximately between 1-2 mu m thick and covered by a SiO2 layer (11) is arranged on a Si-substrate (2) in a dielectrically isolated manner. Two respective n<+>-doped SiC areas (7,8) serve as source contacts or drain contacts. The electron conducting channel is formed on the surface of a p<+>-doped area (13) of the SiC layer (6) situated opposite from the gate electrode (14). Said area (13) is connected to the only weak electron conducting SiC drift zone (12).

Description

1. Einleitung und Stand der Technik1. Introduction and state of the art

Eines der wichtigsten Marktsegmente für Smart-Power-IC's sind Motoransteuerungen, in denen unter anderem sogenannte Halb­ brückeninverter zum Einsatz kommen. Da diese Inverter für Spannungen von einigen 100 Volt ausgelegt sein müssen, ver­ wendet man in der Regel lateral stromleitende IGBT's (Insulated-Gate-Bipolar-Transistor) als Schaltelemente. Trotz ihres vergleichsweise kompakten Aufbaus nehmen die IGBT's deutlich mehr als die Hälfte der gesamten Chipfläche des je­ weiligen Halbbrückeninverters ein (s. beispielsweise [1], Fig. 8). Um Halbbrückeninverter und andere Hochvolt-Smart- Power-IC's (Sperrspannung Vbr < 200-600 Volt) kostengünstiger herstellen zu können, müssen die Materialkosten reduziert und damit insbesondere die Flächen der Driftzonen der Leistungs­ halbleiter-Bauelemente des IC's deutlich verringert werden.One of the most important market segments for smart power ICs are motor controls, in which so-called half-bridge inverters are used. Since these inverters have to be designed for voltages of a few 100 volts, laterally current-conducting IGBTs (insulated gate bipolar transistors) are generally used as switching elements. Despite their comparatively compact structure, the IGBTs take up significantly more than half of the total chip area of the respective half-bridge inverter (see, for example, [1], FIG. 8). In order to be able to manufacture half-bridge inverters and other high-voltage smart power ICs (reverse voltage V br <200-600 volts) more cost-effectively, the material costs have to be reduced and in particular the areas of the drift zones of the power semiconductor components of the IC have to be significantly reduced.

Durch Anwendung des aus [2] bekannten Resurf-Prinzips (Reduced Surface Field) läßt sich die Verteilung des elek­ trischen Feldes an der Oberfläche eines Halbleiterbauelements gezielt beeinflussen. Diese Technik ermöglicht die Herstel­ lung kompakt aufgebauter, hochsperrender Bauelemente mit ver­ gleichsweise dünnen, feldaufnehmenden Halbleiterschichten.By using the resurf principle known from [2] (Reduced Surface Field) the distribution of the elec tric field on the surface of a semiconductor device influence specifically. This technique enables the manufacturer compact, high-blocking components with ver equally thin, field-absorbing semiconductor layers.

2. Gegenstand, Ziele und Vorteile der Erfindung2. Object, aims and advantages of the invention

Die Erfindung betrifft ein in lateraler Richtung stromleiten­ des Halbleiterbauelement. Unabhängig von seiner Ausgestaltung als MOS-Transistor, IGBT, Thyristor oder Diode soll seine Driftzone bei einer vorgegebenen Sperrspannung eine wesent­ lich kleinere Fläche beanspruchen als die Driftzone des ent­ sprechenden, aus dem Stand der Technik bekannten Bauelements. Ein Halbleiterbauelement mit den in Patentanspruch 1 ange­ gebenen Merkmalen besitzt diese Eigenschaft. Ausgestaltungen und vorteilhafte Weiterbildungen des erfindungsgemäßen Halb­ leiterbauelements sind Gegenstand der abhängigen Ansprüche.The invention relates to current conducting in the lateral direction of the semiconductor device. Regardless of its design as a MOS transistor, IGBT, thyristor or diode should be Drift zone essential for a given reverse voltage require a smaller area than the drift zone of the ent speaking component known from the prior art. A semiconductor device with the in claim 1 is  given characteristics has this property. Configurations and advantageous developments of the half according to the invention conductor components are the subject of the dependent claims.

Mit Hilfe der Erfindung lassen sich beispielsweise Smart- Power-IC's aufgrund der deutlich kleineren Fläche der Lei­ stungshalbleiter-Bauelemente wesentlich kostengünstiger her­ stellen bzw. eine größere Anzahl von Bauelementen mit dem­ selben Sperrvermögen auf einer kleineren Chipfläche inte­ grieren.With the help of the invention, for example, smart Power ICs due to the significantly smaller area of the Lei semiconductor semiconductors much cheaper make or a larger number of components with the same blocking capacity on a smaller chip area inte freeze.

3. Zeichnungen3. Drawings

Die Erfindung wird im Folgenden anhand der Zeichnungen erläutert. In den Zeichnungen sind Elemente/Komponenten mit gleicher Funktion und/oder Wirkungsweise mit denselben Be­ zugszeichen versehen. Es zeigen:The invention is described below with reference to the drawings explained. Elements / components are included in the drawings same function and / or mode of action with the same loading provide traction marks. Show it:

Fig. 1 ein erstes Ausführungsbeispiel eines SiC-MOS- Transistors in Draufsicht und im Querschnitt, Fig. 1 shows a first embodiment of a SiC MOS transistor in plan view and in cross-section,

Fig. 2 ein zweites Ausführungsbeispiel eines SiC-MOS- Transistors in Draufsicht und im Querschnitt, Fig. 2 shows a second embodiment of a SiC MOS transistor in plan view and in cross-section,

Fig. 3 ein Ausführungsbeispiel eines IGBT's; FIG. 3 shows an embodiment of an IGBT;

Fig. 4 ein Ausführungsbeispiel eines Thyristors; Fig. 4 shows an embodiment of a thyristor;

Fig. 5 ein Ausführungsbeispiel einer Diode; FIG. 5 shows an embodiment of a diode;

Fig. 6 die jeweilige Halbleiterstruktur nach Ausführung einzelner Schritte eines Verfahrens zur Herstellung des in Fig. 1 dargestellten SiC-MOS-Transistors. Fig. 6 shows the respective semiconductor structure after execution of individual steps of a method for manufacturing the SiC-MOS transistor shown in FIG. 1.

4. Beschreibung der Ausführungsbeispiele4. Description of the embodiments a) Erstes Ausführungsbeispiel eines SiC-MOS-Transistorsa) First embodiment of a SiC-MOS transistor

Der in Fig. 1 nicht maßstabsgetreu dargestellte SiC-MOS- Transistor ist bezüglich der senkrecht auf einer Hauptfläche 1 des Substrats 2 stehenden Achse 3 spiegelsymmetrisch aufge­ baut, wobei eine thermisch gewachsene, typischerweise 1-3 µm dicke SiO2-Schicht 4 den in lateraler Richtung stromleitenden MOS-Transistor vom p+-dotierten Si-Substrat 2 (Dotierstoff­ konzentration < 1018-1019 cm-3) dielektrisch isoliert. Die Dicke dSiC der die SiO2-Schicht 4 teilweise abdeckenden und von einer SiO2-Zone 5 randseitig begrenzten SiC-Schicht 6 beträgt beispielsweise dSiC ≦ 1-2 µm. Die SiC-Schicht 6 weist zwei jeweils n+-dotierte Bereiche 7/8 (Dotierstoffkonzentra­ tion < 1018 cm-3) auf, wobei eine Source-Elektrode 9 den äußeren Bereich 7 und eine Drain-Elektrode 10 den inneren Bereich 8 kontaktiert. Zwischen dem sourceseitigen Bereich 7 und der nur schwach elektronenleitenden, von einer SiO2-Iso­ latorschicht 11 ("Zwischenoxyd") abgedeckten Driftzone 12 liegt ein p+-dotierter Bereich 13 (Dotierstoffkonzentration ≈ 1017 cm-3). Ihm zugeordnet ist die in die Isolatorschicht 11 eingebettete und über Kontaktlöcher mit Leiterbahnanschlüssen verbundene Gate-Elektrode 14. Die beispielsweise aus poly­ kristallinem Silizium gefertigte Gate-Elektrode 14 überdeckt sowohl den p+-dotierten Bereich 13 als auch einen Teil der angrenzenden Driftzone 12. Beaufschlagt man die Gate-Elektro­ de 14 mit einem positiven Potential, verarmt der p-leitende Bereich 13. Gleichzeitig bildet sich an seiner gateseitigen Oberfläche ein n-leitender Kanal, über den die Elektronen von der Source-Elektrode 9 in die Driftzone 12 und weiter zur Drain-Elektrode 10 strömen, sobald die zwischen Source- und Drain-Elektrode 9/10 aufgebaute Potentialdifferenz die bau­ elementspezifische Einsatzspannung übersteigt. Im Bereich der Driftzone 12 fließt der Strom somit in der durch die Pfeile angedeuteten lateralen Richtung durch den SiC-MOS-Transistor.The SiC-MOS transistor not shown to scale in FIG. 1 is mirror-symmetrical with respect to the axis 3 which is perpendicular to a main surface 1 of the substrate 2 , a thermally grown, typically 1-3 μm thick SiO 2 layer 4 being laterally direction current-conducting MOS transistor of the p + -doped Si substrate 2 (dopant concentration <10 18- 10 19 cm -3) is isolated dielectrically. The thickness d SiC of the SiC layer 6 , which partially covers the SiO 2 layer 4 and is delimited by an SiO 2 zone 5, is, for example, d SiC ≦ 1-2 μm. The SiC layer 6 has two each on n + doped regions 7/8 (Dotierstoffkonzentra tion <10 18 cm -3), a source electrode 9 contacted the outer region 7 and a drain electrode 10 to the inner region. 8 A p + -doped region 13 (dopant concentration ≈ 10 17 cm -3 ) lies between the source-side region 7 and the only weakly electron-conducting drift zone 12 covered by an SiO 2 insulator layer 11 (“intermediate oxide”). Associated with it is the gate electrode 14 embedded in the insulator layer 11 and connected to conductor track connections via contact holes. The gate electrode 14 , for example made of polycrystalline silicon, covers both the p + -doped region 13 and part of the adjacent drift zone 12 . If the gate electrode de 14 is subjected to a positive potential, the p-type region 13 becomes impoverished. At the same time forms at its gate side surface of an n-type channel, flow through which the electrons from the source electrode 9 in the drift region 12 and to the drain electrode 10 as soon as the established between source and drain electrode 9/10 potential difference the construction element-specific operational voltage exceeds. In the area of the drift zone 12 , the current thus flows through the SiC-MOS transistor in the lateral direction indicated by the arrows.

Die im unteren Teil der Fig. 1 punktiert dargestellten Linien 15 markieren Orte jeweils gleichen Potentials inner­ halb des in Sperrichtung gepolten SiC-MOS-Transistors. Da die Source-Elektrode 9 und das Substrat 2 auf demselben Potential liegen, verlaufen die Äquipotentiallinien 15 in der SiO2- Schicht 4 annähernd parallel zur Hauptfläche 1 des Substrats 2. Am stärksten elektrisch belastet ist der unmittelbar unterhalb der Drain-Elektrode 10 liegende Bereich der SiO2- Schicht 4. Toleriert man in diesem Bereich der beispielsweise dox = 3 µm dicken SiO2-Schicht 4 noch eine elektrische Feld­ stärke von Emax(SiO2) ≈ 2 MV/cm = 200 V/µm, darf die Sperr­ spannung maximal Vbr = 600 V betragen.The lines 15 shown in dotted lines in the lower part of FIG. 1 mark locations of the same potential within the reverse polarity of the SiC-MOS transistor. Since the source electrode 9 and the substrate 2 are at the same potential, the equipotential lines 15 in the SiO 2 layer 4 run approximately parallel to the main surface 1 of the substrate 2 . The area of the SiO 2 layer 4 located directly below the drain electrode 10 is most strongly electrically charged. If one tolerates an electric field strength of E max (SiO 2 ) ≈ 2 MV / cm = 200 V / µm in this area, for example d ox = 3 µm thick SiO 2 layer 4 , the blocking voltage may not exceed V br = 600 V.

Aufgrund der im Vergleich zu Silizium etwa 10-fach höheren elektrischen Durchbruchfeldstärke des SiC, liegt die Breite ld der die Sperrspannung Vbr = 600 Volt aufnehmenden Driftzone 12 mit ld < 3 µm deutlich unterhalb des in einem entsprechen­ den Si-MOS-Transistor erforderlichen Wertes (ld(Si) ≈ Vbr/Ebr(Si) = 30 µm; Ebr(Si) = 2 . 105 V/cm: = elektrische Durch­ bruchfeldstärke Si). Die Dotierung der Driftzone 12 ist so gewählt, daß das Produkt ND . dSiC (ND: = Dotierstoffkonzentra­ tion, dSiC: = Dicke der SiC-Schicht 6) zumindest nährungsweise dem Wert ND . dSiC ≈ 3 × 1013 cm2 entspricht. Dies gewährlei­ stet, daß die Diftzone 12 sehr schnell an Ladungsträgern ver­ armt und die elektrische Feldstärke im gesperrten Zustand des SiC-MOS-Transistors über die gesamte Breite ld der Diftzone 12 annähernd konstant ist.Due to the approximately 10 times higher electrical breakdown field strength of the SiC compared to silicon, the width l d of the drift zone 12 receiving the blocking voltage V br = 600 volts with l d <3 μm is clearly below that in a corresponding Si-MOS transistor required value (l d (Si) ≈ V br / E br (Si) = 30 µm; E br (Si) = 2.10 5 V / cm: = electrical breakdown strength Si). The doping of the drift zone 12 is selected so that the product N D. d SiC (N D : = dopant concentration, d SiC : = thickness of the SiC layer 6 ) at least approximately the value N D. d corresponds to SiC ≈ 3 × 10 13 cm 2 . This ensures that the drift zone 12 is very quickly depleted of charge carriers and the electric field strength in the blocked state of the SiC-MOS transistor is approximately constant over the entire width l d of the drift zone 12 .

Wie in Fig. 1 angedeutet, können die in einem Hochvolt- Smart-Power-IC vorhandenen weiteren Bauelemente in den nicht von der SiC-Schicht 6 abgedeckten Bereich des Si-Substrats 2 integriert und über Leiterbahnmetallisierungen untereinander sowie mit den Anschlüssen des SiC-MOS-Transistors verbunden werden. Bei dem im linken Teil dargestellten Bauelement han­ delt es sich um einen konventionellen Si-MOS-Transistor mit einer in die SiO2-Schicht 4 eingebetteten Gate-Elektrode 16 und zwei im Substrat 2 beabstandet voneinander angeordneten, jeweils n+-dotierten Bereichen 17/18.As indicated in FIG. 1, the further components present in a high-voltage smart power IC can be integrated in the region of the Si substrate 2 not covered by the SiC layer 6 and via interconnect metallizations with one another and with the connections of the SiC-MOS -Transistors are connected. The component shown in the left part is a conventional Si-MOS transistor with a gate electrode 16 embedded in the SiO 2 layer 4 and two n + -doped regions 17 / spaced apart from one another in the substrate 2. 18th

b) Zweites Ausführungsbeispiel eines SiC-MOS-Transistorsb) Second embodiment of a SiC-MOS transistor

Elektronen besitzen in SiC eine deutlich kleinere Beweglich­ keit als in Silizium, was sich nachteilig auf den Einschalt­ widerstand des entsprechenden SiC-Bauelements auswirkt. Da insbesondere hochsperrende MOS-Transistoren einen möglichst kleinen Einschaltwiderstand aufweisen sollten, wird vorge­ schlagen, nur den spannungsaufnehmenden Teil des Transistors in SiC, den gategesteuerten Kanalbereich hingegen in Si zu realisieren. Die Fig. 2 zeigt das entsprechende, aus einem Si-MOSFET und einer SiC-Driftstrecke bestehende Bauelement in Draufsicht und im Querschnitt.Electrons have a significantly smaller mobility in SiC than in silicon, which has a disadvantageous effect on the on-resistance of the corresponding SiC component. Since, in particular, high-blocking MOS transistors should have a turn-on resistance that is as small as possible, it is proposed to implement only the voltage-absorbing part of the transistor in SiC, and the gate-controlled channel region in Si. Fig. 2 shows the corresponding, consisting of a Si-MOSFET and a SiC drift component in plan view and in cross section.

Das in der z-x-Ebene fingerförmig ausgebildete Bauelement ist wieder spiegelsymmetrisch bezüglich der mit 3 bezeichneten Achse aufgebaut. Gesteuert durch das Potential der in die SiO2-Schicht 4 eingebetteten Gate-Elektrode 14 bildet sich der elektronenleitende Kanal an der Oberfläche des p-leiten­ den Si-Substrats 2 zwischen den beiden jeweils n+-dotierten Bereichen 19/20. Die den Bereich 20 kontaktierende Source- Elektrode 9 ist leitend mit dem p-dotierten, sourceseitigen Bereich 13 der dielektrisch isoliert auf dem Substrat 2 ange­ ordneten SiC-Schicht 6 verbunden, wobei die Source-Elektrode 9 gleichzeitig den ersten Hauptstromkontakt des Bauelements bildet. In lateraler Richtung schließt sich dem sourceseiti­ gen Bereich 13 die die Sperrspannung aufnehmende, schwach elektronenleitende SiC-Driftzone 12 und der p+-dotierte, von der Drain-Elektrode 10 kontaktierte SiC-Bereich 8 an. Die Drain-Elektrode 10 bildet hierbei den zweiten Hauptstromkon­ takt des Bauelements.The finger-shaped component in the zx plane is again mirror-symmetrical with respect to the axis labeled 3 . Controlled by the potential of the embedded into the SiO 2 layer 4 gate electrode 14, the electron-conducting channel formed on the surface of the p-direct the Si substrate 2 between the two in each case n + doped regions 19/20. The source electrode 9 contacting the region 20 is conductively connected to the p-doped, source-side region 13 of the SiC layer 6 which is arranged in a dielectric manner on the substrate 2 , the source electrode 9 simultaneously forming the first main current contact of the component. In the lateral direction, the source side region 13 is followed by the weakly electron-conducting SiC drift zone 12 , which absorbs the reverse voltage, and the p + -doped SiC region 8, which is contacted by the drain electrode 10 . The drain electrode 10 forms the second Hauptstromkon clock of the device.

Wie schematisch in der Draufsicht dargestellt, besteht der sourceseitige Bereich 13 der SiC-Schicht 6 aus einer Viel­ zahl, in z-Richtung beabstandet voneinander angeordneter, p+- dotierter Teilbereiche 13', wobei zwischen benachbarten Teil­ bereichen 13' jeweils ein n+-dotierter SiC-Anschlußbereich 21 (Dotiertstoffkonzentration ≈ 1018-1019 cm-3) angeordnet ist. Während die p+-dotierten Teilbereiche 13' über ein kamm­ förmiges Leiterbahnsystem 22 mit der Source-Elektrode 9 in Verbindung stehen, werden die n+-dotierten Anschlußbereiche 21 von der dem Bereich 19 des Si-MOS-Transistors zugeordneten Kammelektrode 23 kontaktiert.As schematically illustrated in the plan view, is composed of the source-side portion 13 of the SiC layer 6 of a plurality, in the z-direction spaced from each other arranged, p + - doped portions 13 ', wherein between adjacent portions 13' are each a n + - SiC doped terminal region 21 (doped concentration ≈ 10 18- 10 19 cm -3) is disposed. While the p + -doped partial areas 13 'are connected to the source electrode 9 via a comb-shaped conductor track system 22 , the n + -doped connection areas 21 are contacted by the comb electrode 23 assigned to the area 19 of the Si-MOS transistor.

c) Ausführungsbeispiele eines IGBT's, eines Thyristors und einer Diodec) embodiments of an IGBT, a thyristor and a diode

Der in Fig. 3 im Querschnitt dargestellte, spiegelsymme­ trisch bezüglich der Achse 3 aufgebaute IGBT unterscheidet sich im wesentlichen nur dadurch von dem im Abschnitt a) beschriebenen SiC-MOS-Transistor, daß die Drain-Elektrode 10 einen p+-dotierten Bereich 24 (Dotiertstoffkonzentration 1018-1019 cm-3) der SiC-Schicht 6 kontaktiert und diesem Bereich 24 ein als Antipunchzone dienender, n-dotierter Be­ reich 25 (Dotiertstoffkonzentration ≈ 1016-1017 cm-3) vorge­ lagert ist. In Durchlaßrichtung gepolt, fließen die Elektro­ nen von der Source-Elektrode 9 in den n+-dotierten Bereich 7, über den sich an der gateseitigen Oberfläche des p-dotierten Bereichs 13 ausbildenden Kanal in die schwach elektronen­ leitende SiC-Driftzone 12, in Pfeilrichtung weiter zu dem n­ dotierten Bereich 25, dem p-dotierten Bereich 24 und schließ­ lich über die Drain-Elektrode 10 ab. Die Gate-Elektrode 14 ist wieder in die die Driftzone 12 abdeckende SiO2-Schicht 11 eingebettet und oberhalb des sourceseitigen, p+-dotierten Be­ reichs 13 angeordnet. Das mit einer SiO2-Schicht 4 versehene Substrat 2 besteht aus p+-dotierten Silizium.The IGBT constructed in cross section in FIG. 3, mirror symmetrical with respect to the axis 3 , differs essentially only from the SiC-MOS transistor described in section a) in that the drain electrode 10 has a p + -doped region 24 ( doped substance concentration 10 18 10 19 cm contacted -3) of the SiC layer 6 and this portion 24 a serving as an anti-punch zone, n-doped be rich 25 (doped concentration ≈ 10 16- 10 17 cm -3) upstream is. Poled in the forward direction, the electrons flow from the source electrode 9 into the n + -doped region 7 , via the channel forming on the gate-side surface of the p-doped region 13 into the weakly electron-conducting SiC drift zone 12 , in the direction of the arrow further to the n-doped region 25 , the p-doped region 24 and finally via the drain electrode 10 . The gate electrode 14 is again embedded in the drift zone 12 covering SiO 2 layer 11 and arranged above the source-side, p + -doped region 13 . The substrate 2 provided with an SiO 2 layer 4 consists of p + -doped silicon.

Analog wie beim SiC-MOS-Transistor ist es auch beim IGBT möglich, nur den spannungsaufnehmenden Teil in SiC, den gategesteuerten Kanalbereich hingegen in Si zu realisieren (nicht dargestellt, vgl. Fig. 2).Analogously to the SiC-MOS transistor, it is also possible with the IGBT to implement only the voltage-absorbing part in SiC and the gate-controlled channel region in Si (not shown, see FIG. 2).

Die auf der SiO2-Schicht 4 des p+-dotierten Si-Substrats 2 angeordnete SiC-Schicht 6 des in Fig. 4 im Querschnitt dargestellten Thyristors weist in lateraler Richtung diesel­ be Folge von Bereichen 7/13/12/25/24 unterschiedlicher Leit­ fähigkeit auf wie die SiC-Schicht 6 des oben beschriebenen IGBT's, wobei eine SiO2-Schicht 11 wieder die zwischen einem p-dotierten, von einer Gate-Elektrode 14' kontaktierten Be­ reich 13 und dem n-dotierten Bereich 25 angeordnete, schwach elektronenleitende Driftzone 12 abdeckt. Der n+-dotierte Be­ reich 7 ist mit einer als Kathode dienenden Metallisierung 26, der p+-dotierte Bereich 24 mit einer Anodenmetallisierung 27 versehen.The p + on the SiO 2 layer 4 doped Si substrate 2 arranged SiC layer 6 of in Fig. 4 shown in cross-section thyristor comprises in the lateral direction diesel be result of areas 7/13/12/25/ 24 different Conductivity on like the SiC layer 6 of the IGBT described above, an SiO 2 layer 11 again being the weakly arranged between a p-doped area 13 contacted by a gate electrode 14 'and the n-doped area 25 covers electron-conducting drift zone 12 . The n + -doped region 7 is provided with a metallization 26 serving as a cathode, the p + -doped region 24 is provided with an anode metallization 27 .

Den einfachsten Aufbau der erfindungsgemäßen Halbleiterbau­ elemente besitzt die in Fig. 5 im Querschnitt dargestellte SiC-Diode. Sie besteht im wesentlichen aus einem mit einer SiO2-Passivierung 4 versehenen, p+-dotierten Si-Substrat 2, einer auf der SiO2-Schicht 4 angeordneten SiC-Schicht 6, so­ wie einer die SiC-Schicht 6 teilweise abdeckenden SiO2- Schicht 11. Die feldaufnehmende, schwach elektronenleitende SiC-Driftzone 12 ist zwischen einem mit einer Kathodenmetal­ lisierung 27 versehenen, n+-dotierten Bereich 24 und einem mit einer Anodenmetallisierung 26 versehenen, p+-dotierten Bereich 7 angeordnet.The simplest structure of the semiconductor components according to the invention has the SiC diode shown in cross section in FIG. 5. It essentially consists of a p + -doped Si substrate 2 provided with an SiO 2 passivation 4 , an SiC layer 6 arranged on the SiO 2 layer 4 , and an SiO 2 partially covering the SiC layer 6 - Layer 11 . The field-absorbing, weakly electron-conducting SiC drift zone 12 is arranged between a n + -doped region 24 provided with a cathode metalization 27 and a p + -doped region 7 provided with an anode metallization 26 .

d) Verfahren zur Herstellung eines SiC-MOS-Transitorsd) Method for producing an SiC-MOS transistor

Ausgangspunkt des anhand der Fig. 6 erläuterten Verfahrens zur Herstellung des in Fig. 1 dargestellten MOS-Transistors sind ein mit einer thermisch gewachsenen SiO2-Schicht 4 ver­ sehenes, p+-dotiertes Si-Substrat 2 und ein beispielsweise (1 0 0)-orientiertes Si-Substrat 28, auf dessen Oberfläche eine etwa 1-2 µm dicke SiC-Schicht 6, insbesondere durch An­ wendung der in [3] beschriebenen Technik unter Atmosphären­ druck aus der Gasphase abgeschieden wurde. Beide Substrate 2/28 verbindet man derart miteinander (Direct-Wafer-Bonding), daß die SiC-Schicht 6 auf der SiO2-Passivierung 4 des hochdo­ tierten Substrats 2 zu liegen kommt (s. Fig. 6b). Anschließ­ end wird das als Trägermaterial für das SiC dienende Si durch Anwendung einer Folge von Schleif-, Läpp- und Ätzschritten vollständig entfernt. Nach Ausführung eines Trockenätz­ schrittes erhält man den in Fig. 6c dargestellten Halblei­ terkörper, dessen SiC-Schicht 6 entsprechend der verwendeten SiO2-Ätzmaske strukturiert ist. Anschließend werden die erforderlichen n+-, p- und p+-Implantationen zur Definition der Source- und Drainbereiche 7/13/8 durchgeführt (s. Fig. 6d), das MOS-Gateoxid sowie die Gate-Elektrode 14 erzeugt, ein Zwischenoxid 11 aufgebracht, Kontaktlöcher geätzt sowie die Leiterbahn-/Elektrodenmetallisierungen 9/10 aufgebracht und strukturiert (s. auch den Abschnitt "Process Flow" in [1]).The starting point of the method for producing the MOS transistor shown in FIG. 1 explained with reference to FIG. 6 is a p + -doped Si substrate 2 provided with a thermally grown SiO 2 layer 4 and an example (1 0 0) -oriented Si substrate 28 , on the surface of which an approximately 1-2 μm thick SiC layer 6 was deposited, in particular by applying the technique described in [3] from the gas phase under atmospheric pressure. Both substrates 2/28 is associated in such a manner (Direct wafer bonding), that the SiC layer 6 comes to lie on the SiO 2 passivation 4 of the hochdo oriented substrate 2 (see. Fig. 6b). Finally, the Si serving as the carrier material for the SiC is completely removed by using a sequence of grinding, lapping and etching steps. After carrying out a dry etching step, the semiconductor body shown in FIG. 6c is obtained, the SiC layer 6 of which is structured in accordance with the SiO 2 etching mask used. Then the required n + - (s. Fig 6d.), P- and p + implantations to define the source and drain regions 7/13/8 thereof, the MOS gate oxide and the gate electrode 14 generates an intermediate oxide 11 is applied, contact holes are etched, and the applied printed conductor / electrode metallizations 9/10 and patterned (s. also the "Process flow" section in [1]).

In entsprechender Weise lassen sich auch die in den Fig. 2 bis 5 dargestellten Halbleiterbauelemente herstellen, wobei man das SiC beispielsweise auch durch das eine hohe elek­ trische Durchbruchfeldstärke aufweisende GaAs ersetzen kann.The semiconductor components shown in FIGS . 2 to 5 can also be produced in a corresponding manner, wherein the SiC can also be replaced, for example, by the GaAs having a high electrical breakdown field strength.

5) Literatur5) literature

[1] M. Stoisiek et al, "A Dielectric Isolated High-Voltage IC-Technology For Off-Line Applications", Proc. 1995 Int. Symposium on Power Semiconductor Devices & IC's, Yokohama (1995), pp. 325-329;
[2] J. A. Appels and H. M. J. Vaes, "High Voltage thin layer Devices (Resurf devices), IEDM Tech. Dig., 1979, p. 238;
[3] C. A. Zorman et al, "Epitaxial growth of 3C-SiC films on 4 in. diam. (100) silicon wafers by atmospheric pressure chemical vapor deposition", J. Appl. Phys. 78 ([1] M. Stoisiek et al, "A Dielectric Isolated High-Voltage IC Technology For Off-Line Applications", Proc. 1995 Int. Symposium on Power Semiconductor Devices &IC's, Yokohama (1995), pp. 325-329;
[2] JA Appels and HMJ Vaes, "High Voltage thin layer Devices (Resurf devices), IEDM Tech. Dig., 1979, p. 238;
[3] CA Zorman et al, "Epitaxial growth of 3C-SiC films on 4 in. Diam. (100) silicon wafers by atmospheric pressure chemical vapor deposition", J. Appl. Phys. 78 (

88th

), 1995, pp. 5136-5138.), 1995, pp. 5136-5138.

Claims (17)

1. Halbleiterbauelement mit den folgenden Merkmalen:
  • a) Es weist ein mit einer ersten Isolatorschicht (4)versehenes und aus einem ersten Halbleitermaterial bestehendes Sub­ strat (2) auf;
  • b) zumindest ein Teil der Oberfläche der ersten Isolator­ schicht (4) ist mit einer aus einem zweiten Halbleiter­ material bestehenden zweiten Schicht (6) abgedeckt, wobei die elektrische Druchbruchsfeldstärke des zweiten Halb­ leitermaterials größer ist als die elektrische Durchbruchs­ feldstärke des ersten Halbleitermaterials;
  • c) die zweite Schicht (6) ist in einer ersten lateralen Richtung derart aufgebaut, daß zwischen einem von einer ersten Elektrode (9, 14', 26) kontaktierten ersten Bereich (7, 13) eines ersten Leitfähigkeitstyps und einem von einer zweiten Elektrode (10, 27) kontaktierten zweiten Bereich (8, 24) eines zweiten Leitfähigkeitstyps eine von einer zweiten Isolatorschicht (11) abgedeckte Driftzone (12) des ersten oder zweiten Leitfähigkeitstyps angeordnet ist.
1. Semiconductor component with the following features:
  • a) It has a with a first insulator layer ( 4 ) and consisting of a first semiconductor material substrate ( 2 );
  • b) at least part of the surface of the first insulator layer ( 4 ) is covered with a second layer ( 6 ) consisting of a second semiconductor material, the electrical breakdown field strength of the second semiconductor material being greater than the electrical breakdown field strength of the first semiconductor material;
  • c) the second layer ( 6 ) is constructed in a first lateral direction such that between a first region ( 7 , 13 ) of a first conductivity type contacted by a first electrode ( 9 , 14 ', 26 ) and one by a second electrode ( 10 , 27 ) contacted second region ( 8 , 24 ) of a second conductivity type, a drift zone ( 12 ) of the first or second conductivity type covered by a second insulator layer ( 11 ) is arranged.
2. Halbleiterbauelement nach Anspruch 1, dadurch gekennzeichnet, daß es bezüglich einer senkrecht auf einer Hauptfläche (1) des Substrats (2) stehenden Achse (3) spiegelsymmetrisch aufgebaut ist.2. Semiconductor component according to claim 1, characterized in that it is constructed mirror-symmetrically with respect to an axis ( 3 ) which is perpendicular to a main surface ( 1 ) of the substrate ( 2 ). 3. Halbleiterbauelement nach Anspruch 2, dadurch gekennzeichnet, daß der achsenfernere erste oder zweite Bereich (7) von einer isolierenden Randzone (5) begrenzt ist. 3. A semiconductor component according to claim 2, characterized in that the first or second region ( 7 ) further from the axis is delimited by an insulating edge zone ( 5 ). 4. Halbleiterbauelement nach einem der Ansprüche 1-3, dadurch gekennzeichnet, daß ein dritter Bereich (13) des ersten oder zweiten Leitfähigkeitstyps zwischen dem ersten oder zweiten Bereich (7) und der Driftzone (12) angeordnet ist, wobei der dritte Bereich (13) und der unmittelbar angrenzende erste oder zweite Bereich (7) vom entgegengesetzten Leitfähigkeitstyps sind.4. Semiconductor component according to one of claims 1-3, characterized in that a third region ( 13 ) of the first or second conductivity type is arranged between the first or second region ( 7 ) and the drift zone ( 12 ), the third region ( 13 ) and the immediately adjacent first or second region ( 7 ) are of the opposite conductivity type. 5. Halbleiterbauelement nach Anspruch 4, dadurch gekennzeichnet, daß die Driftzone (12) zwischen dem dritten Bereich (13) und einem vierten Bereich (25) des ersten oder zweiten Leitfähig­ keitstyps angeordnet ist, wobei der dritte und der vierte Bereich (13, 25) vom entgegengesetzten Leitfähigkeitstyp sind.5. Semiconductor component according to claim 4, characterized in that the drift zone ( 12 ) between the third region ( 13 ) and a fourth region ( 25 ) of the first or second conductivity type is arranged, wherein the third and fourth regions ( 13 , 25th ) are of the opposite conductivity type. 6. Halbleiterbauelement nach einem der Ansprüche 1-3, dadurch gekennzeichnet, daß der erste und der zweite Bereich (7, 24) vom selben Leit­ fähigkeitstyp sind.6. Semiconductor component according to one of claims 1-3, characterized in that the first and the second region ( 7 , 24 ) are of the same conductivity type. 7. Halbleiterbauelement nach Anspruch 4 oder 5, dadurch gekennzeichnet, daß eine Steuerelektrode (14, 14') den dritten Bereich (13) kontaktiert oder isoliert oberhalb des dritten Bereichs (13) angeordnet ist.7. Semiconductor component according to claim 4 or 5, characterized in that a control electrode ( 14 , 14 ') contacts the third region ( 13 ) or is arranged insulated above the third region ( 13 ). 8. Halbleiterbauelement nach Anspruch 7, dadurch gekennzeichnet, daß die Steuerelektrode (14) in die zweite Isolatorschicht (11) eingebettet ist. 8. A semiconductor device according to claim 7, characterized in that the control electrode ( 14 ) is embedded in the second insulator layer ( 11 ). 9. Halbleiterbauelement nach Anspruch 7 oder 8, dadurch gekennzeichnet, daß die isoliert angeordnete Steuerelektrode (14) den dritten Bereich (13) vollständig und einen sich unmittelbar an den dritten Bereich (13) anschließenden Teil der Driftzone (12) überdeckt.9. A semiconductor device according to claim 7 or 8, characterized in that the isolated arranged control electrode (14), the third region (13) completely and a directly adjoining the third region (13) part of the drift region (12) covers. 10. Halbleiterbauelement nach einem der Ansprüche 7-9, dadurch gekennzeichnet, daß die erste oder zweite Elektrode (9, 10) die Steuer­ elektrode (14) sowie einen Teil der Driftzone (12) überdeckt.10. Semiconductor component according to one of claims 7-9, characterized in that the first or second electrode ( 9 , 10 ), the control electrode ( 14 ) and part of the drift zone ( 12 ) covers. 11. Halbleiterbauelement nach einem der Ansprüche 1-10, gekennzeichnet durch ein mit der ersten oder zweiten Elektrode (9, 10) leitend verbundenes Steuerelement (9, 14, 19, 20, 23), wobei das Steuerelement (9, 14, 19, 20, 23) in einem nicht von der zweiten Schicht (6) abgedeckten Teil des Substrats (2) angeordnet ist.11. The semiconductor component as claimed in one of claims 1-10, characterized by a control element ( 9 , 14 , 19 , 20 , 23 ) which is conductively connected to the first or second electrode ( 9 , 10 ), the control element ( 9 , 14 , 19 , 20 , 23 ) is arranged in a part of the substrate ( 2 ) not covered by the second layer ( 6 ). 12. Halbleiterbauelement nach Anspruch 11, gekennzeichnet durch eine MOS-Struktur als Steuer­ element.12. The semiconductor component according to claim 11, characterized by a MOS structure as a tax element. 13. Halbleiterbauelement nach Anspruch 11 oder 12, dadurch gekennzeichnet,
daß der steuerelementseitige erste oder zweite Bereich (13) eine Vielzahl von Teilbereichen (13') des entsprechenden Leitfähigkeitstyps aufweist,
daß die Teilbereiche (13') in einer zur ersten lateralen Richtung orthogonalen zweiten lateralen Richtung beabstandet voneinander angeordnet sind,
daß benachbarte Teilbereiche (13') jeweils durch einen Kontaktbereich (21) entgegengesetzten Leitfähigkeitstyps getrennt sind und
daß die Teilbereiche (13') jeweils mit einem ersten Anschluß (9) des Steuerelements (4, 14, 19, 20, 23) und die Kontakt­ bereiche (21) jeweils mit einem zweiten Anschluß (23) des Steuerelements (4, 14, 19, 20, 23) leitend verbunden sind.13. Semiconductor component according to claim 11 or 12, characterized in that
that the first or second region ( 13 ) on the control element side has a multiplicity of partial regions ( 13 ') of the corresponding conductivity type,
that the partial regions ( 13 ') are arranged at a distance from one another in a second lateral direction orthogonal to the first lateral direction,
that adjacent sections ( 13 ') are each separated by a contact area ( 21 ) of opposite conductivity type and
that the partial areas ( 13 ') each have a first connection ( 9 ) of the control element ( 4 , 14 , 19 , 20 , 23 ) and the contact areas ( 21 ) each have a second connection ( 23 ) of the control element ( 4 , 14 , 19 , 20 , 23 ) are conductively connected. 14. Halbleiterbauelement nach Anspruch 13, dadurch gekennzeichnet, daß jeweils eine kammförmige Elektrode (22, 23) die Teilbe­ reiche (13') und die Kontaktbereiche (21) kontaktiert.14. Semiconductor component according to claim 13, characterized in that a comb-shaped electrode ( 22 , 23 ) the Teilbe rich ( 13 ') and the contact areas ( 21 ) contacted. 15. Halbleiterbauelement nach einem der Ansprüche 1-14, dadurch gekennzeichnet, daß die zweite Schicht (6) aus Siliziumkarbid oder Gallium­ arsenid besteht.15. Semiconductor component according to one of claims 1-14, characterized in that the second layer ( 6 ) consists of silicon carbide or gallium arsenide. 16. Halbleiterbauelement nach einem der Ansprüche 1-15, gekennzeichnet durch ein Siliziumsubstrat (2).16. Semiconductor component according to one of claims 1-15, characterized by a silicon substrate ( 2 ). 17. Halbleiterbauelement nach einem der Ansprüche 1-16, dadurch gekennzeichnet, daß das Produkt aus der Dotierung ND und der Dicke d der zweiten Schicht (6) im Bereich der Driftzone (12) der Bedingung ND . d ≈ 1 - 5 . 1013 cm-2 genügt.17. Semiconductor component according to one of claims 1-16, characterized in that the product of the doping N D and the thickness d of the second layer ( 6 ) in the region of the drift zone ( 12 ) of the condition N D. d ≈ 1-5. 10 13 cm -2 is sufficient.
DE19741928A 1997-09-10 1997-09-23 Semiconductor component e.g. silicon carbide MOS transistor for smart power integrated circuit Expired - Lifetime DE19741928C1 (en)

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DE19741928A DE19741928C1 (en) 1997-09-10 1997-09-23 Semiconductor component e.g. silicon carbide MOS transistor for smart power integrated circuit
EP98954124A EP1018163A1 (en) 1997-09-10 1998-09-07 Semiconductor component with a drift zone
KR1020007002556A KR20010023873A (en) 1997-09-10 1998-09-07 Semiconductor component with a drift zone
JP2000511196A JP2001516156A (en) 1997-09-10 1998-09-07 Semiconductor components
PCT/DE1998/002625 WO1999013512A1 (en) 1997-09-10 1998-09-07 Semiconductor component with a drift zone
US09/523,232 US6388271B1 (en) 1997-09-10 2000-03-10 Semiconductor component

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999022407A1 (en) * 1997-10-28 1999-05-06 Koninklijke Philips Electronics N.V. Lateral silicon carbide semiconductor device having a drift region with a varying doping level

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5113236A (en) * 1990-12-14 1992-05-12 North American Philips Corporation Integrated circuit device particularly adapted for high voltage applications
US5246870A (en) * 1991-02-01 1993-09-21 North American Philips Corporation Method for making an improved high voltage thin film transistor having a linear doping profile
US5539217A (en) * 1993-08-09 1996-07-23 Cree Research, Inc. Silicon carbide thyristor
KR100355515B1 (en) * 1994-06-01 2002-12-18 코닌클리케 필립스 일렉트로닉스 엔.브이. Semiconductor device provided with a ligbt element
US5877515A (en) * 1995-10-10 1999-03-02 International Rectifier Corporation SiC semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
C.A. Zorman et al, "Epitaxial growth of 3C-SiC films on 4 in. diam. (100) silicon wafers by atmospheric pressure chemical vapor deposition", J. Appl. Phys. 78, (8), 1995, pp 5136-5138 *
J.A. Appels and H.M.J. Vaes, "High Voltage thin layer Devices (Resurf devices), IEDM Techn. Dig., 1979, p. 238 *
M. Stoisiek et al, "A Dielectic Isolated High- Voltage IC-Technology For Off-Line Applications", Proc. 1995 Int. Symposium on Power Semiconductor Devices & IC`s, Yokohama, 1995, pp 325-329 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999022407A1 (en) * 1997-10-28 1999-05-06 Koninklijke Philips Electronics N.V. Lateral silicon carbide semiconductor device having a drift region with a varying doping level

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