DE19741046C1 - Single chip microphone is produced using only three photolithographic masking steps - Google Patents

Abstract

A single chip microphone production process includes only three photolithographic masking steps, masks only being required for forming an opening in a back face SiO2/Si3N4 layer and for structuring a conductive polysilicon layer. Production of a single chip microphone comprises (a) applying a SiO2 layer and then a Si3N4 layer on the front and back faces of a Si substrate (2); (b) applying a spacer layer (8) and a polysilicon layer (10); (c) making the polysilicon layer (10) electrically conductive; (d) opening the back face SiO2/Si3N4 layer (4); (e) applying a Si3N4 layer (14) on the polysilicon layer (10); (f) removing the Si substrate (2) from the back face opening (12); (g) structuring the conductive polysilicon layer (10); (h) contacting the Si3N4 layer (14); and (i) removing the spacer (8). An Independent claim is also included for a single chip microphone produced by the above process.

Description

The invention relates to a method for producing a one-chip microphone.

Miniaturized microphones are of particular interest to the hearing aid industry. In the essay "Subminiature Silicon Condenser Microphone", progress made Akustik, DAGA 1985, pages 847-850, by D. Hohm is a capacitor Microphone in silicon revealed. With this microphone, however, it is disadvantageous that it consists of two chips, a membrane chip and a counter electrode chip, must be put together. It is particularly disadvantageous that a airtight connection between membrane and counter electrode chip created must be, for which an adjustment and a bonding step are necessary. The complicated technology processes with these two-chip microphones increase this Error risk in the manufacture and therefore show only an insufficient reproducibility Availability of such microphones.

One-wafer processes have therefore been developed. With the help of such processes as for example in Proceedings 11th International Congress on Acoustics, Paris, 1983, Vol. 6, pages 29-32 by D. Hohm and G. Sessler, is the Development of a one-chip microphone, see for example P. R. Scheeper,  W. Olthois, P. Bergveld, Proceedings 6th International Conference Solid-State Sensors and Actuaters, San Francisco, USA, June 1991, pages 408-411, been made possible. Such one-chip microphones are advantageous a small number of steps in the manufacturing process and therefore by small Manufacturing costs.

Such a manufacturing process is disclosed, for example, in the article "One-Chip Silicon Condenser Microphone" by C. Thielemann, G. Hess, M. Grabe, J. Glitz in VDI REPORTS No. 1255, 1996. This publication shows the closest state of the art. The publication discloses a method for producing a one-chip microphone, in which an SiO ₂ layer is applied to each of a Si substrate on the front or rear side thereof by means of wet oxidation. An Si ₃ N ₄ layer is then applied to the SiO ₂ layers using APCVD. Then boron is introduced into the front Si ₃ N ₄ layer by means of ion implantation. A spacer layer made of pyrolytic SiO ₂ (Pyrox) is then applied to the front Si ₃ N ₄ layer. This pyrox spacer, which serves as a sacrificial layer, is then structured using a first photolithographic mask. A poly-Si layer is then applied to the pyrox spacer and structured using a second photolithographic mask. A photolithographic mask is then applied to the poly-Si layer and structured. Boron implantation then makes the undoped poly-Si layer electrically conductive in the area which is later to serve as the active area of the microphone.

The rear SiO ₂ / Si ₃ N ₄ layer is then opened by a dry chemical plasma etching process with the aid of a fourth photolithographic mask. A thin Si ₃ N ₄ etching protective layer is then applied to the poly-Si layer, which serves as the counter electrode, as a protective mask for the subsequent etching steps. The Si substrate is then removed using KOH until the etch stop (SiO ₂ ). The remaining SiO ₂ is then removed using buffered HF (BHF). An aluminum mask is then applied to the partially doped poly-Si counterelectrode and structured using a fifth photolithographic mask. Subsequently, the poly-Si counter electrode is structured by means of plasma etching. Finally, the Si ₃ N ₄ layer, which serves as a membrane, is contacted using an aluminum metallization on the back. Finally, the Pyrox spacer is etched away using BHF.

A disadvantage of these known methods is in particular that five photolitho graphic masks must be used.

The object of the present invention is therefore to provide a method for the production to provide a one-chip microphone, which the aforementioned Avoids disadvantages and in particular reliability and reproducibility of the resulting one-chip microphones and increases the time required Manufacturing reduced.

This task is accomplished in a method of the type mentioned by Features of claim 1 solved.

The advantage of the invention is in particular that the number of photolithographic masks is reduced to three. Due to the present invention, photolithographic masks are only required for the manufacture of the one-chip microphone only for the rear opening of the SiO ₂ / Si ₃ N ₄ layer and for the structuring of the electrically conductive poly-Si layer serving as counterelectrode . The reduction in the number of masks also results in a reduction in the number of overall steps in the method according to the invention. This is a considerable simplification of the manufacturing process and thus an increase in reproducibility and a reduction in manufacturing costs.

An advantageous embodiment of the invention is characterized in that the thick thermal oxide has been replaced by low-stress PECVD-SiO ₂ . The stress oxide itself is only very thin and therefore does not play a major role.

It is particularly advantageous if the Si ₃ N ₄ layer is applied by means of APCVD. With the help of this method, the silicon nitride membrane can be produced reliably and reproducibly.

In an advantageous embodiment of the present invention, the spacer layer is formed from SiO ₂ , which was produced using a plasma-assisted CVD process (PECVD-SiO ₂ ). In this way, the mechanical stresses in the spacer can be prevented if it is made from thermal silicon dioxide according to the prior art. In the prior art, these mechanical stresses led to disadvantageous wafer deformations. The PEDVD silicon dioxide is low in stress and therefore advantageously does not cause any wafer deformation.

Another advantageous embodiment of the invention is characterized in that that the spacer layer is removed with the help of 50% hydrofluoric acid (HF). Through the compared to the acids used in the prior art larger etching rate Hydrofluoric acid can increase the etching time by about one compared to the prior art Factor 10 can be shortened. This embodiment is also characterized by an advantageous time saving in the manufacture of the one-chip microphone.

In a further embodiment of the invention, a poly-Si etching protective layer is advantageously applied to the front Si ₃ N ₄ layer after the Si ₃ N ₄ layers have been applied to the SiO ₂ layers. In this way, the Si ₃ N ₄ membrane is effectively protected from the aggressive hydrofluoric acid, which is used to etch the spacer. There is therefore an increase in the reliability and reproducibility of the microphone produced in this way.

In a further advantageous embodiment of the invention, using a after the application of the spacer layer applied photoresist mask and one subsequent etching a number of marks on the wafer upset. With the help of these markings is an advantageous adjustment of the Wafers possible, making the subsequent steps with a higher one Reliability of the microphone thus produced to promote accuracy can be.

In another advantageous embodiment of the invention, the Si substrate is removed by means of KOH up to the SiO ₂ layer serving as an etch stop before the counter electrode is structured. Thus, the problems of the prior art in high-level edge coverage during anisotropic etching of the Si substrate can be avoided.

In a further advantageous embodiment of the invention, according to the Structuring of the poly-Si layer on the front and back of the wafer Protective layer of photoresist applied and the wafer then on 2/3 of the Sawed wafer thickness at regular intervals. With the help of this embodiment can be used to isolate the microphones provided on the wafer Sawing the wafer after the completion of the process steps can be dispensed with, since the Protective varnish serves as protection against saw dust. Thus, the wafer can already go to this Point in time, that is, immediately after the structuring of the poly-Si counterelectrode part of its thickness is sawn and needs after completion of the Her position steps only have to be broken. Because the wafer is only partially through that Sawing the same remains in the network, it can be processed without problems become.  

Another embodiment of the invention has an additional, advantageous drying step after removal of the spacer layer. With the aid of this drying step, which is preferably carried out on the basis of tert-butanol, the sticking of the Si ₃ N ₄ membrane to the counterelectrode, that is to say the so-called sticking, can be successfully avoided. This drying step is preferably carried out with liquid tert-butanol by filling the spacer with it and then subliming the frozen butanol substance out of the solid phase with the aid of an evacuated eczicator.

Another preferred embodiment of the present invention stands out through an additional step by making the structured, electrically conductive Poly-Si layer contact surfaces coated with aluminum and then be structured. In this way there is good ohmic contact with the poly-Si manufactured and good bondability of the electrical connections of the one-chip Microphones advantageously guaranteed.

Further advantageous embodiments, in particular advantageous dimensions The layers and structures of the one-chip microphone are in the subclaims specified.

In the following, the invention will now be described with reference to the accompanying drawings described.

Show it:

Figure 1 shows an embodiment of a process sequence according to the invention in the form of schematic technology step representations.

Fig. 2 is a perspective view of a one-chip microphone with an exemplary embodiment of the method according to the invention;

Fig. 3 is a plan view of a product manufactured according to an embodiment of the method according to the invention one-chip microphone;

Fig. 4 is a plan view are arranged on several, on a chip, according to an embodiment of the method according to the invention produced a one-chip microphone.

Fig. 1 shows an embodiment of an inventive method for manufacturing a one-chip microphone in a representation of a number of technology steps a) to f). In step a), an SiO ₂ layer is applied to the front and the back of an Si substrate 2 by means of dry oxidation. An Si ₃ N ₄ layer is then applied to the SiO ₂ layers using APCVD. Step a) therefore results in a Si substrate 2 on which silicon nitride on stress oxide, that is to say an Si ₃ N ₄ / SiO ₂ mask 4, is located on both sides.

In step b), a poly-Si etching protection layer 6 is applied to the front side of the Si substrate 2 shown at the top in FIG. 1, which is coated with the Si ₃ N ₄ / SiO ₂ layer 4 . A spacer 8 made of PECVD-SiO _{2 is then} applied to the front.

In step c), a layer 10 of undoped poly-Si is applied to the spacer 8 . This layer 10 is then made electrically conductive over the entire area by boron implantation and a subsequent one-hour temperature treatment at 1000 ° C. The result is a doped poly-Si layer 10. Then, with the aid of a first photolithographic mask, the rear SiO ₂ / Si ₃ N ₄ layer 4 is partially opened by a dry chemical plasma etching process. An opening 12 results in the rear SiO ₂ / Si ₃ N ₄ layer 4.

In step d), a thin Si ₃ N ₄ etching protection layer 14 is applied to the front on the poly-Si layer 10 , which serves as the counter electrode. Subsequently, the Si substrate 2 is removed by means of KOH up to the side of the Si ₃ N ₄ / SiO ₂ masking 4 , which serves as an etching stop and is made of SiO ₂ and faces the Si substrate 2 . This results in a recess 15 in the Si substrate 2.

In step e), the doped poly-Si layer 10 serving as counterelectrode is structured by means of plasma etching with the aid of an approximately 2 μm thick photoresist mask. This results in a patterned poly-Si layer 16. This structured, serving as a poly-Si counter electrode poly-Si layer 16 has perpendicular to the wafer surface a number of regularly arranged side by side, the entire layer penetrating holes 17. These holes 17 are only provided in the region of the recess 15 in the Si substrate 2 . At the edge of the poly-Si layer 16 , the layer 16 remains unstructured. These areas of the poly-Si layer 16 are not above the recess 15 in the Si substrate 2 , but in the transition region between the recess 15 and the bulk region of the Si substrate 2.

In an intermediate step, not shown, a protective lacquer can now be applied Front and back of the wafer processed up to this point can be applied and then the wafer is sawn to 2/3 of the wafer thickness at regular intervals become. The saw lines are arranged such that between them a single-chip microphone can be accommodated. Following the manufacturing process of One-chip microphones can then easily break the wafer into individual parts and the individual one-chip microphones can thus easily be obtained (not shown).

In step f), the Si ₃ N ₄ layer, which is retained together with the SiO ₂ layer as Si ₃ N ₄ / SiO ₂ layer 4 to compensate for the stresses therein, is contacted by means of an aluminum metallization 24 on the rear. The spacer 8 consisting of plasma-deposited SiO ₂ is then removed with the aid of 50% hydrofluoric acid (HF) in a time-controlled process. After this etching process only narrow webs 18 remain to support the structured poly-Si counterelectrode 16 in the edge region thereof. The counter electrode 16 therefore only has mechanical contact with the substrate at its corners. Scattering capacities are thus advantageously minimized, and at the same time a good flushing with HF acid is ensured during the spacer etching step just described.

The spacer ( 8 ) is then filled with liquid tert-butanol and then the frozen tert-butanol is sublimed from the solid phase in an evacuated eczicator (not shown). With the aid of this process called "freeze-drying", the wafer is dried in order to prevent sticking, that is to say adhesion of the Si ₃ N ₄ membrane 4 to the counterelectrode 16 after the etching layer in order to remove the spacer 8 . Finally, the unstructured side regions 19 of the structured poly-Si layer 16 are coated with aluminum with the aid of a third photolithographic mask. This aluminum layer is then structured so that contact pads 20 result. These contact pads are then electrically connected by bonding lines 22 .

Fig. 2 shows a according to an embodiment of the method according to the invention fully processed wafer portion in a perspective view. In the figure, the same reference numerals as in FIG. 1 have been used for structures which correspond to those of FIG. 1. Thus, Figure 2 shows the FIG., A Si substrate 2, an Si ₃ N ₄ / SiO ₂ membrane is at the 4. A poly-Si etching protection layer 6 is located on the membrane 4. The Si ₃ N ₄ membrane is contacted on the back (shown in FIG. 2 below) with an aluminum metallization 24 . An already structured spacer layer 18 is located on the front of the wafer, on the poly-Si etch protection layer 6. A structured counter electrode 16 is arranged on this spacer layer 18 . The counter electrode 16 made of doped poly-Si has contact pads 19 . Holes 17 are located in the counterelectrode 16 in the area of the counterelectrode 16 above the recess 15 created by etching in the Si substrate 2 .

FIG. 3 shows a completed prozessiertes one-chip microphone in a plan view. Here too, the same reference numerals are used if the structures designated in this way correspond to the preceding figures. FIG. 3 shows the counter electrode 16 provided with holes 17. The counter electrode 16 has a square shape. This square shape preferably has edge lengths of 0.25, 0.5, 1.1 and 2.0 mm. The square holes 17 in the counter electrode 16 preferably have an edge length of 25 μm and are preferably arranged at a distance of 40 μm. This has contact pads 19 at the corners of the square counterelectrode 16 . The edge of the Si substrate 2 produced by refraction is indicated by lines 26 .

In FIG. 4 shows an arrangement of a plurality of one-chip microphone 28 is shown on a wafer 30. These one-chip microphones 28 also have holes 17 in their counter electrodes 16 . The holes 17 can, as can be seen in the left part of FIG. 4, deviate from the square shape to be seen in the right part, the shape of a rectangle which extends with its long sides almost over an entire edge length of the square counterelectrode 16 . All one-chip microphones 28 are also provided with contact pads 19 here. In contrast to the previously illustrated embodiments of the one-chip microphones produced using the method according to the invention, some contact pads 19 have extensions 31 which end in contact areas 32 for connecting the one-chip microphones 28 . These contact areas 32 (shown in FIG. 4 on the left side of the wafer section 30 ) are arranged in a row on one side of the one-chip microphones 28 . In this way, the one-chip microphones can be contacted more systematically.

Claims (27)

1. Method for producing a one-chip microphone with the steps:
One SiO ₂ layer each is applied to the front and back of an Si substrate ( 2 );
one Si ₃ N ₄ layer each is applied to the SiO ₂ layers;
a spacer layer ( 8 ) is applied;
a poly-Si layer ( 10 ) is applied;
the poly-Si layer ( 10 ) is made electrically conductive;
the back SiO ₂ / Si ₃ N ₄ layer ( 4 ) is opened;
an Si ₃ N ₄ layer ( 14 ) is applied to the poly-Si layer ( 10 );
the Si substrate ( 2 ) is removed from the rear opening ( 12 );
the electrically conductive poly-Si layer ( 10 ) is structured;
the Si ₃ N ₄ layer ( 14 ) is contacted;
the spacer ( 8 ) is removed. 2. The method according to claim 1, characterized in that the SiO ₂ layers are applied by means of dry oxidation on the Si substrate ( 2 ). 3. The method according to any one of the preceding claims, characterized in that the Si ₃ N ₄ layers ( 4 ; 14 ) are applied by means of APCVD. 4. The method according to any one of the preceding claims, characterized in that the spacer layer ( 8 ) is formed from PECVD-SiO ₂ . 5. The method according to any one of the preceding claims, characterized in that the poly-Si layer ( 10 ) is applied undoped. 6. The method according to any one of the preceding claims, characterized in that the poly-Si layer ( 10 ) is made electrically conductive by boron implantation and subsequent temperature treatment at about 1000 ° C for about 1 h. 7. The method according to any one of the preceding claims, characterized in that the rear opening of the SiO _{2 /} Si ₃ N ₄ layer ( 4 ) is carried out with the aid of a photoresist mask and a subsequent etching process. 8. The method according to the preceding claim, characterized in that the etching process is a dry chemical plasma Is etching process. 9. The method according to any one of the preceding claims, characterized in that the Si substrate ( 2 ) is removed by means of KOH up to the SiO ₂ layer serving as an etch stop. 10. The method according to any one of the preceding claims, characterized in that the electrically conductive poly-Si layer ( 10 ) is structured with the aid of a photoresist mask. 11. The method according to any one of the preceding claims, characterized in that the structuring of the poly-Si layer ( 10 ) is carried out by means of plasma etching. 12. The method according to any one of the preceding claims, characterized in that the Si ₃ N ₄ layer is contacted by means of a rear aluminum metallization ( 24 ). 13. The method according to any one of the preceding claims, characterized in that the spacer layer ( 8 ) is removed by means of 50% hydrofluoric acid. 14. The method according to the preceding claim, characterized in that the spacer layer ( 8 ) is removed in a time-controlled process. 15. The method according to any one of the preceding claims, characterized in that after the application of the Si ₃ N ₄ layers to the SiO ₂ layers, a poly-Si etching protective layer ( 6 ) is applied to the front Si ₃ N ₄ layer. 16. The method according to any one of the preceding claims, characterized in that after the application of the spacer layer ( 8 ), a photoresist mask is applied to adjust the wafer. 17. The method according to any one of the preceding claims, characterized in that after the structuring of the poly-Si layer ( 10 ) on the front and back of the wafer ( 2 ) applied a protective lacquer and then the wafer ( 2 ) at intervals at about 2/3 of the wafer thickness is sawn. 18. The method according to any one of the preceding claims, characterized in that the wafer ( 2 ) is dried after removal of the spacer layer ( 8 ). 19. The method according to the preceding claim, characterized in that the drying of the wafer ( 2 ) is carried out by filling the spacer ( 8 ) with liquid tert-butanol and then the frozen tert-butanol in an evacuated eczicator from the solid phase is sublimated. 20. The method according to any one of the preceding claims, characterized in that contact pads ( 19 ) are structured on the structured, electrically conductive poly-Si layer ( 10 ). 21. The method according to the preceding claim, characterized in that the contact pads ( 19 ) with aluminum ( 20 ) are coated. 22. The method according to any one of the preceding claims, characterized in that the poly-Si layer ( 10 ) is applied in a thickness of about 5 microns. 23. The method according to any one of the preceding claims, characterized in that the spacer layer ( 8 ) is applied in a thickness of 2 to 5 microns. 24. The method according to any one of the preceding claims, characterized in that the rear opening ( 15 ) of the SiO ₂ / Si ₃ N ₄ layer ( 4 ) is carried out on a substantially square surface, the edge lengths of the squares in each case between approximately 0.2 and 3 mm can be selected. 25. The method according to any one of the preceding claims, characterized in that in the structuring of the poly-Si layer ( 10 ) in these holes ( 17 ) with a diameter of about 25 microns to 50 microns at a distance of about 20 to 60 microns be introduced. 26. The method according to the preceding claim, characterized in that the holes ( 17 ) are made square with an edge length of about 25 microns and a distance of about 40 microns. 27. A chip microphone manufactured by a method according to one of the preceding claims.