DE19740933C2 - Dynamic memory with two operating modes - Google Patents

Description

Dynamic random access memories (DRAMs) are common organized in blocks. Each memory shows block a number of memory cells that are over word and Bit lines can be selected. With the usual 1- Transistor memory cell is a storage capacitor across egg NEN selection transistor connected to one of the bit lines. A control terminal of the selection transistor is connected to one of the Word lines connected. The word and bit lines are ma arranged in a triangular shape. At their crossing points, they are Storage cells arranged. Each memory block is divided into two opposite sides of sense amplifiers (Sense Ampli fier) limited. Each memory block can have at most one one word line must be selected, otherwise several Memory cells connected to the same bit line at the same time that will.

There are different ways to repair faulty DRAMs Redundancy methods known in which word lines with de perfect memory cells through redundant word lines with in clocked memory cells are replaced. By performing egg ner corresponding redundancy programming is achieved that if there is a word address to address the defective Word line instead of this the redundant word line selek is tiert and a selection of the defective word line is bound. The redundant word lines are parallel to the normal word lines also in each memory block arranged and connected to redundant memory cells that also connected to the bit lines of the memory block are.

A distinction is made between intra-block redundancy and inter-block redundancy danz. With intra-block redundancy, a defective word order can  only through a redundant word line from the same memory cherblockes are replaced. Interblock redundancy can a defective word line due to a redundant word line another memory block. While with intra-block redundancy by replacing a defective one Word line of a block through a redundant word line the same block is guaranteed that only ever at most a word line is activated within a block, With interblock redundancy it could happen that except an intact word line of a block also a redundant one Word line of the same block is activated, which is a defective te word line of another block at the same time replaced. Therefore, it is necessary to take advantage of the interblock redundancy - namely the replacement of word lines with red Undante word lines from other blocks - to be explored that not one word line per memory block (as with intra-block redundancy), but only a single phrase tion per group of memory blocks to which the interblock redundancy is applied, activated at the same time becomes.

Dynamic memories have the property that their memories cells refreshed at certain intervals or right must be freshed because the storage condensate used gates lose their charge due to leakage currents. The refresh must be performed regularly for each memory cell. There with Store at most one word line with interblock redundancy is activated for each interblock group, this also applies to the Refresh the memory cells, so that the refresh is relatively long lasts.

A dynamic memory is described in DE-A1 42 41 327 ben, the memory cells and bits combined into blocks Lines and word lines for selecting the memory cell len, the blocks being combined into a block group are composed.

The invention has for its object a dynamic Specify storage with improved properties.

This task is accomplished with a dynamic memory according to An spell 1 solved. Training and executions of the Erfin are subject to dependent claims.  

The dynamic memory according to the invention has memory cells which are combined into blocks and via bit lines and word lines are selected. The blocks are too white at least summarized in a block group. The store has a first operating mode in which only one of each block group Word lines is selected at the same time, and a second Operating mode in which more than one of the word lines per block group be selected at the same time. In the second loading Drive mode can therefore advantageously egg at the same time ne larger number of word lines are selected than in the first operating mode. In the second mode, at for example, one word line in each block to the same Time selected.

The first operating mode can e.g. B. a normal mode of operation Memory, in which the content of selected memory cells read from memory or new data in selek tated memory cells are written. The second loading mode of operation can, for. B. be a refresh mode in which the Contents of at least a portion of the memory cells is fresh. The memory cells are then refreshed partly in a shorter time than in the first operation Art performed, since several word lines per block group be refreshed at the same time.

An embodiment of the invention provides that the dynami memory has inter-block redundancy. This means, that at least one of its blocks has at least one redundant Has word line with redundant memory cells that after Execution of redundancy programming for the optional Er put one of the word lines of any of the blocks serves the same block group. Furthermore, in this embodiment form in the second operating mode Redundancy programming deactivated. In the second operating So with the deactivation unit, he already becomes an art followed redundancy programming canceled so that no in  terblock redundancy is effective. Subsequently, it can be dangerous a word line can be activated per block, since no red Undant wordline due to the deactivation of the redundancy can become active at the same time.

According to an advantageous development of this embodiment According to the invention, the memory has a deactivation unit to deactivate a redundancy program that has already taken place mation of corresponding storage elements in the second Be mode of operation.

To also include the redundant word lines in the second Be To be able to select drive type is a further development of Invention before that the redundant word lines before Execution of redundancy programming already precoded te addresses are assigned and that in the second operating type (i.e. with redundancy programming deactivated) a Addressing of the redundant word lines via the preco dated addresses or their complements. So is e.g. B. a refresh of the redundant memory cells in the second operating mode possible in which the redundancy program is deactivated.

A further development of the invention provides that the dynami memory is a test mode for a long-term test of Has memory cells (burn-in test) during which the memory is put into the second operating mode. In the test mode art will consequently se a larger number of word lines reads than in the first mode, so that more advantageous a test of the memory cells in a relatively short time can be carried out. Especially when the second Be mode is a refresh mode, the burn-in test can be carried out in a relatively short time, since the refresh no data is delivered outside of memory, but this always within a block of memory leads. A permanent load on the memory cells is on  this way even without reading data from memory enough.

The invention is explained in more detail below with reference to the figures refines, show the embodiments of the invention. It demonstrate:

Fig. 1 shows an embodiment of the erfindungsge MAESSEN dynamic memory,

FIGS. 2a and 3 embodiments of details from Fig. 1,

Fig. 2b signal curves for the subject of Fig. 2a.

Fig. 1 shows a dynamic memory with word lines WL and bit lines BL, which are arranged in a matrix and are combined into two blocks B. The two blocks B form a block group BG (of course, actual memories have a much larger number of word lines, bit lines, blocks and block groups). In the crossing points of the word lines WL and the bit lines BL, memory cells of the dynamic memory are each arranged (not shown), each having a storage capacitor which is connected via a selection transistor to the respective bit line BL, the gate of the transistor being connected to the corresponding word line WL is connected. Each of the blocks B is assigned a word line decoder WDEC, via which the word lines WL are selected as a function of word addresses WADR with address bits A0 to A8.

The memory also has sense amplifiers SA, which with the bit lines BL are connected and on both sides of the memory blocks B are arranged. Architecture corresponds to the folded bitline concept. The sense amplifiers SA amplify one from one of the memory cells on the subject  bit line BL and give this information if necessary to external data lines of the memory. When here acted embodiment is only interested in shown part of the memory, since here essentially on a refresh mode of the memory is entered. On Refresh, ie a refresh of the memory cell contents follows, by the memory cell to be refreshed via the ent speaking word line WL is selected, its content on the corresponding bit line BL is given and there from reading is amplified before the selection transistor of the Memory cell locks again, so that the increased Informati on is written back into the memory cell. The Sense amplifier SA is from the external data lines separated so that the memory cell contents are not read out the memory is done.

The memory in FIG. 1 furthermore has a redundancy decoder RDEC, via which redundant word lines RWL in blocks B are addressed. The word addresses WADR are also fed to the redundancy decoders RDEC. If one of the word lines WL is to be replaced by one of the redundant word lines RWL, memory elements are programmed within the redundancy decoder RDEC so that when the word address WADR of the word line WL to be replaced is present, the redundant word line RWL is activated via the redundancy decoder RDEC and the redundancy decoder RDEC deactivates all word line decoders WDEC of block group BG (indicated in FIG. 1 by an arrow between the redundancy decoder RDEC and word line decoder WDEC). The structure of the redundancy decoder RDEC or its memory elements will be discussed below with reference to FIGS . 2 and 3.

In the dynamic memory of this embodiment, ei Interblock redundancy provided. That means that each of the redundant word lines RWL not just one word line WL of the own block B, but also a word line WL one can replace other block B of the same block group BG. How  described in the introduction to the description can be Block redundancy only one word line at a time Block group must be activated, otherwise there is a risk that one of the word lines WL and at least one of the redun danten word lines RWL within the same block B time become active immediately, whereby the on the same bit line BL read out information inevitably several memory cells becomes unusable. Therefore applies to the memory according to the invention the restriction that in a first operating mode of the Spei chers (in which the interblock redundancy is effective) only one Activate word line WL per block group BG at the same time may be fourth. The word line decoders WDEC are so ge stipulates that when the word address WADR is present in the first Operating mode only one of the word lines WL of the block group BG is activated.

The memory also has a second operating mode in which the redundancy part of the memory is completely deactivated, so that one word line WL per block B can now be activated safely at the same time. The second operating mode is a refresh mode, in which - as already mentioned - read data are only amplified by the corresponding read amplifier SA and written back into the selected memory cell. In order to address only the word lines WL and none of the redundant word lines RWL via the word addresses WADR during the second operating mode of the memory, the redundancy decoders RDEC in FIG. 1 are supplied with an activation signal EN which activates the redundancy decoders RDEC in the first operating mode and in the second Operating mode (at least temporarily) deactivated. In the case of deactivated fourth redundancy decoders RDEC, these do not address the word lines WL.

In Fig. 1, seven address bits A0 to A7 of the word address WADR are supplied to both word decoders WDEC, while an eighth address bit A8 is fed directly to the left word decoder WDEC and to the right word decoder WDEC via an exclusive OR gate XOR. The XOR gate has a further input to which an operating mode signal MODE is supplied. The operating mode signal MODE determines whether the memory is in the first or second operating mode. In the first mode of operation, the mode signal MODE has a high level, in the second a low level. Depending on the mode signal MODE, the right word decoder WDEC is supplied with the eighth address bit A8 inverted or not inverted. If the structure of the two word line decoders WDEC is the same, it is sufficient that in the second operating mode, one of the word lines WL is selected in both blocks B at the same time.

With regard to the components (not shown in FIG. 1) that connect to the sense amplifier SA, such as, for example, external data lines for reading data outside the memory, the memory according to the invention is designed in the same way as a conventional dynamic memory.

FIG. 2a shows a first exemplary embodiment of a detail of one of the redundancy decoders RDEC from FIG. 1 (the other redundancy decoder RDEC is designed accordingly). The redundancy decoder RDEC has a programmable memory element for each address bit A0 to A8 of the word address WADR, as shown in FIG. 2a. This is an electrical connection F that can be separated (e.g. by laser cutting), a so-called fuse. In other embodiments, equivalent circuits can also be implemented with other storage elements, e.g. B. with antifuses. A series circuit comprising a first transistor T1, a second transistor T2 and the fuse F is arranged between a supply potential VDD and a reference potential ground of the memory. A circuit node K between the first transistor T1 and the second transistor T2 is connected via a holding circuit H to a first input of a comparator COMP. One of the address bits A0 of the word address WADR is fed to a second input of the comparator COMP. An output signal RA0 of the comparator K serves as a bit of an address for addressing the corresponding redundant word line RWL, provided that the address programmed with the fuses F matches the word address WADR. For the remaining bits A0 to A7 of the word address WADR there is also a corresponding memory element with a comparator.

When the second transistor T2 is conductive, the state of the fuse is F (intact or destroyed) decisive for which Po potential at the input of the holding circuit H or at the first Input of the comparator K sets. Whether the second transistor T2 conducts or blocks, is dependent in the first operating mode from a set signal SET at its gate. When starting up of the memory, the second transistor T2 is initially blocked, so that the potential at node K is independent of the state of the Fuse F is. After the supply potential has swelled is, the node K is preloaded by a po sitative setting pulse of a precharge signal PRE at the gate of the most transistor T1. In the first operating mode, a Distant signal SET 'the set signal SET to the level of the supplier supply potential brought VDD, so that the transistor T1 lei tet. Thus the redundancy programming becomes active and the Zu Fuse F determines the potential at the first input of the Comparators COMP.

To move the memory from the first to the second operating mode, the memory has a deactivation unit G in the form of an AND gate, to which the operating mode signal MODE is supplied in addition to the distant signal SET '. In the first operating mode, the operating mode signal MODE - as already mentioned with regard to FIG. 1 - has a high level. In the second mode of operation, on the other hand, it has a low level, so that the set signal SET at the output of the AND gate G has a low level regardless of the state of the distant signal SET 'and the transistor T1 blocks. The redundancy programming of the fuse F is thus de-activated in the second operating mode, that is to say the state of the fuse F is irrelevant to the level at the first input of the comparator COMP.

FIG. 2a also shows how the activation signal EN deactivates the redundancy de coder RDEC. The state of a switching element S, for example a transistor, is dependent on the level of the activation signal EN. If the switching element S is closed, the redundancy decoder RDEC is activated, otherwise deactivated.

FIG. 2b shows associated signal curves for the circuit in FIG. 2a. In the left part of Fig. 2b, these are for the first mode (mode signal MODE has a high level) and in the right part for the second mode (mode signal MODE has a low level) Darge.

Fig. 3 shows an alternative to Fig. 2a exemplary embodiment of a detail of the redundancy decoder RDEC. A series circuit comprising a resistance element R and a fuse F is arranged between the supply potential VDD and the reference potential ground. Fig. 3 also shows a transistor T3, which is connected to the fuse F in parallel. The operating mode signal MODE is connected via an inverter I to the gate of the transistor T3. In the second operating mode, in which the operating mode signal MODE is at a low level, the fuse F is short-circuited via the transistor T3, so that the potential at a circuit node K between the resistance element R and the fuse F, regardless of the state of the fuse F, has a low level. Redundancy programming is thus deactivated in the second operating mode.

Of course, in the case of the object shown in FIG. 2a, the redundancy programming can be deactivated in the manner shown in FIG. 3 by means of a transistor connected in parallel with the fuse instead of the AND gate G and vice versa. The circuit in FIG. 3 can also contain a holding circuit like that in FIG. 2a.

Deactivating the redundancy programming according to FIG. 2a or 3 has the consequence that the redundant word lines RWL can be addressed via a precoded address (namely that of the unprogrammed or deactivated fuses F). Via these precoded addresses, the redundant word lines RWL in the case of FIG. 3 are addressed both before carrying out programming of the fuses F and when the programming is deactivated by means of the operating mode signal MODE. In the case of FIG. 2a, the redundant word lines RWL are addressed during the deactivation of the redundancy programming via addresses which are inverse (complementary) to the precoded addresses which were assigned to them before the redundancy programming was carried out.

The memory cells are now refreshed in the following way: The memory is switched from the first to the second operating mode via the operating mode signal MODE. At the same time who the RDEC redundancy decoder deactivated via the activation signal EN. Now, when the word addresses WADR are created, a selection of one of the word lines WL takes place in each block B. After all the word lines WL have been refreshed (defective word lines may also have been selected because the redundancy programming is canceled in the second operating mode), the redundant word lines RWL are refreshed. For this purpose, the redundancy decoders RDEC are reactivated via the activation signal EN, while the programming of the fuses F is still canceled by the mode signal MODE (FIGS . 2a and 3). The redundant word lines RWL are then addressed via their precoded addresses during the refresh.

In the described embodiment, not only one "normal" refresh during normal operation of the memory in the way described. The Re fresh also performed in the second mode while  the memory is a long-term test, a so-called burn-in test, is exposed. Through over a relatively long period of time (e.g. several hours) repetitive refreshing of the Memory cells in very short time intervals Resilience of the memory checked. By the fiction appropriate selection of several of the word lines WL or the redun danten word lines RWL per block group BG in the second Be The mode of operation in which the test is carried out requires the Test less time than with conventional memories with Inter block redundancy.

Claims (8)

1. Dynamic memory

• 1. with memory cells combined into blocks (B) and with bit lines (BL) and word lines (WL) for selecting the memory cells,
• 2. with at least one block group (BG) to which the blocks (B) are combined,
• 3. and with a decoder unit (WDEC, XOR),
  • 1. which, in a first operating mode, selects only one of the word lines (WL) of one of its blocks (B) at the same time per block group,
  • 2. and in a second mode of operation per block group (BG) in more than one of their blocks (B) one of the word lines (WL) is selected simultaneously.

2. Dynamic memory according to claim 1,

• 1. which in at least one of the blocks (B) has at least one redundant word line (RWL) for the selection of redundant memory cells which, after carrying out redundancy programming, selectively replacing one of the word lines (WL) of any of the blocks (B) thereof Block group pe (BG) serves
• 2. and in which a redundancy programming that has already been carried out in the second operating mode is deactivated.

3. Dynamic memory according to claim 2, with a deactivation unit (G; T3) for deactivation corresponding redundancy programming Storage elements in the second mode. 4. Dynamic memory according to claim 3,

• 1. in which the memory elements that can be separated contain connections (F) for storing addresses of a word line (WL) to be replaced by the redundant word line (RWL), a corresponding disconnection of the connections (F) taking place during the redundancy programming,
• 2. and the bridging elements (T3) for bridging the connections (F) for the purpose of deactivating the redundancy programming in the second operating mode.

5. Dynamic memory according to claim 3,
whose memory elements have holding circuits (H) which take over information stored in the memory elements when a set signal (SET) is activated,
and its deactivation unit (G) suppresses the activation of the set signal (SET) during the second operating mode. 6. Dynamic memory according to one of claims 2 to 5,

• 1. Pre-coded addresses are assigned to the redundant word lines (RWL) before performing redundancy programming
• 2. and in which, in the second operating mode, the redundant word lines (RWL) are addressed via the precoded addresses or their complements.

7. Dynamic memory according to one of the preceding claims che, with a test mode for a long-term test of the memory cells during which the memory is in the second mode is transferred. 8. Dynamic memory according to one of the preceding claims che, in which the second operating mode is a refresh mode, in which the content of at least part of the memory cells is refreshed.