DE19740543C1 - Integrated circuit test method - Google Patents

Abstract

The method involves defining, in a data processing system, a model of a circuit arrangement containing the integrated circuit (12) and other electronic functional units (14-42) according to a circuit description language (VHDL). The function of the circuit arrangement (10) is tested by means of the model by the data processing system in a simulation cycle. During the simulation cycle circuit conditions are calculated with partial models of the other functional units (14-42). The calculated conditions define circuit conditions at the inputs (A,B,C) of the integrated circuit (12). Circuit conditions at the outputs of the integrated circuit (12) are calculated with an IC model of the integrated circuit (12) from the input conditions. The circuit conditions occurring during the simulation cycle at at least some of the terminals of the integrated circuit (12) as well as corresponding simulation times are stored. From this data, test data are generated for a test robot. After a fault free simulation cycle the integrated circuit (12) is manufactured. The integrated circuit (12) is then tested by the test robot using the test data. On testing the integrated circuit (12) operates independent of the other functional units.

Description

The invention relates to a method for testing a integrated circuit, in which in a data processing system is a model of the integrated circuit (IC) and other electrical functional units included tendency circuit arrangement according to a circuit writing language is defined. The circuit description writing language is z. B. the well-known language VHDL (very high speed integrated circuit hardware description language). The function of the circuit arrangement is on Hand of the model through the data processing system in checked in a simulation run. During the simulation run ar the data processing system z. B. the program "QSim II" from Mentor Graphics. Furthermore concerns the invention a method and data processing processing system for generating used in testing Test data.

During a simulation run with partial models of the other electrical functional units Schaltzu states calculated, the switching states at the inputs of the Define the integrated circuit. With an IC model of the integrated circuit are from the Schaltzu at the inputs switching states at outputs of the integrated circuit calculated. Continue to be in a recording file during the simulation run the switching states on at least some of the connections of the integrated circuit and associated simulati ons saved. From the in the recording file Data contained in the test run after the simulation run generated for a test machine.

The integrated circuit is only manufactured when no more errors occur during the simulation run ten  the production of the integrated circuit becomes this Capture production errors with the test machine under Test data usage tested.

Should the integrated circuit be independent of the scarf arrangement can be tested in an additional Chen process step with the known test tools Test data are generated by simulating the ASIC's taking into account the requirements set by the test machine restrictions. However, the disadvantage is time and technical effort for the additional procedure race step.

The object of the invention is a simple method for Testing a circuit with fully automatically generated Specify test data before the entire test Circuit arrangement or that after this test for targeted Troubleshooting can be used. It is also a task the invention, a method for generating the test data and a data processing system for generating the test data specify.

This task is accomplished by a process with the characteristics of Claim 1 solved. Advantageous further developments are specified in the subclaims.

The invention is based on the knowledge that during the Simulation of the entire circuit arrangement including the switching states on all connections of the integrated circuit must be calculated. The connections of the integrated Form circuit to the other functional units Interfaces that clear the integrated circuit delimit the remaining part of the circuit arrangement. Because of of these interfaces it is possible to use the integrated Detach circuit from the circuit arrangement or simply omit the other functional units and the integrated circuit after its manufacture alone  test the data calculated for its connections. The Test data for the integrated circuit are at Ver drive out according to the invention  the data in a recording file that is created during the already necessary simulation of the entire scarf arrangement has been saved. An additional one Method step in which the integrated circuit again has to be simulated separately drive according to the invention. This results in an easy method for testing the integrated circuit, where the integrated circuit is also independent of the other functional units of the circuit arrangement can be tested.

The integrier works in the method according to the invention circuit during testing independent of the others electrical functional units. By this measure is achieved that the integrated circuit already before installation in the circuit arrangement z. B. immediately bar can be tested after production. A wide one The test is expediently carried out before the Circuit manufactured by a supplier ler the circuit arrangement in the circuit arrangement is soldered. Errors in the circuit can thus be eliminated record even before assembly, so that otherwise the mistake search and troubleshooting costs can be avoided.

The integrated circuit can also be used independently of the further electrical functional units are tested, if it is already part of the circuit arrangement, d. H. e.g. B. with the conductor tracks of a circuit board is. Such a test is also called an "in-circuit Test ". The circuit arrangement is thus designed fen that the other functional units of the scarf arrangement during the test has no influence on the integrated circuit and thus on the test result to have. For example, the outputs of these functions ons units in a so-called high-resistance state switches. By doing so, one can  Printed circuit board with faulty circuit arrangement easily determine if the integrated circuit is the fault source is.

In the method according to the invention during the Si mulation in the recording file only such switching states be saved at the inputs or the outputs against the model of the integrated circuit. Even with integrated circuits with several hundred The recording file still has connections without one Difficulty to process scope.

In a development of the invention there is in the Circuit arrangement with a periodic reference signal whose help cycle limits are set. The reference signal is e.g. B. an internal clock in the integrated circuit circuit, from the outside to the integrated circuit placed beat or a scarf at another point arrangement occurring clock. Set the cycle limits Simulations in succession during the simulation cycles and when testing in succession Test cycles. By considering Taktsi The method according to the invention can relate to clock-dependent gig working systems are used, for. B. scarf arrangement with microprocessors.

When performing the above-mentioned procedural steps the test data are generated according to the tester so that the technical parameters specified by the test machine be complied with. The cycle time of the clock in the Circuit arrangement is z. B. at 10 ns. These are short periods of time for signal changes also taken into account in the simulation by for Simula times with a numerical value of 0 ns, 10 ns etc. switching states can be calculated. Test machines However, new test data can only e.g. B. every 200 ns to the Create the circuit to be tested. That's why with one  Further development of the invention through the simulation points in time at the cycle limits of a simulation cycle specified time period shorter than the duration of a test cycle klus. Thus, the time axis is stretched at Te instead. This measure can also be used later very fast working circuit arrangements with relative Test the slow-running test machine.

In another development of the invention, the Test data generated so that changes in switching states of the same signal in the test cycles only with the same time interval to the beginning of the respective test cycle occur. So there is for the change of Schaltzu stood only for a time during the entire course of the test Liche description that z. B. in a time record is deposited. Such a time record is also in English referred to as the "Timeset". This measure enables Te automatic vending machines are used that only have a time record allow. Automatic test machines with multiple time records ar usually work slower. With them, too number of time records limited, e.g. B. to sixteen Time records. Due to different signal times ten within the circuit arrangement and in particular inside the integrated circuit, Si Changes in the signal are also not exact in the simulation predictable simulation times. With the Wei Training with only one time record is the changes of switching states within a simulation cycle but at a given point in time within egg nes test cycle postponed.

If the test data in another training of the Invention generated so that the switching states of bi directional connections of the integrated circuit can only change at the cycle limits of the test cycles, so also test machines are used that only have data with can process such switching state changes.  

Test machines that have no restriction regarding the changes tion of the switching states are not always available or will not be used for other reasons det.

In another development of the method according to the Invention is used in the simulation and in the generation of Test data takes into account a switching signal, which the Signal flow direction at bidirectional connections of the in integrated circuit indicates. By this measure can automatically, d. H. without manual intervention, switching states on bidirectional connections in switching states are subdivided, which input signals for the inte are circuit, and in switching states, which Represent output signals of the integrated circuit. During input switching states when testing the test machine are applied to the integrated circuit Output switching states Setpoints, which during the test by the Test machines are queried. When simulating the Circuit arrangement, the switching signal is independent calculates whether there is an inaccessible from outside internal changeover signal or an external changeover signal is that later on a connector of the integrated Circuit is tapped. The automatic Assignment of the switching states to input switching states and output switching states on bidirectional connections be carried out during further training if late ter the test, the switching signal from the outside no longer di can be influenced directly. Switching states that the order switch signal, in this case must be in the Recorded files are saved, but are no longer included in the test data.

In another development of the invention, the Si Signal curve of the switching signal changed so that the a sampling time at the end of the simulation cycle already switched to a state within the same ben simulation cycle lie before this sampling time the time of the shift occurs. This different Practice time is the same in all simulation cycles Chen time interval to the beginning of the respective simula cycle. This measure ensures that in  changes occurring relatively late in a simulation cycle conditions of the switching signal already at Create the test data for this simulation cycle can be viewed. This applies in particular if Simplification of the creation of the test data only switching states at a relatively early point in the simulation cycles are taken into account.

Just like the switch signals are in another Ausge staltung the invention also selected input signals Inputs of the integrated circuit within a Simulation cycle postponed. This affects input signals at inputs that are only connected via blocks with kombina toric basic functions on outputs of the integrated Circuit. Such building blocks are e.g. B. AND gate, OR gates and negators. It is based on knowledge that with these input signals even changes of Signal states that occur towards the end of the cycle, still the Switching states at outputs of the integrated circuit in the influence the same simulation or test cycle. The change tion is then specified as in the time record, z. B. only on Completed at the end of the test cycle. By moving the selected input signals towards the beginning of the test cycle, it is achieved that the Schaltzu would only be within the simula at one time tion cycle must be considered.

Is the integrated circuit a so-called user-specific specific integrated circuit, d. H. an ASIC (application specific integrated circuit), that's the use of the present method particularly advantageous because it not standard for such integrated circuits Test data there.

Which relates to a method for generating the test data The object of the invention is achieved by a method Claim 16 solved. The above technical Effects also apply to the process for generating the Test data itself.  

The task relating to a data processing system becomes through data processing system for generating test data with solved the features of claim 17. With the Data processing system is in particular the method for Generation of the test data carried out. Thus the upper apply mentioned technical effects also for the Data processing system.

The following are exemplary embodiments of the invention Hand explained with the accompanying drawings. In it show:

Fig. 1 is a block diagram of one, to be modeled, and later test module with ASIC

Fig. 2A and 2B are a flowchart showing process steps and files for generating test data for testing of the ASIC,

Fig. 3 switching states of terminals of the ASIC during the simulation,

Fig. 4 switch states at the locations shown in Fig. 3 to circuits of the ASIC according to test data,

Fig. 5 switching states at connections of the ASIC's and switching states on a changeover signal during the simulation, and

Fig. 6 switching states on the connections shown in Fig. 5 of the ASIC's according to test data.

Fig. 1 shows a block diagram of the modeling of an assembly 10 which includes an ASIC 12.. The assembly pe 10 is part of a data processing system still to be manufactured. The ASIC 12 is manufactured by an ASIC manufacturer in accordance with the specifications of the manufacturer of assembly group 10 . Before the manufacturer of the assembly 10 has the ASIC 12 manufactured, he uses modeling and simulation to check whether the ASIC 12 can fulfill all of the tasks assigned to it within the assembly 10 . Before the simulation, a model of the assembly 10 is defined in accordance with a circuit description language using a modeling program on an operational data processing system. A known circuit description language is such. B. the language VHDL (very high speed integrated circuit hardware description language). The simulation is then carried out with a simulation program I, which is carried out on the same data processing system. As simulation program I, cf. Fig. 2A, for example. B. the known program "QSIM II", "QHDL" or another program from Mentor Graphics.

The assembly 10 contains, as further electronic function units, a so-called bus driver 14 , an interface module 16 , a main memory 18 , a processor 20 , a buffer 22 , also called "cache", with a short access time compared to the main memory 18 , an auxiliary memory 24 and an input / output unit 26 . The bus driver 14 is connected to a Sy stembus 28 , via which the module 10 sends data to other modules of the data processing system to be manufactured or receives data from the other modules. The ASIC 12 and the interface module 16 are connected to the bus driver 14 via a bus 30 .

The bus driver 14 has on the one hand the task of amplifying the signals sent by the assembly 10 for data transmission and on the other hand to ensure that the Sy stembus 28 is not overloaded when receiving data in the assembly 10 .

Another bus 32 of module 10 connects ASIC 12 to interface module 16 and processor 20 . The ASIC 12 is connected to the auxiliary memory 24 via a bus 34 and to the input / output unit 26 via a bus 36 . A bus 38 is located between the main memory 18 for storing program data and user data and the ASIC 12 . The interface module 16 accesses the main memory 18 when reading and writing data using a bus 40 , which connects the main memory 18 to the interface module 16 . Another bus 42 connects the processor 20 to the intermediate storage 22nd

The models for the electronic functional units 14 to 26 are taken from so-called macro libraries, which the manufacturer of the modeling program supplies. The model for the ASIC 12 , however, is designed by the manufacturer of the assembly 10 . Buses 30 through 42 are modeled by references. The references indicate which connections of the ASIC 12 and the functional units 14 to 26 are connected to one another.

During the simulation, the functionality of the assembly group 10 is checked, inter alia, by generating inputs on the connections of the system bus 28 for the assembly 10 which later also occur during the operation of the data processing system to be manufactured. The outputs on the system bus 28 which are then simulated with the module 10 are then compared with target outputs which are intended to occur in response to the inputs during error-free operation.

The simulation takes place in such a way that for the models of the ASIC's 12 and the electronic functional units 14 to 26, switching states at the outputs are calculated depending on the switching states at the inputs. This is done for each individual clock pulse of a system clock T, which is applied to the clock inputs of the ASIC's 12 , the interface module 16 and the processor 20 . This system clock T is not shown in FIG. 1 for reasons of clarity, but is explained below with reference to FIG. 3.

The switching states at all inputs and outputs of the model of the ASIC's 12 are stored in one or more recording files during the simulation. From the data stored in the recording file, test data are generated according to the method explained below with reference to FIGS. 2A and 2B, which are used for the test of the ASIC 12 manufactured by the ASIC manufacturer in a test machine.

In Fig. 1 shows a dashed around the ASIC 12 running line 44 that in the simulation in the cut file only switching states are saved, which are calculated with the models of the functional units 14 to 20 , 24 and 26 and which are also the starting point for calculations are with the model of the ASIC's 12 and switching states that are calculated with the model of the ASIC's 12 for the models of the functional units 14 to 20 , 24 and 26 be.

10 pe occur no more errors in the simulation of the operation of the compo, the manufacturer 10 such passes the module, the circuit description of the ASIC 12 to the ASIC vendor who manufactures the ASIC 12th If necessary, the manufacturer of the module 10 also passes the test data generated from the data in the recording file to the manufacturer of the ASIC's 12 , so that the latter can test, even without knowledge of the functions of the ASIC's 12 or even the module 10 , whether the one produced by him ASIC 12 is working correctly.

The test data relate exclusively to the interface between the ASIC 12 and the other functional units 14 to 26 indicated by the dash line 44 . This enables the ASIC 12 to be tested independently of the other functional units 14 to 26 when testing on the automatic machine.

Figs. 2A and 2B show a flow chart Ver method steps for generating the test data for the test of the ASIC 12, see FIG. FIG. 1. The simulation of the assembly 10 explained with reference to FIG. 1 is represented by a method step 100 . Step 100 is carried out when the simulation program I is executed. The system clock T already mentioned is used as a reference signal for setting cycle limits. The cycle limits define a simulation cycle Zn of the simulation, cf. Fig and through the cycle limits who the limits of test cycles Zn 'set. 3 5 to the manufactured for the later test ASICs, see. FIGS. 4 and 6. The differences between simulation cycles Zn and test cycles Zn 'of Fig. 3 and 4 will be explained below on hand. The lowercase letter n is a natural number that takes values from 1 to N or 1 to N ', where N is the number of the last simulation cycle Zn or N' is the number of the last test cycle Zn '.

The switching states of input signals of the ASIC 12 and of so-called switch signals of the ASIC 12 are written into a first recording file 102 when the method step 100 is carried out. The changeover signals are signals that determine in which signal direction bidirectional connections on the ASIC 12 or on its model work at the respective simulation time. Depending on the switching signal, the bidirectional connections work either as inputs or as outputs. The switching states of output signals of the ASIC's 12 and also the switching states of the switching signals are stored in a further recording file 104 . The bidirectional signals are stored both in the first recording file 102 and in the further recording file 104 , because these signals act as inputs on the one hand and also represent output signals on the other hand. The switching states are saved in a format that is specified by the simulation program I. So z. B. for the switching states also the associated simulation times are stored in the recording files 102 , 104 .

In a method step 106 , the data stored in the cut files 102 and 104 are converted into data according to an intermediate format. In the exemplary embodiment, this intermediate format is the SNIP format (standard NICE pattern; NICE = Nixdorf Integrated Circuit Environment), an in-house data format from Sie mens Nixdorf Informationssysteme AG. The intermediate format enables the subsequent process steps to be carried out independently of the simulation program used. However, the prerequisite is that the simulation data generated by the respective simulation program are first converted into the intermediate format used.

During the conversion in step 106 , a file 108 is generated from the cut file 102 , which contains the switching states of the input signals and the switching signals in SNIP format. The switching states and the simulation times remain unchanged in comparison to the switching states and simulation times in the recording file 102 in the file 108 . In method step 106 , the data contained in the recording file 104 are also converted into the SNIP format. A file 110 is created which contains the switching states of output signals and changeover signals and associated simulation times. Method step 106 is carried out by executing a conversion program II.

In a method step 112 , the switching states of the input signals and the switching signals are tapped at a predetermined time ZP1 within each simulation cycle. This is also referred to as a “strobe” and is carried out by determining the state of the respective signal at the point in time ZP1 in the processed simulation cycle Zn using the signal changes noted in the file 108 and the associated simulation times.

Tapping the switching states in step 112 prepares a shifting of combinatorial input signals and the switch signals in a method step 116 explained below. It is necessary to move it if the test machine used during the later test of the ASIC only allows a change of switching states at bidirectional connections only at the cycle limits. By shifting is achieved in particular that the switching states of the combinatorial input signals and the switching signals are already effective in the test cycle Zn 'belonging to the respective simulation cycle Zn', cf. also process step 120 . This is explained in more detail below with reference to FIGS. 3 and 4.

The combinatorial inputs are inputs of the ASIC 12 , the switching states of which affect the switching state at one or more outputs of the ASIC within the same simulation cycle Zn. These are inputs that can only be accessed using a simple combinatorics, e.g. B. from AND gates and OR gates, are connected to outputs of the ASIC's 12 . As already mentioned, the switching signals indicate in which signal direction bidirectional connections of the ASIC's 12 are operated in the respective simulation cycle Zn. The switching state zero of the changeover signal indicates that the bidirectional connections influenced by the respective changeover signal operate as inputs. The switching state logic one indicates that the associated bidirectional connections are outputs.

The switching states are tapped in method step 112 by executing a tapping program III, which processes the file 108 as input and generates a file 114 as output, which likewise contains switching states in SNIP format. The switching states of the input signals and the changeover signals are noted in the file 114 at the time ZP1 in each simulation cycle Zn.

In the following step 116 , the file 114 is processed, the simulation time associated with the switching states of the input signals having a combinatorial effect and the switching signals determined in method step 112 being reduced by a fixed amount. This amount is given by the difference between the simulation time ZP1 and a predetermined simulation time ZP2 lying before this in the simulation cycle Zn in question. The time ZP2, like the simulation time ZP1, occurs at the same time within each simulation cycle Zn. The change in the simulation time in method step 116 leads to a time shift in the switching of the processed signals. The switching of the signal under consideration is postponed to the time ZP2.

The shift in method step 116 is carried out during execution of a shift program IV. The displacement program IV generates a file 118 as output. In the file 118 , the switching states of the switchover signals shifted in step 116 to the point in time ZP2 and the switching states of all other inputs at the point in time ZP1 specified in step 112 are combinatorially acting input signals in the SNIP format.

In a method step 120 , all signal profiles stored in the file 118 for the input signals and in the file 110 for the output signals are processed. With the help of a tapping program V, the switching states at a predetermined point in time ZP3a are determined from the file 118 for the input signals and the changeover signals and recorded in a file 122 . The time ZP3a lies between the times ZP2 and ZP1 close to the time ZP2 and is preferably chosen so that it lies before the active edge of the system clock T in the respective simulation cycle Zn. When processing the tapping program V, the switching states of the output signals and changeover signals contained in the file 110 are determined at a predetermined time ZP3b and noted in a file 124 . The point in time ZP3b is preferably at the end of a simulation cycle Zn, that is to say after the points in time ZP2, ZP3a and ZP1. At time ZP3b, no switching states change within the simulation cycle. The signal states are tapped for each simulation cycle Zn, Zn + 1 etc. The position of the times ZP3a and ZP3b can be seen from FIGS . 3 and 4 explained below. The files 122 and 124 contain data in the SNIP format and are further processed in a subsequent processing step 126 .

In method step 126 , a generation program VI is processed, which generates tester-compatible signal profiles from the signal profiles stored in files 122 and 124 , which signal testers fulfill the requirements placed on the signal profiles by the automatic test machine. The generation program VI continues to process the following entries:

• - The length of a test cycle Zn '. This time can deviate from the time taken by a simulati ons cycle Zn is specified. Therefore times that relate to the test with a highly marked with a dash.
• - the specification of a time record, the definitions from times ZP4a 'to ZP4f', at which the test machine changes the switching states of certain Signals should change. Such a time record is also called "Timeset" in English.
• - A list of the changeover signals and the bidirectional connections of the ASIC 12 belonging to the respective changeover signals.

In method step 126 , the steps explained below with reference to FIGS. 3 to 6 are carried out. These steps include:

• - Aligning the waveforms to the given nen times ZP4a 'to ZP4f';
• - adapting the simulation time t to the test time t ', with different cycle width of Simula tion cycle Zn and test cycle Zn ', z. B. by Mul the simulation times with a Stretch factor;
• - The overwriting of switching states for switched on output bidirectional connections of the ASIC's 12 with a value that indicates a high-resistance state, z. B. with the value Z, cf. also Fig. 6;
• - The insertion of additional test cycles Zn 'in which bidirectional outputs have the high-resistance state Z. These insertions are explained below in connection with FIG. 6.
• - Remove the switching states for the changeover signals if the changeover signals only occur internally in the ASIC 12 .

As a result of the processing in method step 126 , a file 128 is created from the file 122 in which the switching states of the input signals are contained in a manner suitable for the tester. A file 130 is generated from the file 124 , which contains tester-compatible output signals. Files 128 and 130 contain data in SNIP format.

In a last method step 132 for generating the test data, the data contained in the files 128 and 130 are converted with the aid of a conversion program VII into a data format which can be processed by the automatic test machine. During the conversion, a file 134 is created in which the data is stored in accordance with the format of the automatic machine. The data in the file 134 form a tester program because the test machine applies input data to the connections of the ASIC's 12 one after the other and the data at the outputs of the ASIC's 12 are compared with the target data for the outputs contained in the file 134 .

The generation of the files after each process step enables a clear separation of the programs I to VII, so that different developers or groups of developers can work on a program. The method steps 100 , 106 , 112 , 116 , 120 , 126 and 132 can also be carried out in separate files without temporarily storing the results. Furthermore, the processing steps carried out in method steps 106 , 120 , 126 and 132 for the input signals and the output signals can also be carried out separately with different programs.

Fig. 3 shows the switching states of terminals of the ASIC 12, see FIG. Fig. 1, during the simulation. The switching states are shown for specific simulation times t. Various simulation times ZP are shown on a time axis 150 . A cycle limit 152 shows the beginning of a simulation cycle Zn. This simulation cycle Zn has ended at a cycle limit 154 . Immediately after the simulation cycle Zn follows the next simulation cycle Zn + 1, the beginning of which is exactly the end of the cycle Zn, ie the cycle limit 154 . The simulation cycle Zn + 1 ends at a cycle limit 156 .

Both simulation cycles Zn and Zn + 1 simulate simulation periods of the same length, from z. B. 10 ns. The assignment of the switching states calculated in the respective simulation cycle at simulation times is carried out, as already mentioned, by noting the simulation times in the recording file 102 or 104 , cf. Figure 2A.

In the simulation, digital switching states are simulated at certain simulation times ZP. The sequence of these switching states at a particular connection forms a signal run with increasing simulation time t. In the digital simulation considered in the exemplary embodiment, there are only the switching states logic zero and logic one. These switching states can be represented by two values on an abscissa axis. In Fig. 3 five waveforms 160 to 168 are shown.

The signal curve 160 shows the switching states of the system clock T in the simulation cycles Zn, Zn + 1. The system clock T switches exactly once in each simulation cycle Zn from the value logic zero to the value logic one and then again from the value logic one to the switching state logic zero around. The simulated frequency of the system clock T is therefore exactly 100 MHz for the above example with a cycle time of 10 ns. The signal curve 160 generated by the system clock T thus contains a pulse signal 170 with a pulse width Br that is also relatively constant during the simulation. The start of the pulse signal 170 with respect to the start of the respective simulation cycle Zn is also approximately for all simulation cycles Zn same, cf. Clock delay TDT.

The distance between successive cycle limits 152 to 156 is predetermined by the clock period of the system clock T. When determining the exact location of the cycle limits 152 to 156 there is therefore only one degree of freedom, z. B. Determining the beginning of the cycle with respect to the pulse signal 170 . The clock delay TDT is expediently not chosen too short, since the time period TDT is required for method steps 116 and 120 , cf. Fig. 2A and 2B. On the other hand, the clock delay TDT must not be chosen too large, since at the end of the simulation cycle all signal states that change due to the pulse signal 170 must have a stable switching state.

The signal curve 162 belongs to an input A of the ASIC 12 , cf. Fig. 1. The signal curve 162 is a ramp signal, since this signal changes its switching state only once within a simulation cycle Zn. If there is a change in the switching state at input A within a simulation cycle Zn, this change is only within a predetermined time range. In the simulation cycle Zn there is a delay time TDAZn between cycle limit 152 and switchover time. In the simulation cycle Zn + 1 there is a delay time TDAZn + 1 between the cycle limit 154 , ie the beginning of the simulation cycle Zn + 1, and the switchover time. The delay times TDAZn and TDAZn + 1 are different from one another. The difference can be explained by different signal propagation times in the electronic components that generate the respective switching state at input A.

The signal curve 164 occurs at an input B of the ASIC 12 . The signal curve 164 is also a ramp signal with respect to a simulation cycle Zn, because the switching state either does not change at all or changes only once. At the input C of the ASIC 12 , the signal course 166 occurs during the simulation. The input C is a so-called combinatorial input because it is only connected to outputs of the ASIC's 12 via combinatorial switching elements. Within a simulation cycle Zn, the signal course 166 has the form of a ramp signal.

The signal curve 168 relates to three bidirectional connections of the ASIC's 12 , which either work as inputs or as outputs and are referred to as bus B1. The bus B1 is part of the bus 30 , cf. Fig. 1. A switch signal, not shown, defines the manner of operation of the connections of the bus B1. The switchover signal was not shown in FIG. 3 since it does not change its value during the simulation cycles Zn and Zn + 1 shown. The connections of the bus B1 operate as inputs in the example shown in FIG. 3. The processes involved in a switching state change on the changeover signal are explained below with reference to FIGS. 5 and 6.

At the beginning of the simulation cycle Zn there are zero, zero and one at the connections of the bus B1 operating as inputs, represented by "001". These switching states are taken over when switching the system clock T for the calculations within the IC model for the ASIC 12 , so that shortly after the rising clock edge of the system clock T new switching states can be created at the connections of the bus B1. The resulting short-term signal conditions are indicated by crossovers. At the beginning of the simulation cycle Zn + 1, signal states zero, one and zero are present on bus B1, cf. "010".

The position of the simulation times ZP1 to ZP3b in relation to the respective simulation cycle Zn is the same in all simulation cycles Zn, cf. also the simulation times corresponding to the simulation times ZP1 to ZP3b ZP1 * to ZP3b * in the simulation cycle. Therefore, only the position of the simulation times in the simulation cycle Zn must be explained below. The simulation time point ZP1, which is referred to in method step 112 according to FIG. 2A, lies approximately at the beginning of the last quarter of the simulation cycle Zn. At this point in time, all switching states in the simulation cycle Zn already have the value that they also had at the end of the simulation cycle Zn to have.

The simulation time ZP2 used in method step 116 according to FIG. 2A lies approximately at the end of the first third of the simulation cycle Zn. In method step 116 , the switching state determined at the time of simulation ZP1 at the combinatorial input C is "shifted" to the time point ZP2. This means that switching state one is not present during the simulation at the time ZP2 at the input C, but the switching state zero at the time ZP1 at the input C is further processed, so that a relatively late change in the switching state at the input C in one the test cycle Zn 'belonging to the simulation cycle Zn becomes effective, cf. also the description of FIG. 4 below. The changes in the switching states at the inputs A, B and on the bus B1 that occur after the rising clock edge of the system clock T, on the other hand, only become effective in a test cycle Zn + 1 'belonging to the simulation cycle Zn + 1, because these switching states are not shifted after the time ZP2 .

The time ZP3a is after the time ZP2 and before the time at which the rising edge of the system clock T is. As already mentioned, the point in time ZP3a is the point in time at which the switching states which are to apply in the associated test cycle Zn 'are determined for all input signals and changeover signals, cf. the explanation below for FIG. 4.

The point in time ZP3b at which the output signals and changeover signals contained in the file 110 according to FIG. 2A are determined lies between the point in time ZP1 and the end of the simulation cycle Zn.

FIG. 4 shows switching states at connections of the ASIC according to test data which have been generated from the signal states according to FIG. 3 recorded during the simulation. When explaining FIG. 4, reference is also made to FIG. 3 without express reference. The test time t 'is shown on a time axis 180 . The time axis 180 is stretched relative to the time axis 150 . A test cycle Zn 'is limited by cycle limits 152 ' and 154 '. A test cycle Zn + 1 'following the test cycle Zn' is limited by the cycle limit 154 'and a cycle limit 156 '. The test cycles have e.g. B. a duration of 200 ns and are thus twenty times as long as the simulation cycles Zn for the example given above. The signal profiles 160 to 168 include signal profiles 160 'to 168 ' in this order.

The signal curve 160 'represents the switching states at the clock input of the ASIC's 12. Due to the stretching of the time axis 180 compared to the time axis 150 , the system clock T only has a frequency of 5 MHz during the test. The signal curve 160 'is generated in method step 126 according to FIG. 2B, but the data contained in files 122 and 124 is not used, since the signal curve 160 has been lost by tapping the signals in method step 120 according to FIG. 2A . For each test cycle Zn ', times ZP4c' and ZP4d 'explained below are specified, which determine the width of the clock pulse 170 ' in each test cycle Zn '.

The signal curve 162 'is generated from the signal curve 162 . The switching state at the time ZP3a is also used by the test machine in the associated test cycle Zn '. A point in time ZP4a 'in the time data record was specified as the switchover point. The switching state at input A changes according to signal curve 162 'only at the beginning of a test cycle Zn'. This measure ensures that there are no longer any different signal propagation times, since any change of state that may occur is always forced at the start of the test cycle. In addition, requirements that are specified by the tester are taken into account when determining the time data record. For example, the minimum distance between successive changes in switching states at different inputs of the ASIC 12 must be at least 10 ns. The switching states on bidirectional connections may only change at cycle limits 152 'to 156 '.

When comparing the signal curves 162 and 162 'it becomes clear that the change in the switching state after the time ZP3a of the switching state at the input A from the value logic zero to the value logic one only takes effect in the next test cycle Zn + 1'.

The signal curve 164 'is generated from the signal curve 164 . The signal curve 164 'can only change at the time ZP4b'. For signal waveform 164 'as well as for signal waveform 162 ', changes in switching states which occur after time ZP3a only become effective in a subsequent test cycle Zn + 1 '. The location of the test times ZP4a 'and ZP4b' is also determined taking into account the requirements for the switching logic. The switching state at input A must change z. B. always change before the switching state at input B.

In contrast to the signal profiles 162 'and 164 ', the signal profile 166 'relates to a combinatorial input. A shift is carried out on these inputs in method step 116 according to FIG. 2A. This shift explains why the change in the switching state at the input C after the time ZP3a in the simulation cycle Zn already takes effect in the associated test cycle Zn '. The switching state zero at the time ZP1 was shifted ver in step 112 according to FIG. 2A so that it is already effective at the time ZP2 in the simulation cycle Zn. When tapping the signals at the time ZP2 following the time ZP3a it is noted that the switching state logic zero applies to the input C in the simulation cycle Zn. According to the time data record, the signal at input C changes only at one point in time ZP4e '. The signal waveform 166 'corresponds approximately to the signal waveform 166 by this specification.

The signal curve 168 'for the bidirectional connections of the bus B1 connected to input is generated in step 126 according to FIG. 2B by using the switching states present at the time ZP3a in the simulation cycle Zn during the entire associated test cycle Zn'. The requirement that switching states at bidirectional connections may only change at the cycle limits 152 'to 156 ' during the test is thus fulfilled.

Statuses of output signals determined at the time ZP3b in the simulation cycle Zn are used at a time ZP4f 'in the test cycle Zn'. The point in time ZP4f 'is determined by the point in time at which the device automatically senses the switching states at the outputs of the ASIC's 12 . The sampled values are then compared with the associated switching states at the time ZP4f '.

Fig. 5 shows switching states of terminals of the ASIC 12 and switching states of a switching signal U during the simulation. The simulation time t is plotted on a time axis 200 . Five simulation cycles Zn to Zn + 4 are defined by cycle limits 202 to 212 . The system clock T is represented by a waveform 220 .

The switching states on the internal switchover signal U for the bus B1 are represented by a signal curve 222 . Switching signals that change their switching state within a simulation cycle Zn only after the respective point in time ZP3a are shifted in method step 116 from point in time ZP1 to point in time ZP2 in order to evaluate the switching states in the same cycle Zn. Moving takes place in the same way as shifting the switching states at combinatorial input C, cf. Explanations of FIG. 3.

The switching states on the bus B1 itself are illustrated by a signal curve 224 . In contrast to the embodiment explained with reference to FIGS . 3 and 4, the switching state of the switching signal U changes in the embodiment of FIGS . 5 and 6, so that the connections to the bus B1 serve both for input and for output. The switching state zero of the Umschaltsi signal U indicates that the connections of the bus B1 work as inputs. In the simulation cycle Zn, switching states "011" are entered on the bus B1 in the ASIC 12 , and in the simulation cycle Zn + 1 switching states "001" are entered.

The ASIC 12 is operated in such a way that filler data F are transmitted before the bus B1 is switched from input to output. The filler data F are no longer processed but serve as placeholders. As fill date z. B. the switching state one can be used throughout. In the simulation cycle Zn + 2, the fill data F are entered on the bus B1. In addition, in this simulation cycle Zn + 2, the switchover signal U switches from the switching state zero to the switching state one, so that the bus B1 works as a data output. Switching states "111" are output at the connections of the bus B1.

The switching signal U switches in the simulation cycle Zn + 3 again from switching state logic one to switching state logic zero around, so that the bus B1 in the following simulati ons cycle Zn + 4 works again as data input. In the simu lation cycle Zn + 4, data "000" are entered on bus B1 ben.

Fig. 6 shows switching states at the terminals of the ASIC 12, which belong to the test data and the generated from the Si gnalverläufen the simulation according to Fig. 5 who the. When explaining FIG. 6, reference is therefore made to FIG. 5 without express reference. A time axis 230 stretched with respect to the time axis 200 shows the test time t '. Five test cycles Zn 'to Zn + 4' are determined by cycle limits 202 'to 212 '. A signal curve 220 ′ corresponds to the signal curve 220 . However, the system clock T has a frequency of only 5 MHz during the test.

The switchover signal U no longer occurs on the test machine because it is an internal signal in the ASIC 12 that cannot be applied to any of its connections. The switching signal U is automatically switched depending on the inputs to the connections of the ASIC 12 . Thus, in FIG. 6, the signal curve no longer belongs to the signal curve 222 .

The waveform 222 is, however, used to produce a tester just waveform 224 from the waveform 224 '. With signal curve 224 ', the switching states on bus B1 only change at cycle limits 202 ' to 212 '. If the bus B1 is switched to data input, the switching states are generated as already explained above with reference to FIG. 4. In the test cycle Zn + 1 ', the input data "001" present at the beginning of the associated simulation cycle Zn + 1 are applied by the test machine to the connections of the bus B1. The filler data F are overwritten with a value Z, which instructs the test vehicle to generate a high-resistance state at the connections of the data bus B1. In the test cycle Zn + 2 ', the test machine therefore does not enter any data into the ASIC via bus B1. In the following test cycle Zn + 3 ', no data is entered via the bus B1 from the test machine into the ASIC 12 either. The switching states "111" at the beginning of the simulation cycle Zn + 3 are overwritten by values Z which cause the test machine to generate a high-resistance state at the connections of the bus B1. However, the output data "111" from the test machine are used as target data which are compared with switching states which the test machine taps off at the end of the test cycle Zn + 2 'at the connections of the bus B1. In the test cycle Zn + 4 ', the switching states "000" are generated by the automatic test machine at the connections of the bus B1.

Not shown in FIG. 6 is the insertion of additional test cycles. When switching from data output to data input, a test cycle with input values Z for the connections of the bidirectional bus B1 is always inserted in method step 126 according to FIG. 2A when the switchover signal U, as calculated in the simulation, is related to the one under consideration Simulation cycle changes its switching state before the system clock T. If the switchover signal U changes, as shown in FIG. 5, simultaneously with the rising clock edge of the system clock T or only after the rising clock edge of the system clock T has occurred, no additional test cycle is inserted. This procedure means that additional test cycles rarely have to be inserted, since the changeover signal in many modules depends on the system clock T and therefore only switches over after the rising clock edge of the system clock T.

In another exemplary embodiment, a test machine is used in which switching states on bidirectionally operated connections can change at any time. In this case, method steps 112 and 116 according to FIG. 2A do not have to be carried out. Steps 120 and 126 are performed for this test machine in a similar manner as discussed above. However, adjustments are necessary with regard to some additional requirements due to another test machine.

Reference list

10th

Assembly

12th

ASIC

14

Bus driver

16

Interface module

18th

Main memory

20th

processor

22

Cache

24th

Auxiliary storage

26

Input / output unit

28

System bus

30th

to

42

bus
System clock

44

Dash line

100

Simulation of electronic behavior
ISimulation program

102

,

104

Recording file

106

Conversion to SNIP format

108

,

110

File in SNIP format
II conversion program

112

Picking up selected signals
ZP1 time
III tapping program
Zn simulation cycle

114

File in SNIP format

116

Shift the combinatorial input signals and all changeover signals
ZP2 simulation time
IV shift program

118

File in SNIP format

120

Tapping all signals to ZP

3rd

a and ZP

3rd

b
ZP3a,
ZP3b simulation time

122

,

124

File in SNIP format

126

Generate tester-compatible waveforms
VIGeneration program
ZP4a 'to ZP4f' test time
Zn'test cycle

128

,

130

File in SNIP format

132

Conversion to the data format of the test machine
VII Transformation program

134

File in tester format
Zn, Zn + 1 simulation cycle
t'Simulation time

150

Timeline

152

to

156

Cycle limit for simulation cycle

152

' to

156

'' Cycle limit for test cycle

160

to

168

Waveform

170

Pulse signal

170

'Pulse signal
Pulse width
TDT clock delay
A entrance
TDAZn delay time
TDAZn + 1 delay time
Combinatorial input
B1Bus

180

Timeline
t'test time

160

' to

168

'' Waveform
Zn ',
Zn + 1'test cycle

200

Timeline
Zn to Zn + 4 simulation cycle

202

to

212

Cycle limit for simulation cycle

202

' to

212

'' Cycle limit for test cycle
Switchover signal

220

to

224

Waveform
Ffill date

230

Timeline
Zn 'to Zn + 4'test cycle
Z value for high resistance state
ZP1 * to ZP3b * time of simulation
ZP4a * to ZP4b * time of simulation

Claims (17)

1. Method for testing an integrated circuit ( 12 ),
in which a model of a circuit arrangement ( 10 ) containing the integrated circuit ( 12 ) and further electronic functional units ( 14 to 42 ) is defined in a data processing system according to a circuit description language (VHDL),
the function of the circuit arrangement ( 10 ) is checked on the basis of the model by the data processing system in a simulation run (step 100 ),
switching states are calculated during the simulation run with partial models of the further electronic functional units ( 14 to 42 ) which define switching states at inputs (A, B, C) of the integrated circuit ( 12 ),
with an IC model of the integrated circuit ( 12 ) from the switching states at the inputs (A, B, C) switching states at the outputs of the integrated circuit ( 12 ) are calculated,
in at least one recording file ( 102 , 104 ), the switching states occurring during the simulation run on at least some of the connections of the integrated circuit ( 12 ) and associated simulation times (ZP) are stored,
test data for an automatic test machine are generated from the data contained in the recording file ( 102 , 104 ) (steps 106 , 112 , 116 , 120 , 126 , 134 ),
after an error-free simulation run (step 100 ) the integrated circuit ( 12 ) is produced,
and in which the integrated circuit ( 12 ) is tested with the test machine using the test data. 2. The method according to claim 1, characterized in that a periodic signal (T) of the circuit arrangement ( 10 ) is used as a reference signal for setting cycle limits ( 152 to 156 ; 152 'to 156 '), and that the cycle limits ( 152 to 156 ) Define sequential simulation cycles (Zn) for the simulation and temporally successive test cycles (Zn ') for the testing. 3. The method according to claim 2, characterized in that the time period determined by the simulation times at the cycle limits ( 152 to 156 ) of a simulation cycle (Zn) is shorter than the duration of a test cycle (Zn '). 4. The method according to claim 2 or 3, characterized in that the test data is generated so that changes from Switching states of the same signal in different tests cycles only at the same time interval from the beginning of the test cycle. 5. The method according to any one of claims 2 to 4, characterized in that the test data are generated so that the switching states at bidirectional connections (B1) of the integrated circuit ( 12 ) only at the cycle limits ( 152 to 156 ) of the test cycles ( Zn) change. 6. The method according to claim 5, characterized in that in each simulation cycle (Zn, Zn + 1) at a same sampling time (ZP1) for all simulation cycles within the respective simulation cycle (Zn) the switching state of at least one switching signal (U) is determined, the switching state indicates whether the switching signal (U) influenced bidirectional connections of the integrated circuit ( 12 ) in the respective simulation cycle (Zn) work as inputs or as outputs (step 112 ). 7. The method according to claim 6, characterized in that the signal curve of the changeover signal (U) is changed so that the switching state determined at the first sampling time (ZP1) already occurs at a first shifting time (ZP2) lying within the same simulation cycle before the first sampling time , which has the same time interval to the beginning of the respective simulation cycle (Zn, Zn + 1) for all simulation cycles (Zn, Zn + 1) (step 116 ). 8. The method according to any one of claims 5 to 7, characterized in that the switching of the bidirectional connections from input to output and from output to input is controlled by an internal switching signal (U), which is not on a connection of the integrated circuit ( 12 ) is tapped. 9. The method according to any one of claims 5 to 8, characterized in that the switching state of selected input signals (Zn) in each simulation cycle (Zn) at the same for all simulation cycles (Zn) second sampling time (ZP1) within the respective simulation cycle (Zn) C) of the integrated circuit ( 12 ) it is averaged (step 112 ), and that the selected input signals (C) are present at inputs which act exclusively on components with combinatorial basic functions on outputs of the integrated circuit ( 12 ). 10. The method according to claim 9, characterized in that the first sampling time (ZP1) with the second sampling time (ZP1) in the respective simulation cycle (Zn) is identical. 11. The method according to any one of claims 9 to 10, characterized in that the signal curve of the selected input signals (C) is changed so that the switching state determined at the second sampling time (ZP1) is already at a within the same simulation cycle before the second sampling time ( ZP1) second shift time (ZP2) occurs, which has the same time interval to the beginning of the respective simulation cycle (Zn) for all simulation cycles (Zn) (step 116 ) 12. The method according to claim 11, characterized in that the first postponement (ZP2) with the second Shift time (ZP2) in the respective simulation cycle klus (Zn) is identical. 13. The method according to any one of claims 5 to 12, characterized characterized in that an additional test cycle with high-resistance switching states at bidirectional connections the integrated circuit when switching the Switching signal (U) for bidirectional connections from Output on input is only inserted if the un processed changeover signal (U) in its switching state within the respective simulation cycle (Zn) before the periodic signal (T) changes. 14. The method according to any one of the preceding claims, characterized in that the integrated circuit ( 12 ) is a so-called user-specific integrated circuit (ASIC). 15. The method according to any one of the preceding claims, characterized in that the integrated circuit ( 12 ) operates independently of the further electronic functional units ( 14 to 42 ) during testing. 16. Method for generating test data for testing an integrated circuit ( 12 ),
in which a model of a circuit arrangement ( 10 ) containing the integrated circuit ( 12 ) and further electrical functional units ( 14 to 42 ) is defined in a data processing system in accordance with a circuit description language (VHDL),
the function of the circuit arrangement ( 10 ) is checked on the basis of the model by the data processing system in a simulation run (step 100 ),
switching states are calculated during the simulation run with partial models of the further electrical functional units ( 14 to 42 ), which define switching states at inputs (A, B, C) of the integrated circuit ( 12 ),
with an IC model of the integrated circuit ( 12 ) from the switching states at the inputs (A, B, C) switching states at the outputs of the integrated circuit ( 12 ) are calculated,
in at least one recording file ( 102 , 104 ), the switching states occurring during the simulation run on at least some of the connections of the integrated circuit ( 12 ) and associated simulation times (ZP) are stored,
test data for a test machine are generated from the data contained in the recording file ( 102 , 104 ),
wherein the test data units, the interface (44) between the integrated circuit (12) and the further function (14 to 42) relate to, so that the integrated circuit (12) (14 to 42) can work independently of the other functional units in the test. 17. Data processing system for generating test data, in particular for carrying out the method according to claim 16.
with a processor for processing processor instructions, a memory unit for storing at least one recording file ( 102 , 104 ), which contains switching states that occurred during a simulation run on at least some of the connections of an integrated circuit ( 12 ) and associated simulation times (ZP),
the function of the circuit arrangement ( 10 ) is checked during the simulation run (step 100 ) using a model defined in accordance with a circuit description language (VHDL) of a circuit arrangement ( 10 ) containing the integrated circuit ( 12 ) and further electronic functional units ( 14 to 42 ),
a command sequence of processor commands stored in the memory unit, when processed by the processor from the data contained in the recording file ( 102 , 104 ) test data for an automatic test machine for testing the manufactured integrated circuit ( 12 ) are generated,
characterized in that the command sequence is structured such that the test data relate to the interface ( 44 ) between the integrated circuit ( 12 ) and the further functional units ( 14 to 42 ) and a test of the integrated circuit ( 12 ) independently of the other Allow functional units ( 14 to 42 ).