DE19737916A1 - Mask for the production of semiconductor wafers or other micro structures - Google Patents

Mask for the production of semiconductor wafers or other micro structures

Info

Publication number
DE19737916A1
DE19737916A1 DE19737916A DE19737916A DE19737916A1 DE 19737916 A1 DE19737916 A1 DE 19737916A1 DE 19737916 A DE19737916 A DE 19737916A DE 19737916 A DE19737916 A DE 19737916A DE 19737916 A1 DE19737916 A1 DE 19737916A1
Authority
DE
Germany
Prior art keywords
mask
structures
production
geometry
semiconductor wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19737916A
Other languages
German (de)
Inventor
Reinhard Dr Galler
Traugott Dr Schulmeis
Hans Hartmann
Thomas Waas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EQUICON SOFTWARE GmbH
Original Assignee
EQUICON SOFTWARE GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EQUICON SOFTWARE GmbH filed Critical EQUICON SOFTWARE GmbH
Priority to DE19737916A priority Critical patent/DE19737916A1/en
Publication of DE19737916A1 publication Critical patent/DE19737916A1/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors

Abstract

The production of semiconductor devices is made using a photographic mask that is used to reproduce a specific geometric structure. The imaging process is such that structure distortions can occur due to reflections, refractions, etc. The process allows the mask structure to be modified based upon the image errors and so allows a correct structure to be obtained

Description

Gegenwärtig wird das Layout von Entwurfsebenen von Halbleiterbauelementen durch einfache geometrische Figuren beschrieben. Die Übertragung des Layout auf das Halbleitermaterial (Wafer) erfolgt mit Hilfe von Masken, auf die das Layout mit einem bestimmten Maßstab übertragen wird. Die geometrischen Strukturen auf Halbleitermasken sind ebenso wie das Layout mit sehr einfachen geometrischen Mitteln beschrieben. Die damit möglichen Strukturen sind alle geradlinig berandet mit der zusätzlichen Einschränkung, daß die Kanten entweder parallel zu den Achsen des Bezugs-Koordinatensystems angeordnet sind oder feste Winkel zu den Achsen einhalten müssen (z. B. 45°). Die beim Abbildungsprozeß von der Maske auf den Wafer auftretenden Abbildungsfehler (durch z. B. Reflexion, Beugung, Brechung, Streuung) werden dadurch kompensiert, daß die Größe der geometrischen Struktur so verändert wird, daß die auf dem Wafer erzeugte Struktur der gewünschten Struktur möglichst nahe kommt. Die Form der Struktur auf der Maske bleibt unverändert.Currently, the layout of design levels of semiconductor devices is underway described simple geometric figures. Transferring the layout to the Semiconductor material (wafers) is made with the help of masks, on which the layout with a certain scale is transmitted. The geometric structures Semiconductor masks are just like the layout with very simple geometric Means described. The structures that are possible with it are all straight-edged the additional restriction that the edges are either parallel to the axes of the Reference coordinate system are arranged or fixed angles to the axes must adhere (e.g. 45 °). The process from the mask to the wafer during the imaging process Imaging errors that occur (e.g. through reflection, diffraction, refraction, scattering) are compensated for by changing the size of the geometric structure is that the structure of the desired structure produced on the wafer is as possible comes close. The shape of the structure on the mask remains unchanged.

Diese Art der Gestaltung der Maske berücksichtigt zwar die Abbildungsfehler und kompensiert sie zum Teil, doch es bleibt immer ein Restfehler. Dadurch weicht die auf dem Chip erzeugte Struktur immer von der Struktur des Layout ab. Der Einfluß des Restfehlers steigt in dem Maße, in dem sich die Strukturgrößen verringern.This type of mask design takes into account the aberrations and it partially compensates, but there is always a residual error. This softens it Structure created on the chip always depends on the structure of the layout. The influence of Residual error increases as the structure sizes decrease.

Ein weiterer Nachteil des Standes der Technik ist in dem Umstand begründet, daß die entworfenen Strukturen ausschließlich auf einfache geometrische Figuren reduziert und vereinfacht sind und sich daher nur angenähert an den elektrischen/elektronischen Eigenschaften der herzustellenden Strukturen orientieren. Bereits im Entwurf werden Vereinfachungen auf Kosten der Funktionsparameter des Erzeugnisses vorgenommen.Another disadvantage of the prior art is due to the fact that the designed structures reduced to simple geometric figures and are simplified and therefore only approximate to the electrical / electronic Orient properties of the structures to be manufactured. Already in the draft Simplifications made at the expense of the functional parameters of the product.

Aufgabe der Erfindung ist es daher, die Geometrie der Maske, oder Teile davon, so zu gestalten, daß die durch Projektion der Maske und nachfolgende Prozeßschritte auf den Halbleitern oder sonstigen mikrostrukturierten Objekten entstandenen Strukturen vollständig oder zum Teil dem gewollten und unvereinfachten Layout entsprechen. The object of the invention is therefore to reduce the geometry of the mask, or parts thereof shape that by projecting the mask and subsequent process steps on the Semiconductors or other microstructured objects fully or partially correspond to the desired and uncomplicated layout.  

Gelöst wird diese Aufgabe dadurch, daß die Geometrie der Strukturen der Maske die Abbildungsfehler sowie sonstige prozeßbedingte Verfälschungen vollständig berücksichtigt, so daß sie kompensiert werden können. Auf diese Weise entstehen auf der Maske beliebige krummlinig oder geradlinig berandete Strukturen, die durch das berücksichtigte und eingerechnete Wirken der Abbildungsfehler und sonstigen prozeßbedingten Verfälschungen dazu führen, daß die Zielstrukturen exakt den im Layout vorgegebenen geradlinig und/oder krummlinig berandeten Strukturen entsprechen. Die entworfene Struktur wird geometrieerhaltend auf der Maske dargestellt.This problem is solved in that the geometry of the structures of the mask Image errors as well as other process-related falsifications completely taken into account so that they can be compensated. In this way arise on any curvilinear or rectilinear structures bordered on the mask by the considered and included effects of aberrations and other process-related falsifications lead to the fact that the target structures exactly in the Layout predefined linear and / or curvilinear structures correspond. The designed structure becomes geometry preserving on the mask shown.

Mit der erfindungsgemäßen Lösung ist es möglich, Masken so zu gestalten, daß Abbildungsfehler und sonstige prozeßbedingte Verfälschungen, wie etwa Proximity-Ef­ fekte, praktisch keinen Einfluß auf die elektrischen Eigenschaften der Halbleiterelemente haben. Die Geometrie der auf den hergestellten Halbleitern oder sonstigen mikrostrukturierten Objekten erzeugten Strukturen entsprechen den entworfenen Strukturen, die ihrerseits keinen Einschränkungen und Vereinfachungen unterworfen sind. Dadurch erhöht sich die Performance und die Ausbeute der hergestellten Halbleiterelemente oder sonstigen mikrostrukturierten Objekte.With the solution according to the invention it is possible to design masks in such a way that Imaging errors and other process-related falsifications, such as Proximity-Ef fect, practically no influence on the electrical properties of the Have semiconductor elements. The geometry of the semiconductors or manufactured other microstructured objects structures correspond to designed structures, which in turn have no restrictions and simplifications are subject. This increases the performance and the yield of the manufactured semiconductor elements or other microstructured objects.

Die Lösung der Aufgabe kann auch dadurch erfolgen, daß nur ein Teil der Geometrie der Strukturen der Maske die Abbildungsfehler sowie sonstige prozeßbedingte Verfälschungen vollständig berücksichtigt. Die verbleibenden Teile der Maske werden in herkömmlicher Weise gestaltet. Auf diese Weise befinden sich auf der Maske Bereiche, die zu exakten Zielstrukturen führen, neben Bereichen, die zu Zielstrukturen führen, die mit bekannten und beherrschbaren Abweichungen behaftet sind. Der hohe Aufwand, den exakte Zielstrukturen, die den im Layout vorgegebenen geradlinig und/oder krummlinig berandeten Strukturen entsprechen, bedürfen, wird nur in den Bereichen betrieben, wo er zu deutlichen Vorteilen, wie Erhöhung der Performance und der Ausbeute der hergestellten Halbleiterelemente oder sonstigen mikrostrukturierten Objekte führt.The problem can also be solved in that only part of the geometry the structures of the mask the aberrations as well as other process-related Falsifications fully taken into account. The remaining parts of the mask will be designed in a conventional way. This way you are on the mask Areas that lead to exact target structures, in addition to areas that lead to target structures lead, which are afflicted with known and manageable deviations. The height Effort, the exact target structures that are straightforward in the layout and / or structures with curvilinear borders, is only required in the Operated in areas where it has significant advantages such as increasing performance and the yield of the semiconductor elements or other microstructured manufactured Objects leads.

Claims (3)

1. Maske zur Herstellung von Halbleitern oder sonstigen mikrostrukturierten Objekten, dadurch gekennzeichnet, daß die Geometrie der krummlinig berandeten Strukturen der Maske Abbildungsfehler sowie sonstige prozeßbedingte Verfälschungen berücksichtigt.1. Mask for the production of semiconductors or other microstructured objects, characterized in that the geometry of the curvilinear structures of the mask takes account of aberrations and other process-related falsifications. 2. Maske nach Anspruch 1, dadurch gekennzeichnet, daß krummlinig entworfene Strukturen geometrieerhaltend auf der Maske realisiert sind.2. Mask according to claim 1, characterized in that curvilinear designed Structures preserving geometry are realized on the mask. 3. Maske nach den Ansprüchen 1 und 2, dadurch gekennzeichnet, daß krummlinig entworfene Strukturen teilweise geometrieerhaltend auf der Maske realisiert sind.3. Mask according to claims 1 and 2, characterized in that curvilinear designed structures are partially implemented on the mask while maintaining geometry.
DE19737916A 1997-08-26 1997-08-26 Mask for the production of semiconductor wafers or other micro structures Ceased DE19737916A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19737916A DE19737916A1 (en) 1997-08-26 1997-08-26 Mask for the production of semiconductor wafers or other micro structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19737916A DE19737916A1 (en) 1997-08-26 1997-08-26 Mask for the production of semiconductor wafers or other micro structures

Publications (1)

Publication Number Publication Date
DE19737916A1 true DE19737916A1 (en) 1999-03-04

Family

ID=7840692

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19737916A Ceased DE19737916A1 (en) 1997-08-26 1997-08-26 Mask for the production of semiconductor wafers or other micro structures

Country Status (1)

Country Link
DE (1) DE19737916A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10042929A1 (en) * 2000-08-31 2002-03-21 Infineon Technologies Ag OPC method for generating corrected patterns for a phase shift mask and its trimming mask, as well as the associated device and integrated circuit structure
DE10115294C1 (en) * 2001-03-28 2002-08-08 Infineon Technologies Ag Mask for the projection of a structure for producing an integrated circuit on a wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10042929A1 (en) * 2000-08-31 2002-03-21 Infineon Technologies Ag OPC method for generating corrected patterns for a phase shift mask and its trimming mask, as well as the associated device and integrated circuit structure
US6664010B2 (en) 2000-08-31 2003-12-16 Infineon Technologies Ag OPC method for generating corrected patterns for a phase-shifting mask and its trimming mask and associated device and integrated circuit configuration
DE10115294C1 (en) * 2001-03-28 2002-08-08 Infineon Technologies Ag Mask for the projection of a structure for producing an integrated circuit on a wafer

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8139 Disposal/non-payment of the annual fee
8110 Request for examination paragraph 44
8170 Reinstatement of the former position
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