DE19734248A1 - Method and device for transmitting sensor output signals between asynchronously operating sensors and their respective data processing devices - Google Patents

Abstract

The invention relates to a method and corresponding circuit for pulse redistribution of pwm sensor output data (pi), for example from inertial sensors. The method is characterized in that the scanning interval (s2) of a data processing device, which processes the output signals of one or more sensors, is independent of the length and of the phase position of the limit cycle (s1) or limit cycles (s1) of the sensor(s). In addition, a range transfer of sensors having different working ranges is possible, irrespective of the scanning interval of the data processing device. As a result, incorrect sensor output data can be easily recognized.

Description

The invention describes a method for transmitting the sensor output signals of inertial sensors to their respective data processing devices and a facility that works according to the procedure.

As can be seen in FIG. 6, an inertial measurement unit (IMU) uses a set of inertial sensors, for example gyroscopes or accelerometers, to measure all possible rotary and translatory movements. FIG. 6a shows a sensor 41 that converts physical movement into a sensor output signal which is evaluated by a data processing device 42. As FIG. 6b shows, a plurality of sensors 41 can be connected to a data processing device 42 . Such a unit is functionally independent and is referred to as a strand. To achieve an availability requirement that goes beyond everything, an IMU is composed of several such lines in a redundant configuration. Here, all sensor output signals of all strands are distributed to all data processing devices 42 of all strands, as shown in FIG. 6c.

The sensors used for high-resolution inertial measurement apply a reset control for every degree of freedom in order to convert the physical movement into an electrical signal. The signal given by this control loop is a digital pulse width modulated (pwm) signal p _i , which can assume the possible states "0" and "1". The relationship between the "0" and the "1" periods, commonly referred to as the duty cycle of the pwm signal, over a given interval is directly related to the physical movement of the sensor during that interval. The interval, usually a period of the pwm signal, is called the limit cycle.

FIG. 7 shows the numerical processing of the pulse-width-modulated sensor output signal p _i coming from the sensor 41 . For this numerical processing, the data processing devices quantize the output signals of the sensors by counting the number of periods of a known clock signal, normally the sensor clock signal f ₀ , during the "0" and "1" periods of the pwm signal. For this purpose, an up / down counter 43 is used, the duration of the "1" periods of the pwm signal by an incrementation and the duration of the "0" periods of the pwm signal by a decrementation with each period of the clock signal f ₀ "measures". After each sampling interval, a read clock signal causes the counter value to be transferred to a register 44 and the counter 43 to be reset. The counter value c stored in the register 44 , ie the difference between counting up / down, is directly proportional to the physical movement sensed by the sensor 41 .

The resolution of some sensors, and thus their working area, can be determined by the Switching the gain of the control loop of the respective sensor between "High" and "Low" can be switched. Such a switch is possible before or after a limit cycle.

Each sensor 41 sends its own clock f _0, its pwm output signal p _i and a work area identification signal r _i in the form of its control loop gain (“high” or “low”) to all data processing devices 42 .

For reasons of integrity, the respective data processing devices 42 of an inertial measuring unit work independently of one another. The time frame for data processing is only synchronized by the limit cycle of its own sensors 41 .

Due to small differences between the clock frequencies of the individual sensors 41, the sampling interval of the data processing means 42 in the comparison with the limit cycle of a PWM output signal shows a sensor 41 of another sensor 41, a small phase drift. This creates an aliasing effect, which is noticeable in that an oscillating measurement error with a triangular waveform arises (with a constant sensor output signal). The error amplitude of this measurement error is the value of the actual sensor output signal and the frequency is proportional to the clock difference of the two sensors.

If a sensor 41 switches the gain of the reset loop during the sampling interval of the data processing device 42 between "high" and "low", then the data processing device 42 can not determine the correct time relationships of the working areas "low" and "high". The conversion result of this sampling interval must therefore be rejected, which results in a measurement error.

The zero point error and the scale factor of the sensors 41 are compensated for during the data processing of their sensor data. If different calibration parameters are required for the "high" and "low" work areas, the correct size of the compensation parameters cannot be calculated by the compensation algorithm if a sensor 41 switches its work area during the sampling period of the data processing device 42 .

A sensor output signal generated by the sensor getting stuck provides apparently correctly usable data and cannot be corrected by kor direct change results can be distinguished.

The invention is therefore based on the object of a method for transmission the output signals of inertial sensors to their respective data processing beitungseinrichtung indicate that the disadvantages of the previously described Does not have the prior art. The invention is also based on the object reasons to specify a device that according to the inventive Ver driving can work.

The method according to the invention is in independent claim 1 Are defined. An inventive device that ar is defined in the independent claim 4. Advantageous Wei Further training of the procedure and the facility can be found in the subordinate dependent claims.

The inventive method of redistributing the pulse-width-modulated sensor output signal p _i into a transmission signal p _o , which is resampled after the transmission and before the data processing, can both the aliasing effect ver with the same requirements for the number of transmission lines from a sensor 41 to a data processing unit 42 are prevented, as well as the correct time relationships are maintained when switching the working areas of a sensor. As a result, the compensation algorithm can always calculate the correct compensation parameters. Furthermore, according to the invention, the errors resulting from the sensor getting stuck can be recognized and evaluated,

The invention and advantageous details are described below with reference on the drawings in exemplary embodiments explained. Show it:

Fig. 1 is a pulse redistribution circuit 1 according to the invention;

Figure 2 is a signal converting device according to the invention consisting of a pulse redistribution circuit 1 and a recovery circuit. 2;

Fig. 3 is a signal converting device according to the invention with the pulse redistribution circuit 1 and the recovery circuit 2 applied signals;

Fig. 4 shows a second embodiment of a signal conversion device according to the invention;

Fig. 5 shows an inventive error detection circuit for the exemplary embodiment according to Fig. 4;

Fig. 6 is a general illustration of the interaction between sensors and data processing units of an inertial measurement unit; and

Fig. 7 shows a data processing circuit according to the prior art.

In the figures, the same construction elements are identified by the same reference symbols called te.

Fig. 1 shows a pulse redistribution circuit according to the invention 1, which can pwm sensor output signal p _i scans behind each sensor and a newly generated transmission signal p _o to a data processing circuit 42 transmitted.

This pulse redistribution circuit 1 consists of an input-side counter 3 , at the clock input of which the sensor clock signal f ₀ and at the reset input of which a sensor sampling interval signal s _{1 are} present, which comprises 2 ⁿ periods of the sensor clock signal f ₀ , that is to say the sensor clock signal divided by 2 ⁿ f is ₀ . The pwm sensor output signal p _{i is present} at the enable connection of the counter 3 . The counter 3 increments a counter value k in time with the sensor clock signal f ₀ if a high level is present at its enable connection, that is to say if the pwm sensor output signal p _{i has} a high level "1".

After a period of the sensor probe interval signal s ₁ , the counter is reset and the counter value k is written into a first register 4 . Due to the period of the sensor sampling interval signal s _{1, the} counter value k can at most assume the value 2 ⁿ . In a binary representation, this value has a width of n + 1 bit. The sensor sampling interval signal s _{1 is present} at the clock input of the first register 4 and the n + 1 bit wide counter value k is present at its signal input. As a result, the n + 1 bit wide counter value k is loaded into the first register 4 at the end of each sensor sampling interval. The first register 4 outputs the MSB (Most Significant Bit) of the n + 1 bit wide counter value k, ie the bit n + 1, to the OR gate 7 . Furthermore, the first register 4 outputs the n lower bits of the counter value k to a modulo 2 ⁿ adder during the sensor sampling interval following the loading.

This modulo 2 ⁿ adder is connected in such a way that it adds the n lower bits of the counter value k during a sensor sampling interval in time with the sensor clock signal f ₀ and always outputs a carry signal when a carry is generated with the n-bit addition .

The MSB of the n + 1 bit wide counter value k, that is to say the bit n + 1 and the carry signal output by the modulo 2 ⁿ adder, are applied to an OR gate 7 , the output signal of which is transmitted as a transfer signal p _o to a data processing device 42 can, which can evaluate the redistributed sensor output signal via an upstream recovery circuit 2 . Through this circuitry, the transmission signal p _o consists of a number of k evenly distributed pulses during a sensor sampling interval.

The modulo 2 ⁿ adder consists of an adder 6 , which receives the n lower bits of the counter value k at a first signal input and a second register 5 . The n bit wide output signal of the adder 6 is applied to the signal input of the second register 5 , at the clock input of which the sensor clock signal f ₀ and at the reset input of the sensor scanning interval signal s _{1 are} present. The n bit wide output signal of the second register 5 is applied to a second signal input of the adder 6 . In this way, the second register 5 loads the current output signal of the adder 6 with each period of the sensor clock signal f ₀ and in turn applies this to a signal input of the adder 6 . Since the lower n bits of the counter value k are constantly applied to the first signal input of the adder 6 during a sensor sampling interval, 2 ⁿ additions of the n lower bits of the counter value k are carried out in this way in one sensor sampling interval. Every time a carry signal is generated during one of these additions, this is applied to the OR gate 7 by the modulo 2 ⁿ adder.

In this way, the modulo 2 ⁿ addition for 0 ≦ k ≦ 2 ⁿ -1 generates a number of k logical ones for the signal p _o , which are evenly distributed over a period of s ₁ .

For k = 2 ⁿ , 2 ⁿ logical ones are generated for the signal p _o , since the MSB of the n + 1 bit wide counter value k is linked to the carry signal of the adder.

This pulse redistribution algorithm can also be used for sensors that output digital data words (the value k) instead of pwm signals. In this case, counter 3 is not required.

Such a procedure allows the data processing electronics to restore the signal p _o at arbitrary times, the maximum conversion error for added data due to the aliasing effect being a quantization unit, that is to say a clock period of the sensor clock signal f ₀ . This is independent of the number of receiver sampling intervals, which can have an arbitrary length and an arbitrary phase position with respect to the sensor sampling intervals.

Fig. 2 shows a total signal conversion circuit according to the invention. On the left side, the pulse redistribution circuit 1 shown in FIG. 1 can be seen, which receives the output signal p _i and the sensor clock signal f _{0 from} the sensor. It also receives the signal s _{1 derived} from the sensor clock signal, which indicates the length of the sensor sampling interval. The Pulsum distribution circuit 1 passes the generated transmission signal p _o to the recovery circuit 2 , which is a data processing circuit 42 upstream.

The recovery circuit 2 has a 1: 2 decoder 8 , which receives the transmission signal p _o . Depending on the state of the transmission signal p _o , the 1: 2 decoder 8 generates an enable signal for one of two counters 9 and 10 present in the recovery circuit 2 . The counters 9 and 10 each count the sensor clock signal f _{0 present} at their clock input when they are released. In this way, depending on the transmission signal p _o, either the counter 9 or the counter 10 counts. Depending on a receiver sampling interval, which is indicated by a read clock signal s ₂ , the counter readings of the counters 9 and 10 are each transferred to registers 11 and 12 and reset to 0.

The read clock signal s ₂ does not have to be synchronized to the sensor clock signal f ₀ or to the sensor sampling interval signal s ₁ , which indicates 2 ⁿ periods of the sensor clock signal. For this purpose, it can be out of phase and / or have a different frequency.

The recovery circuit 2 thus uses different counters 9 and 10 to separately measure the ones and zeros of the transmission signal p _o , that is to say the redistributed sensor output signal p _i , whereby two counter values c⁺ and c⁻ are obtained during a receiver sampling interval. These are temporarily stored in a register 11 , 12 during the following receiver sampling interval. A value c, which represents the physical movement seen by the sensor, is given by the equation c = c⁺ - c⁻.

FIG. 3a shows a signal conversion circuit according to the invention, ie the pulse redistribution circuit 1 and the recovery circuit 2 applied to the them and discharged from them signals. Except for the sensor clock signal f ₀ , these signals are shown by way of example in FIGS . 3b to 3f. FIG. 3b shows the signal s _1, the per period 2 ⁿ periods of the sensor clock signal f ₀ comprises. The Fig. 3c shows the pulse width modulated Sen sorausgangssignal p _i. Fig. 3d shows the circuit by the pulse redistribution 1-converted sensor output signal p _o. This transmission signal p _o is no longer dependent on the sensor sampling interval. Accordingly, the receiver sampling interval defined by the signal s ₂ shown in FIG. 3e can have any length and any phase position with respect to the sensor sampling interval defined by the signal s ₁ shown in FIG. 3b. Finally, FIG. 3f shows signal c, which represents the digital counter value generated during each receiver sampling interval.

The output signals from sensors that have several working areas can be converted and recovered using the method according to the invention. The transmission of a work area identification signal r _i emitted by the sensor is necessary for unambiguous assignment during the recovery.

A signal conversion circuit with pulse redistribution and recovery circuit for sensors operating in two areas is shown in FIG. 4. The pulse redistribution circuit 1 is constructed in accordance with FIG. 1 and accordingly receives the sensor clock signal f ₀ , the pulse-width-modulated sensor output signal p _i and the sensor sampling interval signal s ₁ . A work area identification signal r _i generated by the sensor is converted into a delayed work area identification signal r _o by a delay circuit 13 , which also receives the signal s ₁ . The transmission signal p _o and the delayed work area identification signal r _o are applied to a 2: 4 decoder 14 . The operating range identification signal r _i is in each case delayed such that the delayed operating range identification signal r _o diert to the generated just by the pulse redistribution circuit 1 transmission signal p _o corres.

The 2: 4 decoder 14 generates four output signals, each of the two states "0", based on the four possible signal combinations of the input signals p _o and r _{o applied to it} , which can each take the two states "0" and "1""and" 1 "can assume and of which, depending on the state of the input signals, a certain one has a certain state, while the others have the other state. The output signals are applied as enable signals to counters 15 to 18 , at the clock input of which the sensor clock signal f ₀ is applied. In this way, depending on the state of the transmission signal p _o and the delayed work area identification signal r _o , one of the counters 15 to 18 counts in time with the sensor clock signal f ₀ .

As in the circuit of FIG. 2, the counter readings at the end of each receiver sampling interval, which is indicated by the signal s ₂ , are transferred to registers 19 to 22 , after which the counters 15 to 18 are reset. The registers now show the state of the transmission signal p _o for each working area of the sensor. In the selected example, a counter value of 1 door would result in a low working range of the sensor from the difference between the values l⁺ are l⁻ stored in register 19 and register 20 , in this case to l = l⁺ - l⁻. A value h representing the physical movement of the sensor in its high working range is correspondingly given by the difference between the counter values h⁺ and h⁻ stored in registers 21 and 22 , in this case to h = h⁺ - h⁻.

The transmission of the sensor output signals according to the invention has the further advantage that an error detection can be carried out on the receiver side. A block diagram of an error detection circuit that matches the recovery circuit shown in FIG. 4 is shown in FIG . Here the four different register values l⁺, l⁻, h⁺ and h⁻ serve as input signals. In the recovery according to the invention, the sum of all counter values relating to a sensor must be equal to the number of f ₀ clock pulses per s ₂ sampling interval, and is therefore constant for unchanged lengths of the receiver sampling interval. "Hanging" errors lead to unexpected sums of the counter values and can therefore be easily recognized, since a hanging error has the consequence that the inputs p _i and r _i supply constant values. So that p _o and r _o (after the pulse redistribution) are constant, so that the downstream decoder constantly releases exactly one of the counters 15 to 18 . This has the effect that exactly three of the four counters 15 to 18 and thus also the corresponding three of the four registers 19 to 22 always deliver the value zero. This is an indication of the presence of a hanging error, since this condition is very unlikely in regular operation. According to the prior art, the identification of this state in the necessary sharpness (aliasing scanning error) is not possible.

In the circuit shown in FIG. 5, this sum of all counter values is present at the “interval” output. The counter values l⁺ and l⁻ of the low work area are added by an adder 27 and the counter values h⁺ and h⁻ of the high work area are added by an adder 34 . The respective addition results of adders 27 and 34 are passed to an adder 29 , which thus forms the sum of all counter values.

Furthermore, according to the arrangement according to the invention, the duration of the sensor operation at "high" rate or "low" rate after each receiver sampling interval s _{2 is determined} from the different counter values. As a result, all conversion intervals generate valid conversion results, and an exact range-dependent zero point error compensation can be achieved.

In FIG. 5, the correct movement of the sensor is representing the output value at the output of "Rate". This is generated by adding the differences of the counter values of a respective work area multiplied by a respective scaling factor to the sums of the counter values multiplied by a zero-point error correction, and these addition results of all work areas are in turn added up.

In the circuit shown in Fig. 5 the counter value is l⁻ by an adder 23 of its associated counter value l⁺ subtracted. The difference thus formed is multiplied by a multiplier 24 by a scaling factor available for the low range. The result of this multiplication is fed to an adder 25 , which adds it to the sum of the counter values l⁺ and l⁻, which is formed by the adder 27 and multiplied by the multiplier 26 by a zero point error correction value for the low range. Furthermore, the counter value h⁻ is subtracted from an adder 30 from the counter value h⁺ assigned to it. The difference thus formed is multiplied by a multiplier 31 by a scaling factor available for the high range. The result of this multiplication is fed to an adder 32 , which adds it to the sum of the counter values h⁺ and h⁻, which is formed by the adder 34 and multiplied by the multiplier 33 by a zero point correction value for the high range. The sum of the results of the adders 25 and 32 formed by an adder 28 is the correct output value at the output “rate” which characterizes the movement of the sensor.

Claims (9)

1. A method for converting a pulse width modulated output signal (p _i ) of a sensor such that it can be transmitted to and processed by data processing devices that receive sensor signals from one or more sensors, a sensor in each case in addition to the pulse width modulated output signal (p _i ) also outputs its clock frequency (f ₀ ) and its working range identification signal (r _i ), characterized by the following steps for each sensor sampling interval:

• a) counting the clock cycles of the sensor clock signal (f ₀ ) in a sensor sampling interval, which comprises 2 ⁿ periods of the sensor clock signal (f ₀ ), during which the pulse world modulated sensor output signal (p _i ) has a first level;
• b) n-fold modulo-2 ⁿ addition of the counted clock cycles in time with the sensor clock signal (f ₀ ), a transmission signal (p _o ) being influenced in such a way that it is always by a clock cycle of the sensor clock signal (f ₀ ) switches the second level to a first level when a carry is generated by the modulo 2 ⁿ addition or the bit n + 1 of the number of clock cycles counted in step a) has a first level;
• c) Counting the clock cycles of the sensor clock signal (f ₀ ) in a receiver sampling interval, during which the transmission signal (p _o ) has a second level, for all possible working areas of the sensor
• d) counting the clock cycles of the sensor clock signal (f ₀ ) in a receiver sampling interval, during which the transmission signal (p _o ) has a first level, for all possible operating ranges of the sensor; and
• e) transmitting the respective number of sensor clock cycles counted in step c) during which the transmission signal (p _o ) has a second level and the respective number of sensor clock cycles counted in step d) during which the transmission signal (p _o ) has a first Level, to the respective data processing device (s).

2. The method according to claim 1, characterized in that a respective data processing device for each sensor carries out the following processing steps:

• a) forming the difference between the two numbers counted for each work area;
• b) forming the sum of the two numbers counted for each work area;
• c) forming the product of the difference obtained in step a) and a respective scaling factor;
• d) forming the product of the sum obtained in step b) and a respective zero point correction value; and
• d) forming the sum of the products generated in steps c) and d); and if you have more than one work area, follow the steps:
• e) forming the sum of the totals generated in step d) of all work areas; and
• f) forming the sum of the sums of all work areas generated in step b),
  where in the case of a work area the sum generated in step b) and in the case of several work areas the sum generated in step f) is the sum of all sensor clock cycles in a receiver sampling interval and in the case of a work area the sum generated in step d) and in the case several working areas, the sum generated in step e) is the output value representing the movement of the sensor.

3. The method according to claim 1 or 2, characterized in that he ste level is a high level and the second level is a low level, or that the first level is a low level and the second level is a high level. 4. A device for converting a pulse-width modulated output signal (p _i ) of a sensor into such a form that it can transmit to data processing devices that receive the sensor signals from one or more sensors and can be processed by them, one sensor in each case besides the pulse-width modulated output signal (p _i ) also outputs its clock frequency (f ₀ ) and its work area identification signal (r _i ), characterized by:
a pulse redistribution circuit ( 1 ) which converts a pulse world modulated output signal from a sensor with the aid of its sensor clock signal (f ₀ ) into a digital transmission signal (p _o ) which is uniform over a sensor sampling interval s ₁ , the 2 ⁿ periods of the sensor clock signal (f ₀ ) comprises, distributed first levels, each having the duration of a clock cycle of the sensor clock signal (f ₀ ), and
a recovery circuit ( 2 ) which outputs the number of clock cycles of the sensor clock signal (f ₀ ) during a receiver sampling interval from the digital transmission signal (p _o ) with the aid of the sensor clock signal (f ₀ ) and a delayed work area identification signal (r _o ) , during which the pulse world modulated output signal (p _i ) of the sensor has a first level and a second level in the respective working range. 5. Device according to claim 4, characterized in that the pulse redistribution circuit ( 1 ) contains the following modules:
a counter ( 3 ) at whose clock input the sensor clock signal (f ₀ ), at its reset input a signal s ₁ , which was generated from the sensor clock signal (f ₀ ) divided by 2 ⁿ , and at its enable input the pulse-width modulated output signal ( p _i ) of the sensor,
a first register ( 4 ), at whose signal input the n + 1 bit wide output signal of the counter ( 3 ) and at whose clock input the signal s ₁ is present,
a modulo 2 ⁿ adder ( 5 , 6 ), which represents an output signal of the first register representing the n lower bits of the n + 1 bit wide in the first register ( 4 ), the signal s ₁ and the sensor clock signal (f ₀ ) receives, at each clock period of the sensor clock signal (f ₀ ) performs a modulo 2 ⁿ addition of the n bit wide output signal of the first register ( 4 ), and outputs a carry signal, and
an OR gate ( 7 ), at the first signal input of which a signal representing the highest bit of the n + 1 bit wide first register ( 4 ) and at the second signal input of the carry signal of the modulo-2 ⁿ adder ( 5 , 6 ) is present , and that outputs the digital transmission signal (p _o ). 6. Device according to claim 5, characterized in that the Modu lo-2 ⁿ adder ( 5 , 6 ) contains the following assemblies:
an adder ( 6 ) with two signal inputs, at the first signal input of which the n-bit wide output signal of the first register ( 4 ) is present and which has an n-bit wide output signal representing the sum of the signals present at its two signal inputs and as the output signal of the modulo 2 ⁿ adders outputs a carry signal, and
a second register ( 5 ), at the signal input of the n-bit output signal from the adder ( 6 ), at the clock input of the sensor clock signal (f ₀ ) and at the reset input of the signal s ₁ , and the n-bit output signal at the second signal input of the adder ( 6 ) is present. 7. Device according to one of claims 4 to 6, characterized in that the recovery circuit ( 2 ) contains the following modules:
a decoder ( 8 ), which generates release signals from the digital transmission signal (p _o ) and the delayed work area identification signal (r _o ), each of which is applied to one of its inputs, which for each respective work area of the sensor corresponds to the states of the transmission signal ( p _o ) correspond to
Two counters ( 9 , 10 ; 15 , 16 , 17 , 18 ) per work area, at whose clock input the sensor clock signal (f ₀ ), at their enable input a respective enable signal generated by the decoder ( 8 ) and at the reset input of a read clock signal s ₂ ,
for each counter ( 9 , 10 ; 15 , 16 , 17 , 18 ) one register ( 11 , 12 ; 19 , 20 , 21 , 22 ), at whose clock input the read clock signal s ₂ and at whose signal input an output signal of a respective counter is present . 8. Device according to one of claims 4 to 7, characterized by a data processing device to which the respective number of clock cycles of the sensor clock signal (f ₀ ) is applied during a receiver sampling interval by the recovery circuit ( 2 ) during which the pulse-width modulated output signal (p _i ) of the sensor in the respective working area has a first level and a second level, for each sensor with:
a respective first adder ( 23 , 30 ) for each work area forming the difference of the two numbers counted for each work area;
a respective second adder ( 27 , 34 ) for each work area forming the sum of the two numbers counted for each work area;
a respective first multiplier ( 24 , 31 ) for each work area, which multiplies the difference formed by the respective first adder ( 23 , 30 ) by a respective scaling factor;
a respective second multiplier ( 26 , 33 ) for each work area, which multiplies the sum formed by the respective second adder ( 27 , 34 ) by a respective zero-point error correction value; and
a respective third adder ( 25 , 32 ) for each work area, which adds the products generated by the respective first multiplier ( 24 , 31 ) and the respective second multiplier ( 26 , 33 ); and with more than one work area:
a fourth adder ( 28 ) which adds the sums formed by the respective third adders ( 25 , 32 ); and
a fifth adder ( 29 ) which adds the sums generated by the respective second adders ( 27 , 34 ). 9. Device according to one of claims 4 to 8, characterized in net that the first level is a high level and the second level is a low Pe gel, or that the first level is a low level and the second level is on is high level.