DE19728465A1 - Serial input and output circuit and interface for serial bus - Google Patents

Abstract

The serial input/output circuit 13 operates with a port input/output circuit 4-12 of an I<2>C bus interface. The bidirectional serial bus has a clock line SCL and a data line SDA with the voltage provided by a pull up resistor. The circuit has a start detector circuit coupled to the output line that is used in control of the input /output circuit activation.

Description

The invention relates to a serial input / output circuit arrangement (I / O circuit arrangement) which can implement a serial bus interface circuit arrangement which, in cooperation with port input / output circuits, an interface between a component, for example a center len processing unit, and a bidirectional serial bus, for example an I ² C bus.

Serial input / output circuit arrangements are used in practice to implement I ² C bus interface circuit arrangements. The I ² C bus proposed by Philips is a two-wire bidirectional serial bus that consists of a serial clock line (SCL) and a serial data line (SDA). A large number of devices or components, for example a microcontroller, an LCD (liquid crystal display) driver, a gate array, an ADC (analog / digital converter), a static RAM or an EEPROM etc. can be used with the I ² C -Bus to be connected. One of the large number of devices can be a leading device with priority - and thus a so-called "master" or a management device of the system - and then data to a subordinate or subsequent device - which is a "slave" or a subsequent device represents - transmitted by addressing the same.

The following is a simple description of the I ² C bus specifications. A device connected to the I ² C bus must have open drain connections for both the SDA and SCL lines. In addition, both the SDA and SCL lines are pulled to a positive voltage by pull-up resistors. As a result, wired AND connections are made between the SDA line and the SCL line of the I ² C bus and each of the I ² C bus interface circuits connected to the I ² C bus. If no device uses the I ² C bus, both the SCL line and the SDA line are kept in their respective high-level states (HIGH). While data is being transferred from one device to another device, the state of the SDA line must be maintained if the SCL line is maintained in its high level. Only when the SCL line is kept in its low level (LOW) can a change in the state of the SDA line be permitted during the transfer of data. There are two exceptions to this rule; one is the creation of an initial or initial condition, and the other is the creation of a stop or end condition. An initial condition is triggered by a falling edge of the SDA line when the SCL line is kept in its high level. In contrast, an end condition is triggered by a rising edge of the SDA line when the SCL line is kept in its high-level state.

Data to be transmitted via the I ² C bus consist of 8 bits (or one byte). A acknowledgment bit is added to the end of each byte wide date. If a receiver correctly receives a byte-wide data and has received the ninth clock signal on the SCL line since receiving the first data bit, it provides a feedback signal to a corresponding transmitter by causing the SDA line to transition from high level to the low level. There is no limit to the number of bytes that can be transferred in one data transfer. It can be transmitted from any number of data between associated with the I ² C-bus devices via the I ² C-bus interfaces. The first byte, which is to be transmitted first via the I ² C bus, contains a 7-bit wide sequencer address which specifies the receiver, ie the sequencer. The least significant bit of the first byte is a direction bit, which indicates the direction of the data. That is, a direction bit with a value of logical zero shows that the guide device writes the data into the following device, whereas a direction bit with a value of logical one shows that the guide device reads the data from the following device.

Reference is now made to FIGS. 6a and 6b, in which an example of a data transfer operation via the I ² C bus is shown. In this case, after the first byte, which contains an address specifying a destination slave device, is transmitted, another data byte is transmitted to the slave device. Fig. 6a shows the waveform of a signal on the SCL line, and Fig. 6b shows the waveform of a signal on the SDA line.

A guide device takes control of the data transmission via the I ² C bus. While the guide device is delivering clock pulses to its follower device, it generates an initial condition and an end condition as shown in Figures 6a and 6b. Since the I ² C bus is also a multi-tasking or multitask system, there is the possibility that several guiding devices begin to transmit data to the subsequent devices via the I ² C bus. In this case, a decision is made to avoid that the I ² C bus system gets into an unordered state. The decision must be made for both the SDA line and the SCL line. While a detailed description of how to decide the above case is not given below, it is noted that because the decision making process is complicated, a hardware device developed for the I ² C bus is used for decision making. If a central processing unit (CPU) for controlling the I ² C bus system has a high performance, the CPU can perform the decision process by controlling its input / output port.

Referring now to Fig. 7, there is shown a block diagram showing the structure of a device including a known I ² C bus interface circuit connected to the I ² C bus. Assume that the processing power of the CPU of the device shown in Fig. 7 is high and that the CPU can implement the decision process by controlling its input / output port. In Fig. 7, reference numeral 1 denotes a conventional serial input / output circuit provided with a clock terminal CLK, an input terminal IN and an output terminal OUT, 2 denotes the CPU for controlling the whole arrangement, and 3 denotes a data bus , which connects the aforementioned components together.

Furthermore, the reference numeral 4 denotes an input buffer with an input which is connected to an SCL connection connected to the SCL line of the I ² C bus, 5 denotes an output buffer with an output which is connected to the SCL connection , and be denotes 6 a selector for selecting one of two inputs or the same input signals in order to supply the selected input signal to an input of the output buffer 5 . Reference numeral 7 be an output latch (output latch) for storing a value of an output signal to be supplied through the SCL connector, 8 denotes a switch for connecting the clock connector CLK of the serial input / output circuit 1 with either one of the two Inputs of the selector 6 or the output of the input buffer 4 , 9 designate an input buffer with an input which is connected to an SDA connection connected to the SDA line of the I ² C bus, 10 designates an output buffer with an output which is connected to is connected to the SDA connector, 11 denotes a selector for selecting one of two inputs to input the selected input signal to the output buffer 10 , and 12 denotes an output latch for storing a value of one to be fed through the SDA connector Output signal.

Referring now to Fig. 8, there is shown a block diagram showing the internal structure of the serial input / output circuit. In this figure, reference numeral 20 denotes a clock generating circuit for generating clock pulses, 21 denotes a switch for selecting clock pulses supplied by the clock generating circuit 20 in an internal clock operating mode and for selecting clock pulses from the CLK connection in an external clock operating mode, 22 denotes a transmission control circuit for providing transmission clock pulses, a transmission end interrupt request signal, a transmission data write signal and so on to control data transmission operations, 23 denotes an output buffer for supplying transmission clock pulses from the transmission control circuit 22 to the clock terminal CLK in the internal clock Mode, and denotes 24 a reception control circuit for providing reception clock pulses, a reception end interrupt request signal, a reception data write signal, and so on, for data reception operations to control. Reference numeral 25 be a receive shift register for converting received data, which are supplied to it via the input terminal IN in serial form, in parallel data, 26 denotes a receive buffer register for reading the contents of the receive shift register 25 in response to the received data write signal the reception control circuit 24 , 27 denotes a transmission buffer register for storing data to be transmitted, 28 denotes a transmission shift register for converting data to be transmitted in parallel form into serial data, and 29 denotes a control register in which a certain value for defining the mode of operation the serial input / output circuit 1 is written.

Will hereinafter be made to FIG. 9a to 9d reference in which are timing charts illustrating the operation of the in Fig. 8 Darge serial input / set output circuit 1 zei gene. Fig. 9a shows the waveform of an output signal of the clock generating circuit 20, Fig. 9b shows the waveform of a by the transmission control circuit 22 Übertragungstaktsi provided gnals, Fig. 9c shows the waveform of provided through the output terminal OUT Übertragungsda th, and Fig. 9d shows the waveform of the provided by the transmission control circuit 22, transmission data write signal.

The transmission operation of the serial bus interface circuit will now be described with reference to Figs. 9a to 9d. The CPU 2 selects an operating mode of the serial input / output circuit 1 from a variety of operating modes, such as the internal clock mode and the external clock mode, for example, by writing a specific value into the control register 29 via the data bus 3 . Assume that the CPU 2 selects the internal clock mode. When predetermined data for selecting the internal clock mode is written in the control register 29 , the switch 21 connects to the clock generation circuit 20 and the output buffer 23 is turned on. As a result, clock pulses according to FIG. 9 a, which are generated by the clock generation circuit 20 , are supplied to the transmission control circuit 22 . The CPU 2 writes data to be transferred via the data bus 3 to the transfer buffer register 27 and then instructs the serial input / output circuit 1 to start the data transfer by writing a predetermined value in the control register 29 .

After the predetermined value for ordering the serial input / output circuit to start a transfer operation is written in the control register 29 , the transfer control circuit 22 sets the transfer data write signal as shown in Fig. 9d and transfer clock pulses as in Fig. 9b shown serially ready for the transfer shift register 28 . In response to the transfer data write signal, the transfer shift register 28 reads data to be transferred, stored in the transfer buffer register 27 , and transfers the data bit by bit in synchronism with each transfer clock pulse, as shown in Fig. 9c. The state of the output terminal OUT was kept in either the high level or the low level (in the figure, it is kept in the high level) before the first bit D0 of the data is transmitted. That is, the initial value of the output or output signal of the output terminal OUT of the serial input / output circuit 1 is either high or low. When the transfer of all bits, in the case shown in the figure, the transfer of the nine bits of the data temporarily stored in the transfer shift register 28 , is complete, the transfer control circuit 22 generates the end-of-transfer interrupt request. The transfer clock pulses are also output buffers 23 issued at the clock terminal CLK ben.

When predetermined data for selecting the external clock mode is written in the control register 29 , the switch 21 connects to the clock terminal CLK, and the output buffer 23 is turned off or is kept in a turned off state. Accordingly, the clock terminal CLK from outside the serial input / output circuit 1 supplied clock pulses to the transmission control circuit 22 output. In this case, no transmission clock pulses generated by the transmission control circuit 22 are output to the outside of the serial input / output circuit 1 through the clock terminal CLK. The other operation in the internal clock mode is similar to the operation mentioned above.

The reception process of the serial input / output circuit 1 will now be described. It is assumed that the CPU 2 selects the internal clock mode by writing predetermined data into the control register 29 . Thereafter, the CPU 2 instructs the serial input / output circuit 1 by writing another predetermined value into the control register 29 to start a reception operation. In response to the instruction to start a Emp capturing operation, the transmission control circuit 22 transfer clock pulses provided on the basis of generated by the clock generation circuit 20 clock pulses. When the reception control circuit 24 receives the respective transfer clock pulses of Übertra supply control circuit which generates and supplies a receive clock pulse to the receive shift register 25th The receive shift register 25 receives the input terminal IN supplied bit by bit in synchronism with each data receiving clock pulse from the control circuit Emp fang 25th After the receive shift register 25 has read all the bits, ie the nine data bits, the receive control circuit 24 outputs the receive data write signal to the receive buffer register 26 . The data received by the receive shift register 25 and stored therein are transmitted to the receive buffer register 26 when the receive data write signal is introduced into the receive buffer register 26 . On the other hand, when the reading of the nine data bits has ended, the reception control circuit 24 generates a reception end interrupt request.

When predetermined data for selecting the external clock mode is written in the control register 29 , the output buffer 23 is turned off or kept in a turned off state, so that therefore no transfer clock pulses generated by the transfer control circuit 22 are output by the clock terminal CLK. The clock terminal CLK from outside the serial input / output circuit 1 clock pulses are fed into the transmission control circuit 22 . The further operational sequence of the serial input / output circuit 1 in the external clock mode is similar to that of the serial input / output circuit 1 in the internal clock mode.

The operation of the device connected to the I ² C bus according to FIG. 7 is described below. After an initial condition has been generated in the I ² C bus system, an address specifying a sequencer is transmitted on the I ² C bus and then data is transmitted on the I ² C bus. In the following, reference is made to FIGS. 10a and 10b, in which timing diagrams are shown for the case in which the device shown in FIG. 7 operates as a guide device. Fig. 10a shows the waveform of the clock pulses on the SCL line of the I ² C bus, and Fig. 10b shows the waveform of a signal on the SDA line of the I ² C bus.

If the SDA signal transitions from the high level to the low level while the SCL line is held high, the transition triggers an initial condition. From the generation of the initial condition up to the point in time at which the device ends the output of an address specifying its follow-up device on the SDA line, the CPU 2 controls the SCL connection and the SDA connection of the I ² C bus interfaces Circuits as if they were your port input / output circuit. This is because such control by the CPU 2 is required to process a complicated decision-making process for authorizing a facility of the system as a guide of the system. If the device has survived the decision process or the decision process for the device has been carried out and since the transmission of the address indicating a subsequent device has ended, the CPU 2 sets within a period of time during which the SCL connection is kept high-level , for example, in Fig. indicated by a broken line time 10a and 10b, respective predetermined states of the selector 6, the selector 11 and the switch 8 fixed, so that as well the SCL pin and SDA-connection of the terminals of the Switch port input / output circuit to those of serial input / output circuit 1 . That is, the SCL connector and the SDA connector start to serve as the serial input / output circuit 1 connectors. Thereafter, the CPU 2 can transmit data to the slave device by controlling the serial input / output circuit 1 as described above. As a result, the CPU 2 can handle the SCL port and the SDA port as ports of the serial input / output circuit 1 to transmit desired data over the SDA line because only the device which is the one at the time of transmission the address of the following device has survived the decision-making process, is the management device of the system, so that a further decision with regard to the data transmission is therefore not necessary.

When the CPU causes the SCL port and the SDA port to switch from the ports of the port input / output circuit to those of the serial input / output circuit 1 , the initial state of the output port OUT, that is, the on Initial value of the output or output signal of the output terminal OUT of the serial input / output circuit 1 , to be fixed to a fixed value such as a high level (HIGH) or a low level (LOW). Because the follower outputs a low level feedback signal to the SDA line when it identifies the follower address from the leader, the SDA line becomes low or is kept in its low level. As a result, the initial value of the output of the output terminal OUT of the serial input / output circuit 1 may be either a high level or a low level state. This is due to the fact that the SDA line of the I ² C bus (hard) has hard-wired AND connection properties, which is why the setting of the SDA connection of the slave device to its low-level state causes the SDA line to be in its low-level closed condition stood passes.

11a and 11b, reference is hereinafter made to Fig., In which timing diagrams for the case, Darge are that the device shown in Fig. 7 operates as a slave device. Fig. 11a shows the signal waveform of clock pulses of the SCL line of the I ² C bus, and Fig. 11b shows the waveform of a signal on the SDA line of the I ² C bus.

As in the case described above in which the device operates as a guide device, the CPU 2 controls the CPU 2 from the generation of the initial condition until the time the device ends receiving an address indicating the subsequent device or the device on the SDA line the SCL connector and the SDA connector of the I ² C-bus interface circuits as if they were the connectors of the port input / output circuit. After means gen the address of the follower means are received, and then outputs a feedback signal to the master, after that the device is a logic zero into the output latch 12 writes and then outputs a low level on the SDA port of the CPU sets 2 within a period of time, currency rend of the SCL pin in its high level to stand is held, for example, in Fig. 11a and Fig. 11b angege by means of broken lines surrounded time predetermined conditions each of the selector 6, the selector 11 and the switch 8 fixed so that both the SCL connector and the SDA connector switch from the ports of the port input / output circuit to those of the serial input / output circuit 1 . Thereafter, the CPU 2 can transfer data to the master by controlling the serial input / output circuit 1 as mentioned above.

When the SCL port and the SDA port, which have served as ports of the port input / output circuit, start to serve as input / output ports of the serial input / output circuit 1 , the initial state of the output port OUT , that is, the initial value of the output of the output terminal OUT of the serial input / output circuit 1 may be a fixed value such as a high or a low level. Assume that the initial value of the output of the output terminal OUT of the serial input / output circuit 1 is a high level, that is, a logic one. In this case, when the CPU 2 causes both the SCL port and the SDA port to switch from the ports of the port input / output circuit to those of the serial input / output circuit 1 , the SDA port goes from low to high level as shown in Fig. 11b. At this time, because the SCL port is kept in its high state, as shown in Fig. 11a, this transition in the state of the SDA port causes an end condition. Such generation of the end condition, which is substantially suppressed at this time and must occur after the end of the data transition, causes a malfunction in the I ² C bus system.

Japanese Patent Application Laid-Open (KOKAI) No. 5-181796 discloses a technology that in relation to the known serial input / output circuit stands.

Since the known serial input / output circuit which can implement an I ² C bus interface circuit arrangement in cooperation with a port input / output circuit is constructed as mentioned above, there is a problem with the serial Input / output circuit 1 in that an incorrect end condition is generated under a condition at the moment when the interface circuit of the device that served as the port input / output circuit starts as a serial input / Output circuit 1 to serve, so that this causes a malfunction in the I ² C bus is caused. The invention is intended to overcome the aforementioned problems.

The invention is therefore based on the object of a serial input / output circuit arrangement which can implement an I ² C bus circuit arrangement in cooperation with port input / output circuitry which does not generate a random end condition when the I ² C -Bus circuitry that has served as a port input / output circuitry begins to serve as a serial input / output circuitry, as well as I ² C bus interface circuitry that is associated with such a serial input / output circuitry. Circuit arrangement is provided to create.

This task is solved by a serial input be / output (I / O) circuit which is an interface circuit Implement arrangement as a serial bus can, characterized in that the as serial Bus-acting interface circuitry elec tric with a bidirectional serial bus that from a clock line (SCL) and a data line (SDA), the voltages of which are pull up resistors are connected, which is connected Interface circuit acting as a serial bus arrangement of outputs with open drain connection for sun probably the clock line as well as the data line points, and the serial input / output circuit ei  NEN clock connection, the electrical with the clock line of the bidirectional serial bus for receiving and Providing a clock signal is connectable, a Input connector that is electrically connected to the data line of the bidirectional serial bus for receiving Data on the data line is connectable, and one Output connector that is electrically connected to the data line to provide transmission data on the Da tenleitung is connectable, the input The output / output circuit further comprises: a data on stop receiving these supplied data, which is an initial value of an output signal that is provided via the output connection set the value of the date received before the serial input / output circuit is activated; an initial value determining means for receiving of the data supplied at the data connection to this to the output port while the serial Input / output circuit is kept disabled, to hold the output of the output port in egg state determined by the initial value if the serial input / output circuit from its deactivated state to its activated state changes, and to receive her afterwards serially supplied data and serially feeding the Data on the data line via the output connection, while the serial input / output circuit in ih rem activated state is held; a clock device for generating and providing a clock signal in an internal clock mode and for receiving against a clock signal supplied to the clock connection,  to the clock signal in an external clock mode respectively; a transmission device that on the Clock signal of the clock device responds to the front temporary storage of on the data line transmitting data and for serial provision the data for the initial value determining means; a receiving device which is based on the clock signal of the Clock device responds to the temporary Spei save data received via the input connection ten; and a control register in which data on the ak activate or deactivate serial input / off gabe circuit can be written.

According to a preferred embodiment of the Er Invention, the clock device includes a Taktzeu supply circuit for generating a clock signal in the Internal clock mode and a switch that with the clock generating circuit and the clock terminal ver is bound to select the clock signal from the clock generation circuit in the internal clock mode or to select the clock signal on the clock connection in external clock mode as well as for provisioning the selected clock for the transmission device device, wherein the transmission device a transmission control circuit for generating a transmission clock signal in response to the clock signal from the Switch, a transfer buffer register to pass outgoing storage of this supplied data, and a transfer shift register for reading the da from the transmission buffer register and bitwise Providing the data for the initial value loading mood device synchronous with the transmission  clock signal of the transmission control circuit, wherein the receiving device receives a receiving tax circuit for generating a receive clock signal in Response to the transfer clock signal of the transfer control circuit, a receive shift register for Receive the bit by bit synchronously with data supplied to the receive clock signal and before temporary storage of the data, and a reception buffer register for reading the in the receive shift register stored data when all bits of data are stored in the receive shift register points.

Can be preferred if the serial input / off gabe circuit in its deactivated state binary data on the data line of the seri ellen bus with the rising or falling Edge of each pulse of a clock signal on the clock line of the serial bus in the data connection of the serial input / output circuit latched be saved to the initial value of the output of the Output connector to the value of the cached stored data.

Alternatively, the aforementioned task is solved by a serial bus interface circuit arrangement voltage that is electrical with a bidirectional seri ellen bus connected from a clock line and a data line, each through Lay-up resistors are placed high and with open ones Drain outputs for both the clock line as well the data lines are provided to make a cut  set up with the bidirectional serial bus the, characterized in that the circuit arrangement voltage includes: a serial input / output circuit, which has a clock connection that is electrically connected to the Clock line of the bidirectional serial bus ver is binding for receiving and providing one Clock signal, an input terminal that is electrical with the data line of the bidirectional serial Busses can be connected to receive data on the Data line, an output connector that is electrical is connectable to the data line. To output Transmission data on the data line, a data connection for receiving binary input from this Data to an initial value one over the output connection to the value of the received binary data leading output set before serial Input / output circuit is activated, an on initial value setting device for receiving the binary Ren data over the data connection to the data to the Output port while the serial Input / output circuit in the deactivated state is held, and to hold the exit of the off connection in one by the initial value placed state when the serial input / output circuit from their deactivated state to the ak activated state changes, and subsequent reception against the serial data and serial len Output of the data on the data line via the Output port while serial input / off gabe circuit kept in its activated state is a clock device for generation and ready  set a clock signal in an internal clock mode as well as receiving one of the tactan finally supplied clock signal and providing the Clock signal in an external clock mode, one Transmission device based on the clock signal of the Clock device responds to the temporary Spei of data to be transmitted on the data line and provide the data for the initial value values mood device, a receiving device, the responsive to the clock signal of the clock device for temporary storage of via the input received data, as well as a control register, in which data to activate or deactivate the serial input / output circuit who wrote the; and a port input / output circuit that then when the serial input / output circuit de is activated, data on the data line and a Clock signal received on the clock line or data on the data line and a clock signal on the clock outputs line, has.

According to a preferred embodiment of the Er Invention, the clock device includes a Taktzeu supply circuit for generating a clock signal in the Internal clock mode and a switch that with the clock generating circuit and the clock terminal ver is bound to select the clock signal from the clock generation circuit in the internal clock mode or to select the clock signal from the clock connection in external clock mode as well as for provisioning the selected clock for the transmission device device, wherein the transmission device a transmission  control circuit for generating a transmission clock signal in response to the clock signal from the Switch, a transfer buffer register to pass outgoing storage of this supplied data, and a transfer shift register for reading the da from the transmission buffer register and bitwise Providing the data for the initial value determination mungseinrichtung in synchronism with the transmission clock signal the transmission control circuit, wherein the receiving device has a receiving control circuit to generate a receive clock signal in response to the transfer clock of the transfer tax circuit, a receive shift register for receiving which is bit by bit in sync with the input port Receive clock signal supplied data and temporary storing the data, and a receive buffer gister for reading those in the receive shift register stored data when all bits of data in the Receive shift registers are stored.

The port input / output circuit preferably comprises a latch circuit for latching of data on the data line of the serial bus with the rising or falling edge of each Pulse of a clock signal on the clock line of the serial bus, the initial value determination device is kept in the activated state and the latch circuit the latch th, binary data to the data connection of the serial Input / output circuit outputs to the initial value of the output of the output connection to the value of binary data. Alternatively, if the serial input / output circuit in their  deactivated state is maintained by the input be / output circuit on the data line de data also the data connection of the serial inputs be / output circuit fed to the initial value of the output of the output connection to the value of Data.

The invention is illustrated below with reference to Example with reference to the accompanying Drawings described in more detail. Show it:

Fig. 1 is a block diagram of a serial be entranc / output circuit according to an embodiment;

Fig. 2 is a block diagram showing the construction of an example of an I ² C bus interface circuit provided with the serial input / output circuit shown in Fig. 1;

Fig. 3a is a timing diagram showing the waveform of clock pulses, the SCL-An circuit of the I ² C bus shown in Figure 2 who supplied the;

Fig. 3b is a timing diagram showing the signal waveform of a signal that is supplied to an SDA connector of the I ² C bus interface circuit;

FIG. 3c is a timing diagram showing the waveform of a signal corresponding to a set terminal S is supplied to an initial value setting of the ge in Fig 1 showed serial input / output circuit.

Fig. 3d is a timing chart showing the signal waveform of a signal which is supplied to a data terminal d of the initial value setting circuit;

Fig. 3e is a timing chart showing the signal waveform of a signal which is provided via an output terminal out of the initial value setting circuit;

Fig. 4 is a block diagram of another example of the I ² C bus interface circuit provided with the serial input / output circuit shown in Fig. 1;

Fig. 5a is a timing diagram showing the signal waveform of clock pulses that are supplied to an SCL connection to the I ² C bus interface circuit shown in Fig. 4;

Fig. 5b is a timing chart showing the waveform of a signal supplied to an SDA connector of the I ² C bus interface circuit;

Fig. 5c is a timing diagram showing the waveform of a signal corresponding to a setting Ellan terminal S of an initial value setting of the se-material input / output circuit in the I ² C bus interface circuit is supplied;

Fig. 5d is a timing chart showing the waveform of a signal d to a data terminal of the initial value setting circuit is supplied;

Fig. 5e is a timing diagram showing the signal waveform of a signal which is supplied via an output terminal out of the initial value setting circuit;

Fig. 6a is a timing diagram showing the signal history of a signal on an SCL line of the I ² C bus;

Fig. 6b is a timing diagram showing the signal history of a signal on an SDA line of the I ² C bus;

Fig. 7 is a block diagram of a device comprising a known I ² C bus interface circuit;

Fig. 8 is a block diagram of a serial input / output circuit included in the I ² C bus interface circuit shown in Fig. 7;

Fig. 9a is a timing chart showing the waveform of an output signal of a clock generating circuit of the prior art serial input / output circuit shown in Fig. 8;

Fig. 9b is a timing chart showing the waveform of a transfer clock signal of a transfer control circuit of the known serial input / output circuit;

Fig. 9c is a timing chart showing the waveform of transmission data, which are provided via an output terminal OUT of the known serial input / output circuit;

Fig. 9d is a timing diagram showing a transmission signal extending the data write signal supplied by the transmission control circuit;

FIG. 10a is a timing diagram gnalverlauf the Si of clock pulses on the SCL line of the I ² C-bus, when the known bus interface circuit means containing as Führungsein device operates;

Fig. 10b is a timing chart showing the signal waveform of a signal on the SDA line of the I ² C bus when the device containing the known bus interface circuit works as a guide device;

Fig. 11a is a timing chart showing the waveform of clock pulses on the SCL line of the I ² C bus when the device containing the known bus interface circuit works as a sequence device; and

Fig. 11b is a timing chart showing the waveform of the SDA signal s on the I ² C bus when the device containing the known bus interface circuit works as a slave.

Reference is now made to FIG. 1, which illustrates a block diagram showing the internal structure of a serial input / output circuit according to an embodiment. In addition to an input terminal IN, an output terminal OUT and a clock terminal CLK, the serial input / output circuit is provided with a data terminal D, to which a binary data is supplied, by the initial or initial value of the output or output signal of the output terminal OUT of the serial input / output circuit to set the binary date.

In the figure, reference numeral 20 denotes a clock generation circuit for generating sen from Taktimpul, 21 denotes a switch for selecting generated by the clock generation circuit 20 clock pulses in an inter-stroke mode and off choose from this fed guide via the clock terminal CLK th pulses of an external clock Mode, 22 denotes a transmission control circuit responsive to the clock pulses selected by the switch 21 for providing transmission clock pulses, a transmission end interrupt request signal, a transmission data write signal, and so on to control data transmission operations, and 23 denotes one Output buffer for outputting the transfer clock pulses from the transfer control circuit 22 to the clock terminal CLK in the internal clock mode.

Further, reference numeral 24 designates a reception control circuit that is responsive to the transmission clock pulses provided by the transmission control circuit 22 for providing reception clock pulses, a reception end interrupt request signal, a reception data write signal, and so on to control data reception operations Reference numeral 25 is a reception shift register for converting received data which are supplied to it through the input terminal IN in serial form into parallel data. The receive shift register 25 receives data supplied to it through the input terminal IN, bit by bit synchronously with each receive clock pulse from the receive control circuit 24 by shifting the received data, and stores all the received data. In addition, 26 denotes a transfer buffer register for reading received , catch shift register in the Emp 25 of stored data in Ant word to the received write data signal from the receiving control circuit 24 each time the receive shift register 25 ends the data reception. The receive buffer register 26 is connected to the data bus 3 , so that a CPU (not shown in FIG. 1, but in FIG. 2) connected to the data bus 3 can read the contents of the receive buffer register 26 .

Reference numeral 27 denotes a connected to the data bus 3 transmission buffer register for SpeI manuals of data to be transmitted, so that the CPU via the data bus 3, data most to the Übertragungspufferregi transmitted 27 and then the data in the Übertra can write supply buffer register 27, and 28 be distinguished a transfer shift register for converting the data to be transferred in parallel to serial data. The transfer shift register 28 reads the data to be transferred, which is stored in the transfer buffer register 27 , in response to the transfer data write signal from the transfer control circuit 22 , and then supplies the data bit by bit with each of transfer clock pulses from the transfer control circuit 22 to one Input terminal in an initial value setting circuit 30 to be described. Reference numeral 29 denotes a control register in which a predetermined value such as a value for defining the mode of the serial input / output circuit or a value for triggering the transmission or reception of data is written. The switch 21 , the transmission control circuit 22 , the output buffer 23 , the reception control circuit 24 and so on operate in accordance with the setting stored in the control register 29 . The control register 29 is connected to the data bus 3 so that the CPU can write data or a value in the control register 29 .

These components of the serial input / output circuit according to this embodiment are similar to those of the known serial input / output circuit, which are denoted by the same reference numerals in FIG. 8.

The initial value setting circuit 30 can set the initial value of the output signal output from the output terminal OUT of the serial input / output circuit. The initial value setting circuit 30 is a key component of the serial input / output circuit of the present invention. The initial value setting circuit 30 has an input terminal in which, as mentioned above, is connected to the transfer shift register 28 , an output terminal out which is connected to the output terminal OUT of the serial input / output circuit, a clock terminal clk, the transfer clock pulses can be supplied from the transmission control circuit 22 , a Setzan circuit s, which is connected to the control register 29 , and a data terminal d, which is connected to the data terminal D of the serial input / output circuit ver connected. When the set terminal s is activated, the initial value setting circuit 30 can provide the binary data applied to the data terminal d as the initial value of the output signal of the serial input / output circuit via the output terminal out. On the other hand, when the set port s is disabled, the initial value setting circuit 30 can provide the output of the transfer shift register 28 to the input port in an input via the output port out in response to each transfer clock pulse supplied to the clock port clk. The set connection s can be set by the control register 29 . If the serial input / output circuit is not used, ie if it is deactivated or switched off, the setting connection s is activated. When the serial input / output circuit is used, ie when it is activated or in operation, the setting connection s is deactivated.

Reference 2 is hereinafter made to Fig., In which a block diagram is shown, which structure the structural means is provided with a the seri elle input / output circuit according to this exporting approximately example as shown in Fig. 1 and a port input / Output circuit containing I ² C-bus interface circuit is provided. As the above-mentioned known device provided with the conventional union serial input / output circuit, this device assumes that an existing CPU in the device has a high processing performance and therefore the decision or decision process by controlling the input / Can execute from output ports.

As shown in FIG. 2, the serial input / output circuit 13 according to this embodiment with the structure shown in FIG. 1 is connected to the CPU 2 via the data bus 3 .

In Fig. 2, reference numeral 4 denotes an input buffer with an input terminal which is connected to an SCL line connected to the SCL line of the I ² C bus. When the CPU 2 reads data, a clock signal is output via the input buffer 3 onto the data bus. 3 Reference numeral 5 denotes an output buffer with an output terminal connected to the SCL terminal, and 6 denotes a selector for selecting one of two inputs, that is, outputs of an output latch 7 and a switch 8 , which will be described later, for switching the to supply the selected output to the output buffer 5 . The output buffer (output latch) is designed such that it stores an output value of an output signal to be supplied via the SCL connection. The output value of a signal to be supplied via the SCL connection is written into the output buffer 7 by the CPU 2 via the data bus 3 . The switch 8 is designed so that it connects the clock terminal CLK of the serial len input / output circuit 13 with either one of the two input terminals of the selector 6 or the output terminal of the input buffer 4 . When the serial input / output circuit 13 is held in the internal clock mode, the switch 8 connects the clock terminal CLK of the serial input / output circuit 13 to one of the two input terminals of the selector 6 , whereas if the Serial input / output circuit 13 is held or operated in the external clock mode, the switch 8 connects the clock terminal CLK of the serial input / output circuit 13 to the output terminal of the input buffer 4 .

Reference numeral 9 denotes an input buffer with an input connection, which is connected to an SDA connection connected to the SDA line of the I ² C bus. When the CPU 2 reads data supplied to the SDA terminal, the data is output on the data bus 3 and also supplied to the input terminal IN of the serial input / output circuit 13 . Fer ner, reference numeral 10 designates an output buffer with an output port connected to the SDA port, 11 designates a selector for selecting one of two inputs, ie, an output of an output buffer 12 , which will be described below, and the output the serial input / output circuit at the output terminal OUT to supply the selected input to the output buffer 10 . The output buffer 12 is designed such that it accepts and stores a value of an output signal which is to be supplied via the SDA connection. The CPU can write the value to the output buffer 12 via the data bus 3 .

These components with the exception of the serial input / output circuit 13 are similar to those of the known arrangement indicated by the same reference numerals in FIG. 7.

Furthermore, reference numeral 14 designates a latch circuit which latches a date (or a binary date) and the date to the SDA connection with the rising edge of each clock pulse supplied to the SCL connection and thus to a clock connection clk of the same to the data terminal D of the serial input / output circuit 13 can output. The port input / output circuit is provided with the input buffers 4 and 9 , the output buffers 5 and 10 , the selectors 6 and 11 , the switch 8 , the output latches 7 and 12 and the latch circuit 14 .

In the following, reference is made to FIGS . 3a to 3e, in which timing diagrams for explaining the functioning of the device provided with the I ² C bus interface circuit containing the serial input / output circuit are shown according to the exemplary embodiment. Fig. 3a shows the signal curve of clock pulses which are supplied to the SCL connection of the interface circuit of the device, Fig. 3b shows the signal curve of a signal which is supplied to the SDA connection of the device interface circuit Fig. 3c shows the signal curve of a signal applied to the set terminal S of the initial value Einstellschal shown in Fig. 1 tung 30 is fed, Fig. 3d shows the Signalver running a signal d to the data terminal as shown in FIG. 1, initial value setting circuit 30 to be performed, and Figure . 3e shows the waveform ei nes signal out through the output terminal shown in FIG. 1, initial value setting circuit 30 will be riding provided.

Tung Since connected to the I ² C-bus I ² C bus interface of lenschaltung open drain outputs for the SDA Lei and having the SCL line and both the SDA line and the SCL line by means of respective pull- up resistors are pulled up to a voltage, wired AND connections are made between the I ² C bus interface circuit and the SDA line and the SCL line. While the I ² C bus is not being used, both SCL and SDA are kept in their high-level states. In this state, when the SDA line transitions from its high level to the low level, an initial condition occurs. Furthermore, when the SDA line goes from its low level state to the high level state while the SCL line is kept in its high level state, an end condition occurs. If an initial condition occurs on the I ² C bus, a sequencer address indicating a sequencer is first serially transmitted and then data is serially transmitted to the sequencer via the I ² C bus.

The operation of the device operating as a guide device of the I ² C bus system is described below. If the device causes the SDA line to transition from the high level to the low level while the SCL line is kept in its high level state, it causes an initial state. The CPU 2 controls from the beginning of the initial condition until the device outputs an address indicating its follower on the SDA line, the SCL port and the SDA port of the device interface circuit as if it were the ports the port input / output circuit. Such a control by the CPU 2 is required to make a complicated decision-making process to authorize a device in the I ² C-bus system as a guiding means of the I ² C-bus system to process. The decision is made as with the conventional I ² C bus system.

After the device has generated an initial condition, the CPU 2 of the device begins to output a slave device address on the SDA line of the I ² C bus via the SDA connector of the I ² C bus interface circuit. When each clock pulse applied to the SCL port of FIG. 3a triggers a transition from the low level to the high level, the latch circuit 14 latches each of the data bits, ie, the slave address supplied to the SDA port of FIG. 3b . The latch circuit 14 supplies each latched bit to the data terminal D of the serial input / output circuit 13 and thus to the data terminal d of the initial value setting circuit 30 of the serial input / output circuit. Fig. 3d shows all bits of the data that are supplied to the data terminal d of the initial value setting circuit 30 . While the device is feeding the slave device address over the I ² C bus, the serial input / output circuit 13 is set in its deactivated state in accordance with the control register 29 so that the CPU 2 has the SCL port and the Controls SDA connector as if it were the connector of the port input / output circuit. At this time, the initial value setting circuit 30 is kept in its activated state in accordance with the low level signal applied to its setting terminal s as shown in FIG. 3c.

After the initial value setting circuit 30 is activated, it begins to provide each data bit supplied at its data connection d via its output connection out. As mentioned above, each bit of the date, ie, each bit of the sequencer address, that is applied to the SDA connector and then latched by latch circuit 14 with the rising edge of each clock pulse applied to the SCL connector. via the data connection D of the serial input / output circuit 13 to the data connection d output. Accordingly, the output of the latch circuit 14 is provided at the output terminal out of the initial value setting circuit 30 as shown in Fig. 3e, so that therefore all bits of the data are output serially through the output terminal OUT of the serial input / output circuit 13 . After the device that has passed the decision process and the slave device output a low-level feedback signal on the SDA line in response to the device address supplied by the device, the SDA line becomes low-level. Thus, the state (ie, low level) of the SDA port on the rising edge of the ninth clock pulse supplied to the SCL port since the beginning of the address transfer operation can be used as the initial value of the output of the output port OUT of the serial input / output circuit 13 are, as can be seen from the level of the SDA signal delimited by an ellipse in FIGS . 3a and 3b.

When the device has survived the decision process, the transfer of the address indicating the follower is completed, and the follower then causes the SDA line to transition to the low level, the device's CPU 2 moves the selector 6 , the voter 11 and the Switch 8 within a period of time during which the SCL connection is held high, for example at the time indicated in Fig. 3a and 3b by means of broken lines, in each predetermined conditions, so that both the SCL connection and the SDA - Switch the connection from the ports of the port input / output circuit to those of the serial input / output circuit. Then, the CPU 2 can transmit data to the slave device by controlling the serial input / output circuit 13 . While the device is supplying the data to the slave device via the I ² C bus, the serial input / output circuit 13 is kept activated in accordance with the control register 29 so that the CPU 2 connects the SCL connector and the SDA Controls the connection as if these were the connections of the serial input / output circuit. On the other hand, the initial value setting circuit 30 has assumed its deactivated state and is kept in this state in accordance with the signal applied to its set input s according to FIG. 3c.

After the initial value setting circuit 30 assumes its deactivated state, it starts to output data supplied at its input terminal via its output terminal out. To be transmitted da ta, the WUR stored by the transmitting buffer register 27 in the transmit shift register 28 to be in synchronism with each of by the delegation of control circuit 22 provided Übertra supply clock pulses serially to the input terminal in is applied. Accordingly, the output of the transfer shift register 28 is supplied through the output terminal out of the initial value setting circuit 30 to the output terminal OUT of the serial input / output circuit 13 as shown in Fig. 3e. Never in the known device, the CPU 2 can handle the SCL connector and the SDA connector as if they were only connectors of the serial input / output circuit to transmit desired data via the SDA line, because only that Device that has survived the decision making process carried out at the time of transfer of the slave address, is a guide device of the system and therefore no further decision regarding the data transfer is necessary.

At the time shown in broken lines in Figs. 3a and 3b, the CPU 2 causes both the SCL port and the SDA port from the ports of the port input / output circuit to those of the serial input / output circuit switch. Before this time, the initial value setting circuit 30 has set the initial value of the output of the output terminal OUT of the serial input / output circuit 13 to the level or value of one with the rising edge of the ninth since the beginning of the address transfer operation to the SCL terminal put clock pulse to the SDA connector supplied binary date set. Accordingly, when the serial input / output circuit changes from its deactivated state to its activated state and the I ² C bus interface circuit starts to serve as the serial input / output circuit, the initial value setting circuit 30 - determined by the initial value - the output of its output connection out and thus the output of the output connection OUT low, so that no change in the state of the SDA connection occurs, as shown in Fig. 3b.

The operation of the device working as a slave will be described below. As in the above-mentioned case where the device operates as a guide device, the CPU 2 controls from the generation of an initial state until the device receives an address on the SDA line indicating its slave device SCL connector and the SDA connector of the interface circuit of the device as if they were the connectors of the port input / output circuit. After the device has received the slave device address and then outputs a feedback signal to the guide device, that is, after the device writes a logic zero in the output latch 12 and then outputs a low level feedback signal to the SDA line through the SDA connector , the CPU 2 puts the selector 6 , the selector 11, and the switch 8 into predetermined states within a period of time during which the SCL connector is kept high, so that both the SDA connector and the SCL connector of the Switch the ports of the port input / output circuit to those of the serial input / output circuit. The CPU 2 can receive data from the guide device or supply data to the guide device by controlling the serial input / output circuit 13 .

Before the CPU 2 causes the SCL port and the SDA port to switch from the ports of the port input / output circuit to those of the serial input / output circuit, the initial value setting circuit 30 has the initial value of the output of the Output terminal OUT of the serial input / output circuit 13 is set to the level or value of a binary data which is applied to the SDA terminal with the rising edge of the ninth clock pulse applied to the SCL terminal since the beginning of the address transmission operation. Therefore, no change in the level of the SDA connector occurs when the I ² C bus interface circuit starts to serve as a serial input / output circuit, as in the case where the device as a guide device of the I ² C- Bus system works.

As mentioned above, because the serial input / output circuit according to the first embodiment, the initial value of the output of its output terminal occurs in accordance with the level or value of a binary data applied to the SDA terminal, that is, the state of the SDA -Connection, may not specify a random or unwanted end condition when a 1 ² C bus interface circuit including the serial input / output circuit starts to serve as the serial input / output circuit. Accordingly, the serial input / output circuit of this embodiment, in cooperation with a port input / output circuit, can be an I ² C bus interface circuit without adding dedicated hardware and, moreover, an I ² C bus device such as a microcontroller or an LCD driver with a small chip area, low manufacturing costs and high general, versatile usability.

4, reference will hereinafter be made to FIG., In which a block diagram is shown, which structure the structural means, coupled to an I ² C bus interface circuit according to another exporting approximately, for example including those in Fig. Serial input / output shown 1 Circuit 13 is provided. The interface circuit according to this embodiment is designed to take the initial value of the output of the output terminal OUT of the serial input / output circuit 13 to be used when the interface circuit starts to serve as a serial input / output circuit Outputting an output value to be supplied to the SDA connection, which was supplied by the CPU 2 and buffered in the output buffer memory 12 , defines the data connection D of the serial input / output circuit 13 . That is, according to this embodiment, instead of latching the level s or the value of a binary data applied to the rising edge of each clock pulse to the SDA terminal using the latch circuit 14 shown in Fig. 2, an output value by the output Buffer 12 has been temporarily stored and is to be output to the SDA connection, is applied to the data connection D of the serial input / output circuit 13 in order to set the initial value of the output of the output connection OUT to the output value. The other components of the interface circuit shown in Fig. 4 are the same as those of the interface circuit according to the first embodiment and denoted by the same reference numerals shown in Fig. 2, so that the description of these components is therefore omitted below.

As in the above-mentioned first embodiment, the CPU 2 of the device provided with the interface circuit according to this embodiment has high processing power and can therefore perform the decision process by controlling the input / output port.

Will hereinafter be made to Fig. 5a to 5e reference in which are timing charts for explaining the operation of the device, which is provided game circuit with the interface according to the second Ausführungsbei shown Fig. 5a shows the waveform of clock pulses corresponding to the SCL-An Conclusion of the I ² C-bus interface circuit shown in Fig. 4, Fig. 5b shows the signal waveform of a signal that is supplied to an SDA connector of the interface circuit of the device, Fig. 5c shows the waveform of a signal that the set terminal s of the initial value adjusting circuit 30 of the serial input / output circuit 13 of FIG. 1 is supplied, Fig. 5d shows the waveform of a signal applied to the data terminal D of the initial value setting circuit 30, the serial input / output circuit 13 is supplied, and Fig. 5e shows the waveform of a signal, the initial value setting sc via the output terminal out attitude 30 of the serial input / output circuit 13 is supplied.

Like the device provided with the interface circuit according to the first embodiment, when an initial condition occurs on the I ² C bus, an address indicating a slave is first transmitted via the I ² C bus and then data to the slave transfer.

The operation of the device operating as a guide device of the I ² C bus system is described below. When the CPU 2 causes the SDA signal to transition from the high level to the low level while the SCL line is kept in its high level state, the transition causes an initial state. The CPU 2 controls from the beginning of the initial condition until the time when the device ceases to output an address indicating its follower device on the SDA line, the SCL port and the SDA port of the device interface circuit as if these were the terminals of the port input / output circuit, according to the device according to the first embodiment, for example. Such a control by the CPU 2 required a complicated decision process to authorize a device in the I ² C-bus system as a guide means of the I ² C-bus system to process.

Then, as with the device provided with the interface circuit according to the first embodiment, while the device provided with the interface circuit according to the second embodiment supplies a slave device address via the I ² C bus, the serial input / output circuit 13 in Correspondence with the control register 29 is kept disabled so that the CPU 2 can control the SCL port and the SDA port as if they were the ports of the port input / output circuit. At this time, the initial value setting circuit 30 is kept in its activated state in accordance with the signal applied to its set input s as shown in FIG. 5c. Since an output value supplied to the SDA terminal, which has been output by the CPU 2 on the data bus 3 and buffered in the output buffer 12 , is also supplied to the data terminal d of the initial value setting circuit 30 , the output becomes off gangs latch 12 as the initial value of the output of the output terminal OUT of the serial input / output circuit in the data terminal D ge, which is to be used when the SCL terminal and the SDA terminal are caused to the terminals of the Switch port input / output circuit to that of the serial input / output circuit, that is, when the serial input / output circuit changes from its deactivated state to its activated state. As a result, the high-level output of the output buffer 12 on the rising edge of the ninth clock pulse according to FIG. 5a since the beginning of the address transmission as the initial value of the output of the output terminal OUT into the data terminal D and thus into the data terminal d the initial value Setting circuit 30 taken over, as shown in Fig. 5d. This is due to the fact that the device, which is the guide device of the I ² C bus system, must supply the SDA connection with a high-level signal, so that a corresponding de-device device sends a low-level feedback signal to the SDA line of the I can output ² C buses.

When the device has survived the decision process, the transmission of the address indicating the slave is finished, and the slave then outputs a low level feedback signal to the SDA line, the CPU 2 moves within a period of time during which the SCL connector is kept high level is, for example, at the time in Fig. 5a and 5b indicated by means of broken lines, the selector 6, the selector 11 and the switch 8 in each weils predetermined conditions, so that both the SCL pin and the SDA port of the connec Switch the port input / output circuit to that of the serial input / output circuit. Then, by controlling the serial input / output circuit 13 , the CPU 2 starts to transmit data to the slave device or to receive data from the slave device. While a data transfer operation between the guide device and the slave device is performed on the I ² C bus, the serial input / output circuit 13 is held in its activated state in accordance with the control register 29 so that the CPU 2 can control the SCL port and the SDA port as if they were the ports of the serial input / output circuit. At this time, the initial value setting circuit 30 is kept deactivated in accordance with the signal applied to its set input s as shown in FIG. 5c.

After the initial value setting circuit 30 assumes its deactivated state, it starts to output data supplied in series through its output terminal out at its input terminal in synchronism with each of clock pulses, as shown in Fig. 5e. The data is then passed to the output terminal OUT of the serial input / output circuit 13 . As in the first embodiment, the CPU 2 can handle the SCL connector and the SDA connector as if they were only the connectors of the serial input / output circuit to transfer desired data over the SDA line because only the one that survived the decision making at the time of transferring the follower address is a leader of the system and therefore no further decision regarding data transfer is required.

As explained above, at the time shown in broken lines in Figs. 5a and 5b, the CPU 2 causes both the SCL port and the SDA port to change from the ports of the port input / output circuit to those of the serial input / Switch output circuit. Previously, the initial value of the output of the output terminal OUT of the serial input / output circuit 13 has been set to the high level, which is the setting value that has been set by the CPU 2 during the cycle of the ninth since the address transfer operation to the SCL terminal clock pulse applied to the SDA connection. On the other hand, the follower continues to supply a low level feedback signal while the SCL line is kept high. Accordingly, when the serial input / output circuit 13 changes from its deactivated state to its activated state and the I ² C bus interface circuit starts to serve as the serial input / output circuit, the initial value setting circuit 30 - determined by the initial value - the output of their output connection out and thus the output of the output connection OUT high level, so that therefore no change occurs in the state of the SDA connection, as shown in Fig. 5b.

The operation of the device operating as a device is described below. As in the above-mentioned case where the device operates as a guide device, the CPU 2 controls from the generation of an initial state until the device ceases to receive an address on the SDA line indicating its subsequent device , the SCL connector and the SDA connector of the device interface circuit as if they were the connectors of the port input / output circuit. After the device has received the subsequent device address and then outputs a feedback signal to the guidance device, that is, after the device writes a logic zero in the output latch 12 and then a low level feedback signal to the SDA port via the SDA port outputs, the CPU 2 puts the selector 6 , the selector 11 and the switch 8 into predetermined states within a period of time during which the SCL connector is kept high, so that both the SDA connector and the SCL connector of switch the ports of the port input / output circuit to those of the serial input / output circuit. The CPU 2 can receive data from the guide device or supply data to the guide device by controlling the serial input / output circuit 13 .

Before the CPU 2 causes the SCL port and the SDA port to switch from the ports of the port input / output circuit to those of the serial input / output circuit, the initial value setting circuit 30 has the initial value of the off gangs of the output terminal OUT of the serial input / output circuit 13 is set to a high level, which is the setting value which is applied by the CPU 2 during the cycle of the ninth clock pulse applied to the SCL terminal since the address transmission process began the SDA connection must be created. Therefore, no change occurs in the level of the SDA terminal when the device starts to serve as a serial input / output circuit, as in the case where the device acts as a guide device of the I ² C bus system.

As mentioned above, because the I ² C bus interface circuit according to the second embodiment occurs the initial value of the output of the output terminal of the serial input / output circuit by using the level s or value s ees through the port input / Output circuit can be set to the binary date to be applied to the SDA connection, no random or unwanted end condition. Further, because the interface circuit according to this embodiment does not require the latch circuit 14 shown in FIG. 2, the size of the I ² C-bus interface circuit can be further reduced compared to the I ² C-bus interface circuit according to the first embodiment.

As explained above, in accordance with a preferred embodiment, there is provided a serial input / output circuit which includes an initial value setting circuit for setting an initial value of the output of an output terminal thereof and a data terminal in which a binary date is introduced around the initial value to set the output of the output terminal of the serial input / output circuit to the value of the binary data. Furthermore, the serial input / output circuit is designed to output the data applied to it through the data port through its output port when the serial input / output circuit is kept in its deactivated state. On the other hand, when the serial input / output circuit is kept in its fourth state, it is designed to output transmission data supplied to it via an input terminal on the SDA line through the output terminal. Accordingly, the serial input / output circuit according to the embodiments, in cooperation with a port input / output circuit, can implement an I ² C-bus interface circuit arrangement that does not have a wrong end condition that a malfunction in the I ² C-Bus system causes generated when the I ² C-Bus interface circuitry that has served as the port input / output circuit begins to serve as a serial input / output circuit.

In addition, the I ² C bus interface circuitry includes a latch circuit for latching a binary data on the SDA line of the I ² C bus with the rising edge of each pulse of a clock signal on the SCL line of the I ² C-buses. The serial input / output circuit can set the initial value of its output terminal to the value of the binary data cached by the latch circuit. Therefore, an end condition does not occur accidentally when 03110 00070 552 001000280000000200012000285910299900040 0002019728465 00004 02991nn the I ² C-Bus interface circuit arrangement, which has served as port input / output circuit, begins as a serial input / output circuit to serve. Thus, the serial input / output circuit according to the described exemplary embodiments can implement an I ² C bus interface circuit arrangement in cooperation with a port input / output circuit without adding dedicated hardware and, in addition, an I ² C Bus devices such as a microcontroller or an LCD driver with a small chip area, low manufacturing costs and high general, versatile usability.

In accordance with another exemplary embodiment, if the serial input / output circuit is kept deactivated, a binary data to be output by the port input / output circuit on the SDA line is also in the data connection of the serial input / output circuit directed to set the initial value of the output port to the value of the binary date. Accordingly, the I ² C bus interface circuitry according to this embodiment needs the aforementioned latch circuit for latching a binary data on the SDA line of the I ² C bus with the rising edge of each pulse of a clock signal on the SCL line of the I ² C bus not, so that the size of the I ² C bus interface circuit arrangement can be further reduced in comparison with the I ² C bus interface circuit arrangement of the aforementioned first exemplary embodiment .

As described above, serial input / output circuitry, in cooperation with port input / output circuitry, may implement interface circuitry connected to a serial bus such as an I ² C bus. The serial input / output circuit arrangement has an initial value setting circuit which receives data, by means of which an initial value of the output of an output terminal is determined via a data connection before the serial input / output circuit is activated by which the Data port to receive received data to the output port while the serial input / output circuit is kept in its deactivated state and - when the serial input / output circuit changes from the deactivated state to the activated state - the output of the output terminal in a state determined by the initial value and then receiving the data supplied to it serially and routing it serially via the output connection to a data line of the I ² C bus, while the serial input / output circuit is kept in its activated state becomes.

Claims (9)

1. Serial input / output (I / O) circuit ( 13 ), which can implement an interface circuit arrangement as a serial bus, characterized in that
the interface circuit arrangement acting as a serial bus is electrically connected to a bidirectional serial bus, which consists of a clock line (SCL) and a data line (SDA), the voltages of which are raised by pull-up resistors,
the interface circuit arrangement acting as a serial bus has outputs with an open drain connection for both the clock line and the data line, and
the serial input / output circuit has a clock connection (CLK) which can be electrically connected to the clock line of the bidirectional serial bus for receiving and providing a clock signal,
an input terminal (IN) which is electrically connectable to the data line of the bidirectional serial bus for receiving data on the data line, and
an output connection (OUT), which can be electrically connected to the data line for providing transmission data on the data line,
the input / output circuit further comprising:
a data terminal (D) for receiving this supplied data which sets an initial value of an output signal which is provided through the output terminal to the value of the received data before the serial input / output circuit is activated;
initial value determining means ( 30 ) for receiving the data supplied to the data port to be supplied to the output port while the serial input / output circuit is kept deactivated, for holding the output of the output port in a state determined by the initial value is determined when the serial input / output circuit changes from its deactivated state to its activated state, and thereafter receiving its serially supplied data and serially feeding the data on the data line via the output port during the serial input / output Circuit is kept in its activated state;
clock means ( 20 , 21 ) for generating and providing a clock signal in an internal clock mode and for receiving a clock signal supplied to the clock terminal to supply the clock signal in an external clock mode;
transmission means ( 22 , 27 , 28 ), responsive to the clock signal from the clock means, for temporarily storing data to be transmitted on the data line and for serially providing the data to the initial value determining means;
receiving means ( 24 , 25 , 26 ), responsive to the clock signal from the clock means, for temporarily storing data received via the input terminal; and
a control register ( 29 ) in which data for activating or deactivating the serial input / output circuit are written. 2. Serial input / output circuit according to claim 1, characterized in that the clock device a clock generating circuit ( 20 ) for generating a clock signal in the internal clock mode and a switch ( 21 ) which is electrically connected to the clock generating circuit and the Clock connection is connected to select the clock signal of the clock generating circuit in the internal clock mode and to select the clock signal of the clock terminal in the external clock mode and to supply the selected clock to the transmission device, the transmission device comprising a transmission control circuit ( 22 ) for generating a transfer clock signal in response to the clock signal from the switch, a transfer buffer register ( 27 ) for temporarily storing data supplied thereto, and a transfer shift register ( 28 ) for reading the data from the transfer buffer register and bitwise supplying the data the initial value determination egg nrich device in synchronism with the transmission clock signal from the transmission control circuit, and wherein the receiving device comprises a reception control circuit ( 24 ) for generating a reception clock signal in response to the transmission clock signal from the transmission control circuit, a reception shift register ( 25 ) for bitwise reception of the data supplied to the input terminal in synchronism with the receive clock signal and temporarily storing the data and a receive buffer register ( 26 ) for reading the data stored in the receive shift register when all the data bits are stored in the receive shift register. 3. Serial input / output circuit according to An saying 1 or 2, characterized in that then if the serial input / output circuit in their Disabled state is held on the data Serial bus data line increases with the falling or falling edge of each pulse Clock signal on the clock line of the serial bus into the data port of the serial input / output circuit can be cached to the Initial value of the output of the output connection set the value of the cached data len.   4. Serial input / output circuit according to on saying 1 or 2, characterized in that then when the serial input / output circuit is deactivated fourth is held by the interface scarf arrangement for the serial bus on the data Data to be output in the data connection of the serial input / output circuit can to the initial value of the output connector to set the value of the data. 5. Interface circuitry for a serial bus, which is electrically connected to a bidirectional len serial bus, which consists of a clock line (SCL) and a data line (SDA), the voltages of which are raised by pull-up resistors, and with open drain outputs for both the clock line and the data line is seen to form an interface with the bidirectional serial bus, characterized in that the circuit arrangement comprises:
a serial input / output circuit which has a clock connection which can be electrically connected to the clock line of the bidirectional serial bus for receiving and providing a clock signal,
an input connection which can be electrically connected to the data line of the bidirectional serial bus for receiving data on the data line,
an output connection which can be electrically connected to the data line for outputting transmission data to the data line,
a data port for receiving these supplied data which set an initial value of an output signal which is provided via the output port to the value of the received date before the serial input / output circuit is activated;
initial value setting means ( 30 ) for receiving the data over the data port, for outputting the data to the output port while the serial input / output circuit is kept in the deactivated state, and for holding the output of the output port in one through the beginning value-defined state when the serial input / output circuit changes from its deactivated state to the activated state, and subsequently receiving the data supplied to it serially and serially outputting the data to the data line via the output connection, while the serial input / Output circuit is kept in its activated state;
clock means for generating and providing a clock signal in an internal clock mode and for receiving a clock signal supplied to the clock terminal and providing the clock signal in an external clock mode;
transmission means responsive to the clock signal of the clock means for temporarily storing the data to be transmitted on the data line and providing the data to the initial value determining means; receiving means responsive to the clock signal from the clock means for temporarily storing data received through the input port;
a control register into which data for activating or deactivating the serial input / output circuit is written; and
a port input / output circuit ( 4 to 12 , 14 ) which, when the serial input / output circuit is deactivated, receives data on the data line and a clock signal on the clock line or data on the data line and a clock signal on the Clock line outputs. 6. Interface circuit arrangement for a serial bus according to claim 5,
characterized in that the clock means
a clock generating circuit for generating a clock signal in the internal clock mode and
a switch which is connected to the clock generation circuit and the clock connection, for selecting the clock signal from the clock generation circuit in the internal clock mode or for selecting the clock signal from the clock connection in the external clock mode and for providing the selected one Clocks for the transmission device,
being the transmission device
a transmission control circuit for generating a transmission clock signal in response to the clock signal from the switch,
a transfer buffer register for temporarily storing the data supplied thereto and a transfer shift register for reading the data from the transfer buffer register and providing the data bit by bit for the initial value determination device in synchronism with the transfer clock signal of the transfer control circuit,
being the receiving device
a reception control circuit for generating a reception clock signal in response to the transmission clock signal of the transmission control circuit,
a receive shift register for receiving the data supplied to the input terminal bit by bit synchronously with the receive clock signal and temporarily storing the data and
a receive buffer register for reading the data stored in the receive shift register when all bits of the data are stored in the receive shift register. 7. Interface circuit arrangement for a serial bus according to claim 5 or 6, characterized in that the port input / output circuit has a buffer circuit ( 14 ) for buffering data on the data line of the serial bus with the rising or falling edge of each Has a pulse of a clock signal on the clock line of the serial bus, and in which the initial value determining device is kept in the activated state and the latch circuit outputs the buffered data to the data connection of the serial input / output circuit by the initial value of the output of the output connection set the value of the cached data. 8. Interface circuitry for one serial bus according to claim 5 or 6, characterized records that when the serial input / output be circuit kept in its deactivated state is by the input / output circuit on the Da Data to be output also to the data connection fed to the serial input / output circuit be the initial value of the output of the output to determine the value of the data.