DE19714756A1 - Data processing circuit structure for describing or modelling of digital circuit - Google Patents

Abstract

The circuit for processing several data streams including functional units for carrying out a number of logic or arithmetic basic functions (1e,2e,3e) i.e. ALUs, a digital information store (RAM), (7), clocked registers (6,8) giving stepped status exchange. One ALU (3c) is assigned per data stream (3) and is specially designed for a particular processing task (11-15) and generates the control (11,131,4) data and the input (12;14) data for the RAM (7) or the register (6), with control (6a) or RAM- or register output data (9,10) feedback to the assigned ALU (3c). At least two ALUs (1e,2e,3e) are provided for the data streams (1,2,3) when one ALU function cannot be separated into several ALUs as described.

Description

The invention relates to a circuit structure for processing multiple data streams for describing or modeling digital circuits, which are also called digital Signal processor, hereinafter called DSP, can function.

Circuit structure describes a template or an executed digital circuit for the realization of digital circuits named task. Data streams consist of incoming and outgoing signals from combined Sub-functions of the overall function. There are either complex formats of Data streams, for example a serial bit stream with a bit-coded data format, or just simple, parallel data buses as data streams, for example in a digi tal signal processor. Processing tasks consist of either processing the complex formats of the data streams, for example decoding one serial bit stream, or performing special operations for simple parallel Data formats, for example complex arithmetic operations in a DSP. Of course, there are also mixed forms of the types of data streams mentioned and processing tasks.

A description or model of a circuit can be found next to a circuit diagram also descriptions in the register transfer level or descriptions of behavior of any kind, for example in VHDL or Verilog. These can be acquainted with th means (circuit synthesis) are converted into a circuit form with which can be implemented in terms of circuitry.

Previously common implementations of digital circuits, the aforementioned task, can generally be divided into 2 implementation groups.

On the one hand, an implementation of microprocessor systems, following MPS called, which generally consist of a RAM, a register set, a ALU and a control logic and peripheral connection options exist. On Bus system connects the named elements with each other (for example in the open documents DE 36 36 095, DE 29 44 419 or in the patent DE 43 12 090 C2).

In an MPS, the task is realized by the differenti Chen data streams assigned to the peripheral connection options of an MPS are, as well as a pre-assignment of the RAM unit with a microcode. This ensures that the MPS monitors every single condition of all incoming lines Data streams are queried one after the other and stored in registers or RAM cells. With With the help of a central ALU or control logic, new states of the outgoing Lines of all data streams calculated and modified. This turns into processing the data streams only an ALU or control logic for controlling the RAM unit or the register is used. That means the data streams become a total data stream can be summarized. The function of the individual ALU or control logic to solve all processing tasks of the data streams equally. The ALU or control logic is therefore relatively simple arithmetic and logic Functions designed so that different complex processing functions of the individual data streams must be processed in many cycle steps.  

In special versions of MPS, so-called superscalar MPS or VLIW machines (VLIW: Very Long Instruction Word), arith is parallelized metallic data manipulation with the help of several ALU units. That’s it possible to reduce the number of clock cycles. Edit these ALU units but not the RAM / register control. This is like the simple MPS with only one ALU unit, can only be influenced centrally. This means that, for Example of complex address calculations, the address data via the ALU units first modified as normal data information and abge in an address register must be saved.

(Described in the specialist book "Computer Architecture", 2nd edition by Wolfgang K. Giloi, Springer-Verlag Berlin from page 187 chapter "Superscalar processors and VLIW machines", well presented from page 194, sub-section 6.3.3 "Motorola MC88110", specifically Figure 6-7 "Block diagram of the Motorola MC88110 processor" or sub-item 6.6 "The VLIW machine", Figure 6-17 "Basic diagram of a VLIW machine";
Note: There (Fig. 6-17) it can be clearly seen that the address information, as part of the control, cannot be influenced via the "Floatingpoint" or "integer ALU" units.)

As a rule, MPS are specified as hardware, for example as a finished microchip, or as a CAD system description for integration into a larger ASIC (Applica tion specific integrated circuits) in CAD design, in practice also as core or Called Macro Cell.  

The second implementation group includes digital circuits in which the complex Processing tasks can be implemented purely in terms of circuitry. That kind of digi tal circuit are usually with a hierarchical design methodology (Top Down) realized. Sub-modules of the overall circuit are usually sequential State machines, for example designed as Mealy or Moore machines. The This implementation form is called special circuit in the following.

When processing as MPS, the following disadvantages generally occur on. The processing of a data stream usually requires a large number of functions of clock cycles. These are needed to keep the information of everyone arriving To receive and store signal streams. After reading the microcode from RAM, this information is modified in the ALU and at the specified time again made available to the outgoing signal streams. The strictly sequential Processing results from the use of only one ALU or only one tax logic (see superscalare or VLIW machines) with relatively simple, general usable logical or arithmetic basic functions which are used for the machining tion of all data streams is used. This requires that the MPS with a higher clock frequency, relative to the highest frequency of a data stream, work got to. This creates greater demands in terms of delays in the design times of the hardware to be used. This will reduce the power consumption of the MPS increases or the range of applications in applications with high clock rates borders. The available MPS are still fixed systems with very limited customization options, which for the realization of special Requirements are used. In most cases, MPS are oversized based. This has an adverse effect on the production costs.

Mentioned disadvantages of MPS implementations may be special circuits are avoided. However, this comes at the cost of flexibility Circuit function, since all processing steps are implemented in terms of circuitry have to. After the completion of the overall circuit is a change in the Function no longer possible. That means that before manufacturing the circuit in practice a considerable amount of development time, from qualifi graceful staff and cost intensive CAD development software to minimize the risk of an undesirable development. When executing one Special circuit is also disadvantageous that the sub-modules as a sequential state machine are realized. This means that there are many in the special circuit of clock edge-controlled status registers, which in the implemented circuit, for example in an ASIC layout, in the circuit arrangement together with combinatorial circuit elements are distributed. This has a particular impact disadvantageous when routing the clock connections to the status registers. This easily creates the problem of clock skew. Clock skew is one undesired phase shift in clock connections. It continues to grow with the number of clock edge controlled status registers the dynamic loss power that accounts for a large part of the total power loss. Another ent a crucial point in ASIC's is the testability of a circuit during the pro production phase. There it is the target with a minimum number of test vectors one To ensure minimum coverage of possible manufacturing defects. To achieve this Chen, it is necessary to use the existing, functionally finished special circuit to expand through test structures. This has a considerable effect with a special circuit Enlargement of the finished circuit area as a result of the more processing steps of the data streams exist.  

The invention has for its object a circuit structure for processing to create multiple data streams, from which a reduced development effort to describe and model a digital circuit. This should Ensure flexibility of function even after completion. Farther should reduce the electrical operating power required and the testability in one early phase of design with little effort from test structures be guaranteed. For the gradual processing of the data streams, only a few clock cycles are required. The circuit is also intended for many applications Processing of data streams may be suitable. In addition, a high over Visibility of the circuit can be guaranteed by a few sub-modules in order to work with we little special knowledge to modify an existing circuit.

This object is solved by a circuit structure comprising at least follow de elements has (see Figures 1, 2, 3...):

• - Functional units in which arithmetic or logical functions are implemented electronically, hereinafter referred to as ALU ( 1 e, 2 e, 3 c).
• - A storage unit for digital information, hereinafter called RAM ( 7 ).
• - Clock-controlled register to ensure a clock-wise change of state ( 6 ).

Such a circuit structure is characterized by the following main features:

• - for a data stream ( 3 ) an ALU ( 3 c) is assigned,
• - The assigned ALU ( 3 c) is specially designed for the processing task ( 11, 12, 13, 14, 15 ) and processes the processing task comprehensively (IDLE, TRA3.0 / REC3.0 to TRA3.n / REC3.n or E3 / E4, IT3.0 / IR3.0 to R6 / R5),
• - The assigned ALU ( 3 c) generates the control ( 11 , 13 , 14 or 3 d, 3 f, 3 g or 4 a, 4 c, 4 d or 6 a, 6 c, 6 d) and Input data ( 12 or 3 e or 4 b or 6 b) for the RAM ( 7 ) or the register ( 6 ),
• - The control ( 6 a) or the RAM or register output data ( 9 , 10 ) is fed back to the assigned ALU ( 3 c),
• - There are at least two ALU units ( 1 e, 2 e, 3 c) assigned to data streams ( 1 , 2 , 3 ) if an ALU function cannot be divided into several assigned ALU units with the aforementioned features.

Furthermore, a circuit structure is marked with said properties by the following, advantageous side points (see Figures 1, 2, 3, 4, 5.....):

• - Clock-controlled registers are inserted ( 6, 8 ) so that a large part of all ALU functions are in a signal path between a minimum number of register stages ( 6 , 8 ).
• - The ALU units mutually generate the RAM write accesses.
• - Outgoing signal lines ( 1 c, 1 d, 2 d, 2 c, 3 b) are controlled with every clock change.
• - The circuit structure described can be created as a template from which specific digital circuits are developed or from which a model for Simulation is created.
• - The circuit structure, or, derived from its template, have circuits Test structures, with some of the test structures serving the RAM and the other test structures are inserted so that the ALU functions are observable.
• - Each ALU ( 27 , 28 , 29 , 30 ) is assigned a part ( 21 , 22 , 23 , 24 , 25 ) of the RAM area ( 26 ) in which the assigned ALU can carry out write operations.

Fig. 1 shows the block diagram of the preferred embodiment.

Fig. 2 shows the block diagram of an ALU.

Fig. 3 shows a basic sequence for operating the circuit structure.

Fig. 4a shows a basic circuit diagram of the circuit structure as DSP.

FIG. 4b shows an example of a RAM subdivision for the ALU write accesses (with reference to FIG. 4b).

As shown in FIG. 1, the preferred embodiment of a circuit structure processes three data streams 1, 2, 3 . The first data stream 1 consists of 2 incoming signals, each with an outgoing (outgoing) and incoming (incoming) 1-bit line 1 a, 1 c and an outgoing data bus 1 d with a bus width of u and one incoming. Data bus 1 b with the bus width of z. The second data stream 2 has the same format as data stream 1 only with the bus widths s and t. The third data stream 3 consists of an ank. 1-bit line 3 a and an ab. 1-bit line 3 b. These data streams are assigned 3 ALU units 1 e, 2 e, 3 c, which are adapted in their function to the processing tasks of the data streams. 2 RAM control signals 1 f, 1 g, 2 f, 2 g, 3 f, 3 h run from each ALU, which, like the ALU address 1 i, 2 i, 3 d and data lines 1 h, 2 h, 3 c to the ALU-MUX 4 module. In the ALU-MUX 4 module, all inputs are combined into one control group each, consisting of the control signals 4 c, 4 d and the address 4 a and RAM input data bus 4 b. Before these act as RAM inputs 6 a, 6 b, 6 c, 6 d, a register stage 6 , consisting of (x + y + 2) registers, is interposed, for example D flip-flops, which operate with clock 5 to be controlled. The register outputs act as RAM control. In addition, the address lines 6 a are fed back to the ALU units 1 e, 2 e, 3 c. This also happens with the RAM output data 10 after they also pass through a register stage 8 , which comprises y registers, controlled by the clock 5th The RAM 7 usually consists of a memory field, an address decoder and control logic.

The inner realization principle of the ALU3 3 c can be seen in FIG. 2. The address bus 6 a and the RAM data output bus 10 and the ank. Line 3 a serve as inputs for the ALU3 components SUB-ALU3.1 11 , for generating the ALU3 address bus 3 d. The ALU3 data input bus 3 e is generated via SUB-ALU3.2 12 . CONTROLLOGIK3.1 13 generates the ALU3 control line Read 3 f. CONTROLLOGIK3.2 14 is used to generate the ALU3 control line Write 3 g and SUB-ALU3.2 15 is used to generate the line 3 b. The ALU1 1 e and ALU2 2 e are implemented in a similar way.

The following explanations refer to FIG. 3. From the basic state IDLE, to which a start address is assigned, depending on the occurrence of various signals of the incoming data streams or the state of the RAM data, E1-E6, the following states TRA1, REC1, TRA3 can be used. 0, REC3.0, TRA2, REC2. This is done by assigning an address in the RAM area to each state, which calculates the relevant ALU. Now the external data can be loaded into the addressed RAM area (REC1, REC3.x, REC2), or the data from this RAM area can be made available via the outgoing lines of the data streams (TRA1, TRA3.x, TRA2) . After this, the game returns to the basic state IDLE. The RAM data of the start address can also be influenced, but also the outgoing signal streams of the data streams (R1, R2, R3, R4, R5, R6).

In particular for the processing of the data stream 3 , it should be noted that during the state transitions (IT3.x or IR3.x), in addition to the mere storage or transmission, the data can be manipulated by, for example, a data bit (a bit line from RAM output data bus 10 ) with the previous data bit (another bit line from RAM output data bus 10 ) via XOR logic (implemented in SUB-ALU3.2 12 and SUB-ALU3.3 15 , Fig. 2) is linked. Depending on the state (IT3.x or IR3.x), this link can be activated or deactivated in the ALU. With this measure, special polynomial operations, for example scrambling functions, CRC test functions, error corrections or encryption operations, can be easily implemented, which are required in many applications, for example in DECT / GSM applications. The following tables explain the functional sequence in connection with FIG. 3.

Table 1 lists the states and their functional combination hang in the overall circuit. In table 2 all actions are listed, which ones received with the individual changes of state or generated by the circuit will.  

Table 1

Explanation of the states in FIG. 3

Table 2

Events for state changes in FIG. 3

The preceding explanations related to the implementation principle of the circuit structure as an alternative to special circuits (reference to FIG. 1, FIG. 2, FIG. 3). Compared to the special circuits, the circuit structure is characterized by the fact that the required state or data memory of a circuit can be put in the RAM for the most part. Only global states are expediently implemented in edge-controlled registers. These are ( Fig. 1) the address register 6 a. This results in the following advantages over conventional special circuits for an ASIC design based on the circuit structure:

• 1. The power consumption of the overall circuit is limited because only a few power-intensive edge-controlled registers are used.
• 2. The testability of the circuit structure is guaranteed from the specification phase, since the register structure is qualitatively fixed. These registers can now usually be replaced by special test registers. This ensures the applicability of automatic test pattern generators (ATPG), which significantly shortens the time to implement test patterns and achieves a minimum number of test patterns per circuit. The observability of the circuit in the test is good because the combinatorial elements lie between only two register stages ( 6 , 8 ).
• 3. The area requirement of the circuit is less because a large part of the system states de and data are in RAM, which is usually optimized in terms of space requirements (at ASIC’s) because only a few (test) registers exist and because a large part of all ver combinatorial elements used lie between only two register levels. There with it is possible with relatively simple means of Boolean algebra redundant Eliminate combinatorics. This is usually done automatically by a synthesis se program if the circuit as a synthesis-capable description, VHDL or Veri log, is present. (In the case of special circuits, the combinatorial elements are between many register levels.)
• 4. By the spatial separation of combinatorial elements and the together hanging structures of the registers problems in the ASIC layout are avoided (see clock skew).
• 5. The circuit structure is particularly simple with HDL programming languages, VHDL or Verilog to implement, since only a few submodules exist. Here In particular, the ALU submodules can also be used by developers with relatively few Knowledge of the HDL programming languages mentioned can be implemented. Farther it is possible to produce templates.
• 6. The circuit structure can be designed to be functionally flexible. This is dependent gig, how specially designed the individual ALU functions for the processing task are. Relatively simple ALU functions can make processing tasks more universal process by processing RAM contents as microcode similar to MPS. The functional sequence can then also be modified by modifying the microcode Manufacturing affected as ASIC. A data stream with ALU can function as Loading, for example an initial state, or reading out the RAM content take over.

Point 6 just described is the starting point for further use speed of the circuit structure described. Attention is drawn to the fact that even a circuit structure with the least flexibility, i.e. close to a special scarf benefits (see points 1-5).

The circuit structure, which is similar in function and structure to an MPS or a DSP, is shown in principle in FIG. 4a. Here special arithmetic functions are used as processing tasks of the data streams of the same format. A structure with 4 ALU blocks is shown, an ALU 27 existing, which has conventional functionality, and primarily serves the interface to standard inputs / outputs 16 , 17 . There are also 2 special ALU blocks 28 , 29 that can process special arithmetic operations with fewer cycles than the standard ALU 27 . The fourth ALU block 30 is the ALU with the most specialized function. This is intended to serve an external control object 18 and thus represents the control function of a control chain. All data are routed to a data bus 20 here. Furthermore, the address control of this DSP is influenced in all ALU functions ( 27 , 28 , 29 , 30 ).

Is used for the basic operation of this DSP circuit principle Fig. 4b, which assigns the write access to the RAM 7. The standard ALU 27 and standard I / O 17 have write access 25 to the entire RAM area 26 in an initialization phase. This allows presettings, for example for the ALU 30 controller, to be made. After initialization, this write access is limited to part of the RAM area 21 . The ALU blocks 28 , 29 , 30 can only access limited RAM areas 22, 23, 24 .

Thanks to this functional principle, the special ALU functions can perform the tasks from co-processors, which are traditionally integrated in parallel to the MPS that will. When implementing such DSP structures, it is certainly advisable to use ent to develop speaking compilers or linkers to handle the program optimize. The decisive advantage is the reduction in the clock rate over conventional DSP / MPS seen because external data streams directly through the ALU blocks have direct access to RAM.

Claims (7)

1. Circuit structure for processing several data streams ( 1 , 2, 3 ) for describing or modeling digital circuits, the format of at least one data stream or at least one processing task of the individual data streams being sufficiently complex, at least consisting of functional units in which a large number of logical ones or basic arithmetic functions are implemented electronically ( 1 e, 2 e, 3 c), hereinafter such a functional unit is referred to as an ALU, from a storage unit of digital information ( 7 ), hereinafter referred to as RAM, from clock-controlled ( 5 ) registers ( 6 , 8 ), which are installed appropriately so that there is a gradual change of state, characterized by the following features:

• - for a data stream ( 3 ) an ALU ( 3 c) is assigned,
• - The assigned ALU ( 3 c) is specially designed for the processing task ( 11, 12, 13, 14, 15 ) and processes the processing task comprehensively (IDLE, TRA3.0 / REC3.0 to TRA3.n / REC3.n or E3 / E4, IT3.0 / IR3.0 to R6 / RS),
• - The assigned ALU ( 3 c) generates the control ( 11 , 13 , 14 or 3 d, 3 f, 3 g or 4 a, 4 c, 4 d or 6 a, 6 c, 6 d) and Input data ( 12 or 3 e or 4 b or 6 b) for the RAM ( 7 ) or the register ( 6 ),
• - There is a feedback of the control ( 6 a) or the RAM or register output data ( 9 , 10 ) to the assigned ALU ( 3 c),
• - There are at least two ALU units ( 1 e, 2 e, 3 c) assigned to data streams ( 1 , 2 , 3 ) if an ALU function cannot be divided into several assigned ALU units with the aforementioned features.

2. Circuit structure according to claim 1, characterized in that a minimum number of clock-controlled ( 5 ) register stages ( 6 , 8 ) are inserted so that the majority of all combinatorial elements, which are essentially in the ALU units ( 1 e, 2 e, 3 c) are realized, lie in the signal path between the register outputs ( 6 a, 10 ) and register inputs ( 4 a, 4 b, 4 c, 4 d). 3. Circuit structure according to claim 1, characterized in that the ALU units ( 1 e, 2 e, 3 c) mutually generate the write accesses to the RAM ( 7 ). 4. Circuit structure according to claim 1, characterized in that outgoing ( 1 c, 1 d, 2 c, 2 d, 3 b) signal lines of the data streams ( 1, 2, 3 ) are controlled with each change of state. 5. Circuit structure according to claim 2 characterized, that the circuit structure or derived digital circuits according to patent Claim 7 have test structures that generate minimal numbers of test samples, preferably with automatic test sample generators, guarantee through which manufacturing defects in digital circuits can be identified, where a summarizable unit of a test structure serves the storage unit, other test structures are inserted so that the other logical elements or Connections of this circuit structure are observable. 6. Circuit structure according to claims 1, 2, 3, 4, 5 characterized, that the circuit structure is created as a template or as a model, from which digi tal circuits can be generated or simulations can be carried out. 7. Circuit structure according to claim 1, characterized in that each ALU ( 27 , 28 , 29 , 30 ) parts of the memory area ( 26 ) of the RAM unit ( 7 ) are assigned ( 21, 22, 23, 24, 25 ), in which the assigned ALU write operations or a modification of the RAM content can make.