DE19701843C1 - Micromechanical structure formation method - Google Patents

Abstract

The structure formation method uses a layered plate (100) having a dielectric layer (3) between (2) silicon layers (1,2), the dielectric layer having (2) silicon oxide layers (4,6) and an intermediate silicon nitride layer (5). Several troughs (12) are etched in one silicon layer (1), which has a thickness of up to (5) times less than the other silicon layer (2) before etching a recess (10) in the latter using an etching solution.

Description

State of the art

The invention is based on a method of manufacture of micromechanical structures according to the genus of independent claim. From DE 43 15 012 already a process for the production of micromechanical Structures known at the bottom Silicon layer is a dielectric layer and then one upper silicon layer is arranged. From the top Silicon layers become structures for one Structured out acceleration sensor. In the lower one Silicon layer is below the moving structures this acceleration sensor etched a recess. in the The area of the moving structures then becomes the dielectric layer removed. The dielectric layer consists of silicon oxide.

Advantages of the invention

The inventive method with the characteristic In contrast, features of the independent claim the advantage that a particularly reliable and safe Manufacture of micromechanical structures guaranteed  becomes. This is achieved in that in the dielectric Layer defines tensile stresses can be set which then allow particularly fine micromechanical Form structures in the first silicon layer without risk of breaking the dielectric layer. The The second silicon layer can therefore be structured easily as the last etching step of the manufacturing process of the micromechanical structures take place as the under tension standing, dense dielectric membrane a reliable Ensures sealing to the front and this before Shields wet etching medium.

By those listed in the dependent claims Measures are advantageous training and Improvements to the independent process Claim possible. The first silicon layer can significantly thinner, especially at least five times thinner than the second silicon layer are formed. It can particularly fine structures are formed that initially with connected to a massive substrate plate and therefore very are stable. If the second, thicker silicon layer is etched last, the handling during the Manufacturing simplified and there is no risk that the sensitive micromechanical structures or the whole Wafers can be destroyed by a break. Wet chemical etched Wafers break very easily because the etch stops Crystal planes just the easily fissile directions of the Correspond to silicon crystal. It will be particularly easy dielectric layer formed by two Silicon plates connected to each other by a bonding process be, one on one of these silicon plates Silicon nitride layer is arranged, the surface of which an oxidation process in a silicon oxide layer was converted. Such silicon plates can be problem-free thanks to a direct bonding process (SFB = silicon  fusion-bonding). After connecting can then reduce one of the silicon plates in thickness to form the first thin silicon layer.

drawings

Embodiments of the invention are in the drawings shown and in the following description explained. They show

Fig. 1 and 2, the manufacturing method based on cross-sections through the silicon layer and

Fig. 3 shows a plan view of the first silicon layer.

description

In Fig. 1 a cross section is shown through a layer plate 100 having a first silicon layer 1 and a second silicon layer 2. Between the first silicon layer 1 and the second silicon layer 2, a dielectric layer 3 is arranged. The dielectric layer 3 has a plurality of dielectric individual layers. A silicon oxide layer 6 is provided for the first silicon layer 1 and a silicon oxide layer 4 is provided for the second silicon layer 2 . A silicon nitride layer 5 is arranged between the two silicon oxide layers 4 , 6 .

The individual layer thicknesses and lateral dimensions are not shown to scale here. The first silicon layer 1 typically has a layer thickness between 20 to 70 μm, preferably 50 μm, the second silicon layer has a thickness between 300 and 700 μm, preferably 450 μm, the oxide layer 6 has a thickness of typically between 300 to 700 nanometers, preferably 500 nanometers Silicon nitride layer 5 has a thickness of approximately 100 to 500 nanometers, preferably 300 nanometers, and the silicon oxide layer 4 has a thickness of approximately 10 to 20 nanometers. Since the layer plate 100, as will be described later, results from the connection of conventional silicon wafers, the lateral dimensions of the layer plate 100 range from 10 cm (four-inch wafers) to 20 cm (eight-inch wafers).

To produce the layer plate 100 , a first silicon wafer and a second silicon wafer are connected to one another. The thickness of the second silicon wafer is essentially the thickness of the second silicon layer 2 . The thickness of the first silicon wafer is significantly greater than the thickness of the first silicon layer 1 . The individual layers of the dielectric layer 3 are then produced on one of these two silicon wafers. For the following description it is assumed that this takes place on the first silicon wafer. The desired layer thickness for the silicon oxide layer 6 is first generated by thermal oxidation. Thermal oxidation creates silicon oxide layers with an extremely high surface quality, which are outstandingly suitable for further processing, in particular for a bonding process. A silicon nitride layer is then produced on this thermal silicon oxide layer, the thickness of which is slightly larger than the desired thickness of the silicon nitride layer 5 . If this silicon nitride layer is produced by an LPCVD process (low pressure chemical vapor deposition process), the high surface quality required for the bonding process can also be guaranteed. Since the surface of such a nitride layer is generally hydrophobic and not suitable for connection to silicon plates, a repeated thermal oxidation reoxidizes a surface layer of this silicon nitride layer while maintaining the surface quality, ie converts it back into silicon oxide. Since this process is very slow, only small layer thicknesses of the order of 10 to 20 nanometers can be produced. However, this thin surface oxide layer 4 can then be used to connect the first silicon wafer to the second silicon wafer. This takes place after a corresponding surface pretreatment by hydrophilizing the silicon or silicon oxide surface. The connection is established by placing the first silicon wafer with the oxide layer 4 on the second silicon wafer. If this stack is then heated, there is a firm, no longer detachable connection between the two silicon wafers. In a subsequent step, the thickness of the first silicon wafer is then reduced in order to set the desired thickness of the silicon layer 1 . This can be done by mechanical processing such as grinding and polishing or by chemical processing such as chemical etching. The different methods can also be combined.

The mechanical stress in the dielectric layer 3 can be set by the construction of the dielectric layer 3 from silicon oxide and silicon nitride. This is made possible by the fact that silicon oxide layers are under compressive stresses relative to silicon and silicon nitride layers are under strong tensile stresses relative to silicon. The mechanical stresses in the dielectric layer 3 can thus be influenced by a suitable choice of the parameters in the production of the layers and by a suitable thickness combination of the layers 4 , 5 and 6 . In the present case, the layer thicknesses are selected so that there are slight tensile stresses in the dielectric layer 3 relative to the silicon of the first silicon layer 1 and second silicon layer 2 .

The meaning of these additional tensile stresses is described in the further course of the manufacturing process, as shown in FIG. 2.

In FIG. 2 a cross section is shown by the layer panel 100 for further processing steps. With the reference numerals 1 , 2 , 3 , 4 , 5 and 6 the same objects are again described as for FIG. 1. However, trenches 12 are etched into the first silicon layer 1 , through which a bending tongue 11 is structured out of the upper silicon layer 1 . A recess 10 is etched into the second silicon layer 2 and is arranged below the bending tongue 11 . A top view of the first silicon layer 1 of the layer plate 100 is shown in FIG. 3. FIG. 2 corresponds to a cross section along the line II-II of FIG. 3. As can be seen in FIG. 3, the bending tongue 11 is suspended from a bearing block 15 . The bending tongue 11 and the bearing block 15 are completely surrounded by the trench 12 . Furthermore, the upper dimension of the recess 10 is shown in FIG. 3, so that it can be seen that the recess 10 is arranged below the bending tongue 11 . No recess 10 is arranged below the bearing block 15 . 100 with an etching medium for the dielectric layer, in particular a hydrofluoric acid solution or a Flußsäuredampfes etching of the dielectric layer 3 by subjecting the layer board in a further etching step. By removing the dielectric layer 3 in the region of the bending tongue 11 , this bending tongue becomes a movable element which can be moved as a function of an acting force, for example when accelerating. The etching of the dielectric layer 3 is carried out in such a way that the bearing block 15 is not undercut due to its large lateral dimensions. The bending tongue 11 is thus firmly connected to the silicon layer 2 via the dielectric layer 3 remaining under the bearing block 15 . The structure formed in this way represents the basic structure of a micromechanical force sensor, in particular an acceleration sensor, without a completely functioning example being given here. With a movable structure that is firmly anchored, however, the basic structure of numerous micromechanical force sensors is represented.

Of particular importance is the function of the multilayer dielectric layer 3 with controlled voltage relative to silicon in the process step shown in FIG. 2. As shown in FIG. 2, in the upper silicon layer 1 is a grave structure is etched 12, which extends from the top of the first silicon layer 1 up to the dielectric layer 3. This trench structure 12 is etched by a plasma etching process with which the first silicon layer 1 can be etched with almost vertical walls. Such a plasma etching process can be used with acceptable process times for silicon layers up to a layer thickness of a few 10 μm. The recess 10 in the second silicon layer 2 is preferably etched through the use of a basic anisotropic etching solution, for example KOH, TMAH or NaOH. Since the layer thickness of the second silicon layer 2 is generally a few hundred μm in order to obtain a manageable micromechanical structure, plasma etching processes for the etching of the second silicon layer 2 can only be used while accepting long process times. Because of the different etching methods, the etching processes for the first silicon layer 1 and the second silicon layer 2 have to be carried out in succession. If the second silicon layer 2 is first etched and the first silicon layer 1 is etched in a subsequent step, the handling of the layer plate after the first etching step is extremely problematic. The reason for this is that the first silicon layer 1 is considerably thinner than the second silicon layer 2 , which, however, has already been mechanically destabilized by the first etching step and can therefore break very easily. The etching limits in anisotropic wet etching precisely define the easily cleavable <110 <directions on the wafer. The introduction of a silicon wafer into a plasma etching system is usually carried out by an automatic handling device, so that the risk of breakage is comparatively high at other points in the plasma etching process. If a silicon wafer breaks within a plasma system, the entire system has to be laboriously cleaned, which leads to considerable disruptions and delays in the production process. It is therefore highly desirable to first etch the first silicon layer 1 and only in a process step which is as late as possible to etch the second silicon layer 2 . However, sufficient stability of the dielectric layer 3 must be ensured so that the alkaline etching solution cannot reach and destroy the thin structures of the bending tongues 11 or possibly other structures produced in the first silicon layer 1 (in particular circuits). The application of the first silicon layer 1 with the basic etching solution for the second silicon layer 2 would have the immediate destruction of the formed in the first silicon layer 1 micromechanical structures result. The dielectric layer made of silicon oxide known from DE 43 15 012 has the problem that silicon oxide is under compressive stresses which are so great that when the recess 10 is etched, the dielectric layer cracks as soon as the dielectric layer is exposed. Experiments have now shown that the multilayer dielectric layer 3 made of silicon oxide and silicon nitride is a highly stable membrane when large tensile stresses are set, in which large membrane areas can be exposed without causing cracks in the dielectric layer 3 and thus a loss of insulation properties Front is coming. Such a dielectric layer 3 with slight tensile stresses can therefore be used to etch recesses 10 into the second silicon layer 2 by means of basic etching solutions, even if the upper silicon layer 1 is already structured in the region of the recess 10 . By using such a dielectric layer 3 , the recesses 10 can thus be reliably, inexpensively and easily etched using basic etching solutions.

Claims (8)

1. A method for producing micromechanical structures in which a layer plate ( 100 ) with a first silicon layer ( 1 ) and a second silicon layer ( 2 ) and a dielectric layer ( 3 ) arranged therebetween is first created, with subsequent steps into the first silicon layer ( 1 ) and the second silicon layer ( 2 ) structures are etched and then the dielectric layer ( 3 ) in the area of the etched structures is removed by a further etching step, characterized in that the dielectric layer ( 1 ) has a first silicon oxide layer ( 6 ) and has a second silicon oxide layer ( 4 ) with a silicon nitride layer ( 5 ) arranged between them. 2. The method according to claim 1, characterized in that the first silicon layer ( 1 ) is formed thinner than the second silicon layer ( 2 ). 3. The method according to claim 2, characterized in that the first silicon layer ( 1 ) is formed at least five times thinner than the second silicon layer ( 2 ). 4. The method according to claim 2 or 3, characterized in that in a first etching step, the first silicon layer ( 1 ) and in a second subsequent etching step, the second silicon layer ( 2 ) is etched. 5. The method according to claim 4, characterized in that the second silicon layer ( 2 ) is etched with a basic etching solution, and that this etching step is carried out as the last step of the method. 6. The method according to any one of the preceding claims, characterized in that the layer plate ( 100 ) is created by connecting a first silicon plate and a second silicon plate to one another, wherein a silicon nitride layer is deposited on at least one of the silicon plates, that the surface of the silicon nitride layer by an oxidation process is converted into a silicon oxide layer, and the silicon oxide layer ( 4 ) thus obtained is connected to the other silicon plate. 7. The method according to claim 6, characterized in that a silicon oxide layer ( 6 ) is generated before the deposition of the silicon nitride layer ( 5 ). 8. The method according to claim 6 or 7, characterized in that after connecting one of the silicon plates in your Thickness is reduced.