DE19655128C2 - Semiconductor device generating internal operating factor corresp. to external factor - Google Patents
Semiconductor device generating internal operating factor corresp. to external factorInfo
- Publication number
- DE19655128C2 DE19655128C2 DE19655128A DE19655128A DE19655128C2 DE 19655128 C2 DE19655128 C2 DE 19655128C2 DE 19655128 A DE19655128 A DE 19655128A DE 19655128 A DE19655128 A DE 19655128A DE 19655128 C2 DE19655128 C2 DE 19655128C2
- Authority
- DE
- Germany
- Prior art keywords
- factor
- corresp
- circuit
- signal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19654935A DE19654935C2 (en) | 1995-02-06 | 1996-01-26 | Semiconductor device generating internal operating factor corresp. to external factor |
DE19655211A DE19655211B4 (en) | 1995-02-06 | 1996-01-26 | Semiconductor device generating internal operating factor corresp. to external factor - contains difference controller, differential amplifier, internal clock circuit, current supply element and resistance element producing feedback voltage |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1808695 | 1995-02-06 | ||
JP12262195A JP3523718B2 (en) | 1995-02-06 | 1995-05-22 | Semiconductor device |
DE19654935A DE19654935C2 (en) | 1995-02-06 | 1996-01-26 | Semiconductor device generating internal operating factor corresp. to external factor |
DE19655211A DE19655211B4 (en) | 1995-02-06 | 1996-01-26 | Semiconductor device generating internal operating factor corresp. to external factor - contains difference controller, differential amplifier, internal clock circuit, current supply element and resistance element producing feedback voltage |
Publications (1)
Publication Number | Publication Date |
---|---|
DE19655128C2 true DE19655128C2 (en) | 2001-10-31 |
Family
ID=27438519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19655128A Expired - Fee Related DE19655128C2 (en) | 1995-02-06 | 1996-01-26 | Semiconductor device generating internal operating factor corresp. to external factor |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE19655128C2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5061907A (en) * | 1991-01-17 | 1991-10-29 | National Semiconductor Corporation | High frequency CMOS VCO with gain constant and duty cycle compensation |
US5175512A (en) * | 1992-02-28 | 1992-12-29 | Avasem Corporation | High speed, power supply independent CMOS voltage controlled ring oscillator with level shifting circuit |
-
1996
- 1996-01-26 DE DE19655128A patent/DE19655128C2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5061907A (en) * | 1991-01-17 | 1991-10-29 | National Semiconductor Corporation | High frequency CMOS VCO with gain constant and duty cycle compensation |
US5175512A (en) * | 1992-02-28 | 1992-12-29 | Avasem Corporation | High speed, power supply independent CMOS voltage controlled ring oscillator with level shifting circuit |
Non-Patent Citations (1)
Title |
---|
Mijuskovic,D. et al. "Cell-Based Fully Integrated CMOS Frequenzy Synthesizer". In: IEEE Journal of Solid-State Circuits, Vol.29, No.3, March 1994, S.271-279 * |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
Q172 | Divided out of (supplement): |
Ref country code: DE Ref document number: 19654935 |
|
8110 | Request for examination paragraph 44 | ||
8172 | Supplementary division/partition in: |
Ref country code: DE Ref document number: 19655211 Format of ref document f/p: P |
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Q171 | Divided out to: |
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AC | Divided out of |
Ref country code: DE Ref document number: 19654935 Format of ref document f/p: P |
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AH | Division in |
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D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
AC | Divided out of |
Ref country code: DE Ref document number: 19654935 Format of ref document f/p: P |
|
8339 | Ceased/non-payment of the annual fee |