DE19641112A1 - End-to-end clock recovery for ATM networks - Google Patents

Abstract

The invention relates to the field of telecommunications, and more particularly to a method and apparatus for conveying timing information in packet switched, asynchronous data networks, such as ATM (Asynchronous Transfer Mode) networks. A source 1 includes a cell emitter 3 that emits ATM cells 4 over a constant bit rate, virtual connection, at a rate that is related to payload clock 2, which references the timing information for the payload data of the ATM cells 4. At the destination 5, the ATM cells 4 are received by cell receiver 6, which transfers the cells to read buffer 14. The rate of arrival of cells is timed by timer 10 and averaged by averaging circuit 11. Destination payload clock 12 generates payload clock signals referenced to the average rate of arrival of cells at cell receiver 6. Thus, the cell emission rate of the virtual connection is used to convey timing information.

Description

This invention relates to the field of telecommunications and in particular a method and a device for transmission clock information in asynchronous packets switched in packets Data networks, such as ATM (asynchronous transmission mode) networks.

To provide real-time interactive services such as To transmit voice phone traffic in ATM networks, clock information must be provided in connection with the payload information to be provided. This clock information is for the synchronization of coded payload on Decoder / encoder used by the user.

The existing telephone network is a synchronous time division multiplex (Time Division Multiplexed) (TDM) network. This digital network (PSTN-Public Switched Telephone Network) uses 8 kHz clock information for synchronization and transmission of real time information with a constant Delay between two endpoints, e.g. B. a telephone.

A B-ISDN (Integrated Broadband Service Digital Network) network uses the asynchronous transmission mode (Asynchronous Transfer Mode) (ATM) technology for transfer and switching or switching operations. To one Real-time information, such as a voice phone between synchronous PSTN / PBXs networks and asynchronous B-ISDN (ATM) networks to transmit must have a certain means  be provided in order for the encoded information end to end clock or time control information.

A known method for transmitting clock information uses loop timing out. The loop clock uses a physical or physical layer of the interface for coding and transmission 8 kHz clock information from the switch to the end station. In this method, the synchronization of the narrowband TDM PSTN or private PBX network on the ATM network to be expanded. Most ATM auxiliary systems (premise), which are manufactured and traded today However, the 8 kHz clock information can be used do not transfer or deliver the loop clock.

An object of the present invention is to achieve the above overcome the disadvantage mentioned, and a method and a device for end-to-end or end-to-end end) to create recoveries for ATM networks without use the conventional 8 kHz clock information is satisfactory work.

In one aspect, the present invention provides a method for transferring payload clock information between a source and a type of determination via an asynchronous Network, taking data as a lead and containing payload fields Packets are transmitted, including the steps: Emit the packets at the source at a rate that is in Relation to the payload clock information, and recoveries the cycle information at the destination from the information rate of the packages.

The network is preferably an ATM network, in which case the packets are ATM cells.  

While the inventive method in connection with a 3.1 kHz µ law or A law coded 64 kbit / s PCM information is explained, it is based on other data rates and others Coding schemes applicable. This explained end-to-end clock recovery method is independent of the transmission rate and the ATM adaptation layer (AAL). It can be for any Application and for each AAL, if one Transmission of end-to-end clock information is required such as for voice telephony, for H320 video, unencrypted data etc.

For the 64 kbit / s µ-law or A-law PCM-encoded information becomes an octet or a byte of PCM encoded information transmitted after every 125 µs (64 kbit / s). If a cell PDU (Payload Data Unit) - size of 48 Bytes (AAL 0) is used, it would take 6 ms. For one Cell PDU size of 47 bytes (AAL 1) would be 5.875 ms. It can be deduced that in or at a constant bit rate operation a 48-byte PDU size cell for the duration of the Connection is received every 6 ms. For a cell PDU size of 47 bytes, the duration is 5.875 ms. That's why the ATM source emits ATM cells to the ATM network 6 ms each. For different data rates, e.g. B. 384 kbit / s, one cell is transmitted per 1 ms for the 48 byte PDU cell size.

For data rates with 64 kbit / s:

One byte after every 125 µs = 64 kbit / s
and the ATM PDU cell size = 48 bytes (AAL 0),

therefore: ATM PDU size × data transfer rate = cell emission rate

48 × 125 µs = 6 ms

For data rates of 384 kbit / s, corresponding to 6 bytes 1225 µs each, applies:

48 × 125 µs / 6 = 1 ms

Below is a table that shows several different ones Data rates and the calculated cell emission rate for a cell PDU size of 48 bytes (AAL 0).  

Table 1

Cell emission rate for different data rates (AAL 0)

There is only one for the ATM PDU size of 47 bytes (AAL 1) only practical data rate available: 64 kbit / s, since 47 is a primary number. Therefore the cell emission rate is:

47 × 125 µs = 5.875 ms

The invention also provides an arrangement for transmission payload clock information between a source and a  Destination over an asynchronous network, data as transmit packets containing a lead and payload fields with: a packet emitter at the source for emitting of packets via a virtual link of constant bit rate through the network, a clock device for controlling the emission rate of the cells from the emitter with respect to the one to be transferred Payload clock information, a cell receiver on Destination for receiving the cells from the network, and a payload clock for recovering the clock information on Destination from the information rate of incoming cells.

In the following, the invention will only be used as an example explained in more detail on the accompanying drawings; it shows

Fig. 1 is a block diagram of a system according to the invention,

Fig. 2 shows an ATM cell flow format (UNI),

Fig. 3 shows a cell flow in an ATM CBR operation,

Fig. 4 is a block diagram of a clock control and filter circuit, and

Figure 5 is a timing diagram showing a VCO tracking or -Taktgabe a received cell emission rate..

As shown in Fig. 1, a source 1 is connected to a destination 5 via a virtual link which is established by an ATM network in a conventional manner.

The source 1 has a cell emitter 3 which emits ATM cells 4 above or at a constant bit rate, the virtual linking taking place at a rate which is related to a payload clock 2 which provides the clock information for the payload data from relates to the ATM cells 4 .

At the destination 5 , the ATM cells 4 are received by a cell receiver 6 , which transfers the cells to a read buffer 14 . The cell arrival rate is clocked by a timer 10 and averaged by an averaging circuit 11 . A destination payload clock generator 12 generates payload clock signals which are related to the average or averaged cell arrival rate at the cell receiver 6 .

It is clear from this that the cell link rate of the virtual link (VC) is used to transmit the clock information for a constant bit rate (CBR) ATM link between the source 1 and the destination 5 . The timer 10 is also used to detect lost or significantly delayed cells because the ATM network has a low likelihood that cells may be lost or delayed due to switching overload or bit errors.

At the destination 5 , the clock rate is set in order to determine how quickly the received information is read from the receive buffer 14 . The read information rate from or from the buffer must be equal to the information rate written to the buffer. If this relationship cannot be maintained, the receive buffer is not overloaded or underloaded.

Each cell 4 transmitted by the cell emitter 3 has a five octet or byte lead. The lead is used to route the cells in the ATM switches.

Figure 2 shows a diagram of the cell advance format. The fifth byte of the lead is called "lead error control" (HEC). It is used to determine / correct bit errors in the ATM cell lead. This HEC byte is used to transmit the transmitter's cell emission rate over the virtual link (VC).

The characteristics of the ATM network are such that the network a cell delay variation for each CBR link or change (CDV) or introduce a jitter. Furthermore cells in the network can be lost or significantly delayed become (larger than CDV from the VC). Therefore the procedure be able to keep timing information under to transfer the above conditions.

First of all, it must be determined or ascertained when an ATM cell is lost or significantly delayed. This is accomplished by using the timer 10 (timer A in Fig. 3) which times the arrival interval between cells. The receipt of a "advance error control" (HEC) byte in the VC that requires clock information to be transmitted is used to trigger timer A. Under normal conditions, a 48-byte PDU cell size arrives every 6 milliseconds for 64 kbit / s operation. The maximum CDV of the ATM network is determined by signaling and added to the total delay. A maximum CDV of 2 ms is used for this example. Therefore, the timer 10 is set to a PDU cell segmentation delay plus the maximum network link CDV: 6 ms + 2 ms = 8 ms.

The expiration of timer A indicates that a cell for the in Talking virtual channel within the allowed time (8 ms) has not arrived and therefore the cell is lost or is significantly delayed. A clearly delayed cell is a cell that has a longer delay than what was agreed by signaling at the beginning of the connection. For one or more cells that were lost or not in time one or more dummy or Spare cells that contain rest information for the payload  (payload) for voice connections. This keeps the buffer on the correct level (no underload). It also keeps System tracking or tracking how many Replacement cells have been added or added.

Fig. 3 shows cells ms combined with fixed time intervals, in each case after 6 into packets and transmitted. At the destination it is shown that the cells arrive at the receiver with a certain CDV (cell delay variation). In this example, cell n + 2 was lost in the ATM network. A spare cell was added to maintain an appropriate flow of information from the buffer to the decoder. This locally generated spare cell has the same frequency and phase as the locally generated cell emission rate pulse. Therefore, no VCO clock setting occurs when inserting a replacement cell.

At or in the source, the cell emission clock is related to the information encoder (payload) clock 2 . Therefore, the transmitter's encoding clock at the destination can be recovered by determining the arrival rate of incoming cells. Each cell that is not supplied must be replaced by a spare sleep cell such that the decoder receives cells every 6 ms or one byte after 125 µs.

The ATM network delivers the payload (cells) with a jitter (CDV) of 2 ms in this example. This cell reception jitter does not need to be filtered.

Fig. 4 is a simplified block diagram of a digital frequency / phase detector, which determines whether the received payload clock 12 is running slow or fast. This detector compares the phases of the two clocks and decides whether the frequency (f _x ) of the VCO has to be increased or decreased.

The circuit for extracting the clock signals from the incoming cells is shown in more detail in FIG. 4. The digital frequency and phase detector 20 receives at its inputs the incoming cell arrival rate and the generated clock frequency f _x at the destination 5 . The detector 20 generates respective up or down pulses, which are connected by tristable buffers 21 , 22 to the integrator 23 , the output of which is connected to the voltage-controlled oscillator 24 , which generates the recovered clock signal f _x . This signal f _x is applied to the second input of the detector 20 by a divider 25 as the feedback signal.

Fig. 5 shows a timing chart of the two clock rates, and as the digital frequency / phase detector or to the integrator 23 to adjust the frequency of the VCO 14 generates pulses.

The purpose of the integrator 23 is to control the rate of change of the output frequency of the VCO 24 . The integrator 23 can change the voltage threshold at the VCO 24 . The voltage change rate for the integrator 23 is programmable by a resistor R1 and a capacitor C1. The change duration is controlled by the width of the "up" or "down" pulses that are output by the detector 20 . If there is no pulse from the digital frequency / phase detector, the integrator generates a constant voltage level at or for the VCO 14 , which maintains its frequency.

The explained end-to-end clock recovery method can clock information transmitted over asynchronous ATM networks without an 8 kHz frame (frame) information in the physical or physical interfaces must be encoded. That explained Process works on or for current ATM networks and  does not require additional bandwidth or control information from the ATM network. The procedure is for the ATM network transparent.

Claims (20)

1. A method for transmitting payload clock information between a source and a destination over an asynchronous network, wherein data is transmitted as packets containing header and payload fields, comprising the steps of:
Emitting the packets at the source at a rate related to the payload clock information and
Recovery of the clock information at the destination from the arrival rate of the parcels. 2. The method of claim 1, wherein the network is an ATM network and the packets are ATM cells. 3. The method according to claim 2, further comprising the step of Clock signals for the payload at the destination from the Generate clock information. 4. The method of claim 3, wherein each cell has a pre-run error control byte (HEC), and being the arrival rate the incoming cells by determining incoming HECs is determined. 5. The method of claim 3, wherein the arrival rate and the Phase difference arriving cells used at the destination to set a clock that the Clock signals generated at the destination. 6. The method of claim 5, wherein the duration of the adjustment controlled by the width of "Up" or "Down" pulses becomes.   7. The method of claim 5, further comprising the temporal Setting or controlling the arrival of HEC bytes and ignoring bytes that are outside of predetermined Arrive at borders. 8. The method of claim 7, further comprising adding from spare cells to a desired flow of information to keep the decoder if bytes are outside the predetermined Limits are determined. 9. The method of claim 8, further comprising filtering the cell delay variation for the link. 10. The method of claim 9, further comprising using the recovered clock information at the receive buffer read rate to control to buffer overload or underload to prevent at the destination. 11. An arrangement for transmitting payload clock information between a source and a destination via an asynchronous network, wherein data is transmitted as packets containing header and payload fields, with:
a packet emitter at the source for emitting packets via a virtual link at constant bit rate through the network,
a clock device for controlling the emission rate of the cells from the emitter in relation to the payload clock information to be transmitted,
a destination cell receiver for receiving the cells from the network, and
a payload clock for recovering the clock information at the destination from the arrival rate of arriving cells. 12. The arrangement of claim 11, wherein the network is an ATM network and the packets are ATM cells. 13. The arrangement of claim 3, wherein each cell is a pre-run error control byte (HEC), and being the arrival rate incoming cells by detecting incoming HECs is determined. 14. The arrangement of claim 13, further comprising a device for generating clock signals at the destination and an arrival rate and phase detector that operates on the arriving cells and the clock signals responds to the Clock signal generating device in a feedback arrangement to control. 15. The arrangement according to claim 14, wherein the detector "on" - and Generated "down" pulses, and wherein the duration of a change signal, that applied to the clock signal generating device is determined by the width of these pulses. 16. The arrangement according to claim 15, further comprising a device to set the arrival of HEC bytes and for ignoring bytes outside of predetermined ones Boundaries arrive. 17. The arrangement according to claim 16, further comprising a device to add spare cells to a suitable one Maintain flow of information to the decoder if incoming bytes are ignored. 18. The arrangement according to claim 17, further comprising a device to filter out the cell delay variation for the virtual link.   19. The arrangement according to claim 18, wherein the means for filtering the cell delay variation for the virtual Linkage is an integrator. 20. The arrangement of claim 18, wherein the recovered clock information is used to read the receive buffer rate to control a buffer overflow or -to prevent underload.