DE19630902A1 - Temperature monitoring device for power semiconductor IGBT - Google Patents

Temperature monitoring device for power semiconductor IGBT

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Publication number
DE19630902A1
DE19630902A1 DE19630902A DE19630902A DE19630902A1 DE 19630902 A1 DE19630902 A1 DE 19630902A1 DE 19630902 A DE19630902 A DE 19630902A DE 19630902 A DE19630902 A DE 19630902A DE 19630902 A1 DE19630902 A1 DE 19630902A1
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Prior art keywords
power semiconductor
temperature
chip resistor
silicon chip
carrier plate
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DE19630902A
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DE19630902B4 (en
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Olaf Dipl Ing Zschieschang
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IXYS Semiconductor GmbH
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IXYS Semiconductor GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • G01K7/22—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor
    • G01K7/226—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor using microstructures, e.g. silicon spreading resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The monitoring device uses an electrically insulating carrier plate (1), which has metallising surfaces (2). At least one power semiconductor component (3) is arranged on the surfaces. A temperature dependent electric resistance (4a) is used as a temperature sensor. The resistance is a silicon chip resistor with metallised top and bottom main surfaces. The chip resistor is arranged on an individual metallising surface (2a) of the carrier plate. Its electrical connections are led out potential-free across bonding wires (5) and module connections (6) from the power semiconductor.

Description

Die Erfindung bezieht sich auf eine Einrichtung zur Temperaturüberwachung in einer leistungselektronischen Anordnung nach dem Oberbegriff des Anspruchs 1.The invention relates to a device for temperature monitoring in one Power electronic arrangement according to the preamble of claim 1.

In K. Reinmuth, L. Lorenz, S. Konrad, "A New Generation of IGBT′s and Concepts for their Protection", Power Conversion, June 1994 Proceedings, Seiten 139 bis 147, sind zwei prinzipielle Wege zur Durchführung einer Temperaturüberwachung in ei­ ner leistungselektronischen Anordnung beschrieben. Eine leistungselektronische Anordnung kann beispielsweise ein Leistungshalbleitermodul oder eine Anordnung mehrerer solcher Module sein. Im Aufsatz ist ein Leistungshalbleitermodul darge­ stellt, das eine elektrisch isolierende Trägerplatte aufweist, die elektrisch leitfähige strukturierte Metallisierungsflächen trägt und mit Leistungshalbleiterbauelementen, nämlich IGBT′s bestückt ist.In K. Reinmuth, L. Lorenz, S. Konrad, "A New Generation of IGBT's and Concepts for their Protection ", Power Conversion, June 1994 Proceedings, pages 139 to 147, are two basic ways of performing temperature monitoring in egg ner power electronic arrangement described. A power electronic An arrangement can, for example, be a power semiconductor module or an arrangement of several such modules. A power semiconductor module is shown in the article provides an electrically insulating support plate, the electrically conductive structured metallization surfaces and with power semiconductor components, namely IGBT's is populated.

Die erste beschriebene Methode bezieht sich auf eine indirekte Erfassung von Übertemperaturen, z. B. mittels Anordnung eines temperaturempfindlichen Bauele­ ments auf der Trägerplatte eines Leistungshalbleitermoduls.The first method described relates to indirect detection of Overtemperature, e.g. B. by arranging a temperature-sensitive component elements on the carrier plate of a power semiconductor module.

Bei der zweiten Methode wird eine möglichst direkte Messung der Temperatur eines Halbleiterbauelements durch enge räumliche Kopplung eines temperaturempfindli­ chen Bauelements mit der Wärmequelle angestrebt. In dem Aufsatz wird zur Durch­ führung der zweiten Methode eine Anordnung beschrieben, bei der ein zur Tempera­ turerfassung dienender Baustein mittels Kleben auf einen Leistungshalbleiterchip aufgebracht ist. Ein noch engerer Kontakt ist durch Integration eines Temperaturer­ fassungsbausteins im Leistungshalbleiterchip erreichbar.In the second method, the temperature of a is measured as directly as possible Semiconductor component through close spatial coupling of a temperature sensitive Chen component aimed at with the heat source. In the essay it becomes a through leadership of the second method described an arrangement in which a tempera  The door detection module is glued to a power semiconductor chip is applied. An even closer contact is through the integration of a temperature socket in the power semiconductor chip.

Eine solche enge räumliche Kopplung gemäß der zweiten Methode ist angezeigt, wenn eine sehr kleine Zeitkonstante erforderlich ist, um ein Leistungshalbleiterbau­ element z. B. selektiv abschalten zu können bzw. um auf einen Kurzschlußstrom und eine daraus resultierende plötzliche Erwärmung schnell reagieren zu können. Diese Methode ist aber nicht uneingeschränkt zur Erfassung aller Fehlerarten geeignet und verursacht außerdem relativ hohe Kosten entweder bei der Herstellung speziel­ ler Bausteine mit integrierter Temperaturerfassungseinrichtung oder bei der Monta­ ge von z. B. aufzuklebenden Bausteinen.Such a close spatial coupling according to the second method is indicated when a very small time constant is required to build a power semiconductor element z. B. to be able to switch off selectively or to a short-circuit current and to be able to react quickly to the resulting sudden warming. This However, the method is not fully suitable for recording all types of errors and also causes relatively high costs either in the manufacturing process modules with integrated temperature detection device or at the Monta ge of z. B. building blocks to be glued.

Die Erfindung bezieht sich auf eine Temperaturüberwachung nach der ersten, also indirekten Erfassungsmethode, die beispielsweise geeignet ist, das Versagen eines Kühllüfters in einer leistungselektronischen Anordnung, eine unzulässige Erwär­ mung aufgrund einer Abdeckung von Lüftungsschlitzen eines Gerätes, eine Erhö­ hung der Kühlmitteltemperatur oder eine Überlastsituation zu erkennen. Die für eine solche Oberwachung geforderte Zeitkonstante ist zwar größer als bei einer Kurz­ schlußüberwachung, soll aber trotzdem möglichst klein sein, um Störungen mit nur kurzem Zeitverzug zu erfassen.The invention relates to temperature monitoring after the first, that is indirect detection method, which is suitable, for example, the failure of a Cooling fans in a power electronic arrangement, an impermissible heating mung due to a cover of ventilation slots of a device, an increase the coolant temperature or an overload situation. The one Such monitoring required time constant is greater than in a short final monitoring, but should still be as small as possible to avoid interference with only short time delay.

Zur Durchführung der indirekten Temperaturüberwachung werden in der Praxis oberflächenmontierte temperaturempfindliche Bausteine (SMD-Bauelemente) in lei­ stungselektronischen Anordnungen verwendet. Nachteilig ist jedoch, daß ein sol­ ches SMD-Bauelement nicht mit seiner gesamten Fläche auf der Trägerplatte auf­ liegt, sondern nur über die elektrischen Anschlüsse ein Wärmekontakt zur Träger­ platte besteht. Dadurch sind Fehler bei der Erfassung der Höhe der Temperatur so­ wie relativ große Zeitkonstanten bedingt.In practice, indirect temperature monitoring is carried out surface-mounted temperature-sensitive components (SMD components) in lei Stungselectronic arrangements used. The disadvantage, however, is that a sol ches SMD component with its entire surface on the carrier plate lies, but only via the electrical connections a thermal contact to the carrier plate consists. As a result, errors in the detection of the height of the temperature are so how relatively large time constants.

Der Erfindung liegt die Aufgabe zugrunde, eine Einrichtung zur Durchführung der indirekten Erfassung von Temperaturerhöhungen in Leistungshalbleiteranordnungen anzugeben, die mit geringem Aufwand im Rahmen der üblichen Modulfertigung rea­ lisierbar ist und zu einer ausreichend genauen und schnellen Temperaturerfassung führt.The invention has for its object a device for performing the indirect detection of temperature increases in power semiconductor devices specify that rea with little effort in the usual module production  is measurable and for a sufficiently accurate and fast temperature detection leads.

Diese Aufgabe wird bei einer Einrichtung zur Temperaturüberwachung nach dem Oberbegriff des Anspruchs 1 durch dessen kennzeichnende Merkmale gelöst.This task is carried out in a device for temperature monitoring after Preamble of claim 1 solved by its characterizing features.

Mit der Erfindung wird vorgeschlagen, einen Silizium-Chipwiderstand als tempera­ turabhängiges Bauelement auf der Trägerplatte eines Leistungshalbleitermoduls anzuordnen. Solche Silizium-Chipwiderstände finden bereits als Gate-Vorwiderstand für schaltbare Halbleiterkomponenten in der Modultechnik Anwendung. Silizi­ um-Chipwiderstände tragen auf ihrer oberen und unteren Hauptfläche Metallisie­ rungen, die ein Löten, Kleben oder Drahtbonden im Rahmen der zur Modulherstel­ lung benutzten Technologie ermöglicht. Ein zur Temperaturüberwachung auf einer Trägerplatte anzuordnender Silizium-Chipwiderstand erfordert keinen besonderen Herstellungsschritt, da er zusammen mit den übrigen Halbleiterbauelementen be­ stückt und kontaktiert wird.The invention proposes a silicon chip resistor as tempera door-dependent component on the carrier plate of a power semiconductor module to arrange. Such silicon chip resistors are already used as gate series resistors for switchable semiconductor components in module technology application. Silici UM chip resistors have metallization on their upper and lower main surfaces that require soldering, gluing or wire bonding as part of the module manufacture technology used. One for temperature monitoring on one Silicon chip resistor to be arranged on the carrier plate does not require any special one Manufacturing step, since it be together with the other semiconductor components pieces and is contacted.

Vorteilhaft ist weiterhin, daß es sich beim Silizium-Chipwiderstand um ein sehr ein­ faches und preisgünstiges Siliziumbauelement handelt, dessen Charakteristik, die auch durch einen bestimmten Montageort im Modul beeinflußt wird, auf einfache Weise erfaßbar ist. Die üblicherweise verwendeten komplexen Steuerungen für lei­ stungselektronische Einrichtungen erlauben in der Regel eine Kalibrierung, um den Startwert der Temperatur bzw. die Temperaturabhängigkeit in mehreren Punkten zu erfassen. Der Bezug des Nennwertes zu einer bestimmten Temperatur darf sich deshalb innerhalb eines relativ großen Toleranzfelds bewegen.It is also advantageous that the silicon chip resistor is a very special and inexpensive silicon component, the characteristics of which is also influenced by a specific installation location in the module, on simple Way is detectable. The commonly used complex controls for lei electronic equipment usually allow calibration to the Starting value of the temperature or the temperature dependency in several points capture. The reference of the nominal value to a certain temperature is allowed therefore move within a relatively large tolerance range.

Weitere Einzelheiten zu Anordnungsmöglichkeiten für einen Silizium-Chipwiderstand zur Temperaturüberwachung in einem Leistungshalbleitermodul ergeben sich aus der nachstehenden Beschreibung eines in Fig. 1 gezeigten Ausschnittes einer be­ stimmten Trägerplatte.Further details on possible arrangements for a silicon chip resistor for temperature monitoring in a power semiconductor module result from the following description of a section of a certain carrier plate shown in FIG. 1.

Fig. 1 zeigt eine elektrisch isolierende Trägerplatte 1, z. B. eine Keramikplatte, die auf ihrer oberen Hauptfläche eine zu Leiterbahnen strukturierte leitfähige Schicht 2 trägt, die eine Schaltungskonfiguration bildet. Auf Flächen der Schicht 2 sind Halbleiterbauelemente 3, Silizium-Chipwiderstände 4a, 4b und Anschlußelemente 6 pla­ ziert. Mittels Bonddrähten 5 sind elektrische Verbindungen zwischen Chips 3, 4a, 4b und Flächen der Schicht 2 hergestellt. Fig. 1 shows an electrically insulating carrier plate 1 , for. B. a ceramic plate which carries on its upper main surface a structured to conductive tracks conductive layer 2 , which forms a circuit configuration. On surfaces of layer 2 , semiconductor devices 3 , silicon chip resistors 4 a, 4 b and connection elements 6 are placed . Electrical connections between chips 3 , 4 a, 4 b and surfaces of layer 2 are produced by means of bonding wires 5 .

Im dargestellten Ausführungsbeispiel ist der mit 4b bezeichnete Silizium-Chipwider­ stand als Gate-Vorwiderstand eingesetzt. Der mit 4a bezeichnete Chipwiderstand ist als Temperatursensor potentialfrei auf einer besonderen Teilfläche 2a befestigt und mittels Bonddrähten jeweils mit weiteren potentialfrei angeordneten Teilflächen (Metallisierungsflächen) 2b, 2c verbunden, die jeweils Anschlüsse 6 tragen. Die bei­ den elektrischen Anschlüsse des Temperatursensors 4a sind also auf diese Weise - ohne elektrische Verbindung zu sonstigen Schaltungsteilen - über zwei Anschlüsse 6 aus einem Modul herausgeführt und für eine Auswertung der temperaturabhängi­ gen Widerstandsänderung in einer externen Auswerteeinrichtung verfügbar.In the illustrated embodiment, the 4 b designated silicon chip is cons was used as a gate resistor. The chip resistor denoted by 4 a is attached as a temperature sensor in a potential-free manner on a special partial area 2 a and is connected to further potential-free partial areas (metallization areas) 2 b, 2 c, which each carry connections 6 , by means of bonding wires. The electrical connections of the temperature sensor 4 a are thus in this way - without an electrical connection to other circuit parts - led out of a module via two connections 6 and available for an evaluation of the temperature-dependent change in resistance in an external evaluation device.

Es versteht sich, daß abweichend von der beschriebenen Anordnung auch ein An­ schluß eines Silizium-Chipwiderstands 4a zusammen mit anderen Leistungshalblei­ terbauelementen 3 auf der selben Teilfläche der leitfähigen Schicht 2 montiert sein kann und damit das gleiche Potential, z. B. ein Massepotential aufweisen kann.It goes without saying that, deviating from the arrangement described, a connection to a silicon chip resistor 4 a together with other power semiconductor components 3 can be mounted on the same partial surface of the conductive layer 2 and thus the same potential, for. B. may have a ground potential.

Claims (3)

1. Einrichtung zur Temperaturüberwachung einer Leistungshalbleiteranord­ nung, insbesondere eines Leistungshalbleitermodules mit einer elektrisch isolieren­ den Trägerplatte (1), die Metallisierungsflächen (2) aufweist, auf der zumindest ein Leistungshalbleiterbauelement (3) angeordnet ist, und unter Verwendung eines tem­ peraturabhängigen elektrischen Widerstandbauelements (4a) als Temperatursensor, dadurch gekennzeichnet, daß
  • a) das Widerstandsbauelement ein Silizium-Chipwiderstand (4a) mit Metallisie­ rungen auf seinen oberen und unteren Hauptflächen ist, und
  • b) der Silizium-Chipwiderstand (4a) auf einer Metallisierungsfläche (2, 2a) auf der Trägerplatte (1) befestigt ist.
1. Device for monitoring the temperature of a power semiconductor arrangement, in particular a power semiconductor module with an electrically insulate the carrier plate ( 1 ), which has metallization surfaces ( 2 ) on which at least one power semiconductor component ( 3 ) is arranged, and using a temperature-dependent electrical resistance component ( 4 a) as a temperature sensor, characterized in that
  • a) the resistor component is a silicon chip resistor ( 4 a) with metallizations on its upper and lower main surfaces, and
  • b) the silicon chip resistor ( 4 a) is attached to a metallization surface ( 2 , 2 a) on the carrier plate ( 1 ).
2. Einrichtung zur Temperaturüberwachung nach Anspruch 1, dadurch ge­ kennzeichnet, daß der Silizium-Chipwiderstand potentialfrei auf einer eigenen Me­ tallisierungsfläche (2a) der Trägerplatte (1) angeordnet ist und seine elektrischen Anschlüsse über Bonddrähte (5) und Modulanschlüsse (6) aus einem Leistungshalb­ leitermodul potentialfrei herausgeführt sind.2. Device for temperature monitoring according to claim 1, characterized in that the silicon chip resistor is potential-free on its own Me tallisierungsfläche ( 2 a) of the carrier plate ( 1 ) and its electrical connections via bond wires ( 5 ) and module connections ( 6 ) a power semiconductor module are brought out potential-free. 3. Einrichtung zur Temperaturüberwachung nach Anspruch 1, dadurch ge­ kennzeichnet, daß ein elektrischer Anschluß des Silizium-Chipwiderstands (4a) zu­ sammen mit wenigstens einem weiteren Halbleiterbauelement (3) auf einer Metalli­ sierungsfläche (2) der Leiterplatte (1) montiert ist und damit das selbe Potential auf­ weist.3. A device for temperature monitoring according to claim 1, characterized in that an electrical connection of the silicon chip resistor ( 4 a) is mounted together with at least one further semiconductor component ( 3 ) on a metallization surface ( 2 ) of the printed circuit board ( 1 ) and so that has the same potential.
DE19630902A 1996-08-01 1996-08-01 Device for temperature monitoring in a power electronic device Revoked DE19630902B4 (en)

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FR2776462A1 (en) * 1998-03-19 1999-09-24 Schneider Electric Sa MODULE OF ELECTRONIC POWER COMPONENTS
EP1455391A1 (en) * 2003-03-04 2004-09-08 Semikron Elektronik GmbH Patentabteilung Power semiconductor module with sensor
DE10355333B3 (en) * 2003-11-27 2005-06-30 Infineon Technologies Ag Device and method for detecting overheating of a semiconductor device
DE10024516B4 (en) * 2000-05-18 2006-03-09 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG The power semiconductor module
EP1501125A3 (en) * 2003-07-23 2006-12-06 SEMIKRON Elektronik GmbH & Co. KG Power semiconductor module with scalable structural-design technology
EP2120260A3 (en) * 2008-05-13 2010-07-07 Kabushiki Kaisha Toyota Jidoshokki Semiconductor unit with temperature sensor
US20120201272A1 (en) * 2010-05-20 2012-08-09 Semikron Elektronik Gmbh & Co. Kg Method for Determining the Temperature of a Power Semiconductor
DE102010050315C5 (en) * 2010-11-05 2014-12-04 Danfoss Silicon Power Gmbh Process for the production of sintered electrical assemblies and power semiconductor modules made therewith
DE102013211841A1 (en) * 2013-06-21 2015-01-08 Osram Opto Semiconductors Gmbh Method for determining a temperature of an optoelectronic semiconductor chip and optoelectronic component
CN113053856A (en) * 2019-12-26 2021-06-29 湖南国芯半导体科技有限公司 Method and structure for preventing silicon chip resistor from partial discharge failure and power semiconductor device

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US7988354B2 (en) 2007-12-26 2011-08-02 Infineon Technologies Ag Temperature detection for a semiconductor component
DE102022208171A1 (en) 2022-08-05 2024-02-08 Volkswagen Aktiengesellschaft Arrangement for measuring the temperature of at least one component
DE102022211818A1 (en) 2022-11-09 2024-05-16 Volkswagen Aktiengesellschaft Electronic assembly and method for producing an electronic assembly

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