DE19612676C2 - Arrangement of semiconductor memory cells with two floating gates in a cell array and method for operating a non-volatile semiconductor memory cell - Google Patents

Description

The invention relates to an arrangement of highly integrated, non-volatile semiconductor memory cells, in particular from EPROM or EEPROM cells, with two floating gates and a control gate and an improved method of operation a non-volatile semiconductor memory cell.

In the case of semiconductor memories, the achievable storage density is determined by the structure fineness of the corresponding technology. The cell area of a memory is limited by the grid of word and bit lines in the matrix. If the width and spacing of the word and bit lines are equal to the minimum structural fineness F, the minimum cell area is 4 F ² . A planar digital memory cell with two states contains 1 bit, so that the information density is 1 bit / 4 F ² .

In the case of non-volatile memories, the information is loaded represented on a floating gate. Approaches to Increase of the information density by cells with several logi conditions. To achieve more than two logical states, there are several different operating voltages in the program lubrication process due to different charges on the floating gate set. To achieve 2 bits, for example, there are four Levels necessary. When reading, these must be different Threshold voltage levels are clearly recognized again. The The difficulty of this solution lies in the required ge accuracy with which the load and thereby the resulting Threshold voltage must be set and detected.

In US 5,051,793 is an EPROM cell with a control gate and two floating gates described in a cell array  is arranged. The cell array has bit lines that ver sets are arranged to parallel field oxide islands. The bit line contacts are over in columns in the cell array arranged one another. This publication also describes that the programming of the floating gates by hot Load carriers or tunnel processes can take place and that the Deletion of the programming, for example by UV light Irradiation can take place (column 1, lines 6 to 38).

A semiconductor memory cell with two floating gates is also known from US Pat. No. 5,159,570, which are controlled capacitively via a control gate. The design of a cell field is not specified in this publication. From this publication, if a method for reading the cell is known and explained in FIGS. 3 and 4 and the associated description. In this method, one of the bit lines 36 a or 36 b, which serve as a drain, is first read out and then, depending on the result, a further read operation is carried out, so that a two-stage read process takes place.

No. 5,424,979 also describes how a semiconductor memory cell with two floating gates and one control gate can be read out. It can be seen from FIG. 7 that three logical states "0", "1", "2" can be stored. This is also described in column 17, line 39. Not all four possible states are read out here.

From US 5,427,968 and US 5,494,838 are also half conductor memory cells with two floating gates and one control Gate known. A cell field is described in US Pat. No. 5,284,784, with which T cells can be connected.

The object of the present invention is an improved Arrangement of semiconductor memory cells of the aforementioned Way of creating. In addition, an improved process for Readout of such a semiconductor memory cell can be specified.  

This task is based on US 5,051,793 with the Arrangement of semiconductor memory cells with the features of Claim 1 or starting from US 5,159,570 with the method for operating a semiconductor memory cell with the Features of claim 2 solved.

The semiconductor memory cell behaves through the fiction moderate arrangement like a series connection of three transistors, the control gate acting as the gate of a selection transistor and is directly controlled and the two floating gates as Ga tes of two memory transistors act. The floating gates are galvanically isolated and capacitively controlled by the gate voltage. The cell can be made by applying negative and / or positive Loads on the floating gates and the associated lifting and / or lowering the threshold voltage of the respective transistor be programmed. With two floating gates per cell there are four States and thus 2 bit reachable.

The floating gates are individually programmable, so that on each individual either no charge applied or a negative or a positive charge can be applied. You bring it for example only negative charges, so you can choose between the state with no charge and with negative charge below divorce. With two floating gates, there are four states and thus 2 bit. The possibility is also conceivable that one at the states positive charge, no charge for each floating gate and can distinguish negative charge. With two floating gates this gives nine states per cell, which represent 3 bits are adjustable.

When designing such a memory cell, each floating Gate preferably assigned a drain area and a common one Source area available for the floating gates. The floating Gates are preferred by the control gate by a thin one Dielectric separated. This can be nitride, for example. Also  an oxidation of the relevant positions to form a insulating oxide layer is possible. Likewise, a station wagon nation made of thermal oxide and deposited dielectric such as for example ON, or ONO can be used. This is preferred the oxide used nitrides, (in NO or NH3).

The semiconductor memory cells are preferably arranged in a cell field with an asymmetrical arrangement. This means that one connection of the cells is carried out together. This can be used, for example, to create a common source connection. In another preferred embodiment, the cell array is arranged symmetrically. This means the formation of a virtual ground. In both cases, cell areas of about 5-6 F ^{2 are} reached. With 2 bits per cell, this results in an information density of 1 bit / 3 F ² to 1 bit / 2.5 F ² .

An explanation of the above-mentioned semiconductor memory cells, and cell arrays on the basis of Fig. 1, 2, 3a, 3b and 3c, and a more detailed description of examples of the OF INVENTION to the invention the arrangement and method according to the invention with reference to FIGS. 4a, 4b, 4c and 5 In detail, the schematic representations show in:

Fig. 1 shows a cross section through a double-floating gate cell;

Fig. 2 is an equivalent circuit diagram of a dual floating gate cell;

FIG. 3a shows a layout of an asymmetric cell array;

Figure 3b shows a section along the line AA in from FIG. 3a.

FIG. 3c is a section along the line BB of Fig. 3a;

FIG. 4a is a layout of a symmetrical cell array;

FIG. 4b shows a section along the line AA of Fig. 4a;

Fig. 4c shows a section along the line BB of Fig. 4a;

Fig. 5 is a schematic cell characteristics in the various states.

In Fig. 1, a cross section is shown by a double-floating gate cell. The control gate 3 consists of polysilicon and is contacted directly with the gate connection. The floating gates 1 and 2 lie in the same plane as the control gate 3 and are separated from the side regions of the control gate 3 by a thin dielectric 4 . A first gate oxide 18 is arranged below the floating gates 1 and 2 and a second gate oxide 5 is arranged above the substrate 6 below the control gate 3 . The gate oxide 5 below the control gate 3 forms together with the sem a MOS transistor. The gate oxide 18 among the floating gates 1 and 2 is usually somewhat thinner than the gate oxide 5 underneath the control gate 3 , because it must be so thin that a tunneling process between the floating gates and the drain areas below it must be possible. Each floating gate is assigned a drain region 7 and 8 , which are each contacted with a drain connection 9 and 10 .

In FIG. 2, the memory cell is shown as an equivalent circuit. The memory cell behaves like a series connection of three transistors. The selection transistor TC is net arranged in the middle. The gate of the selection transistor is formed by the control gate and driven directly. The two memory transistors TF1 and TF2 are on both sides of the selection transistor TC. Their gates are formed by floating gates 1 and 2 and are galvanically isolated and capacitively controlled by the gate voltage. The cell can be programmed by applying negative / positive charge to the floating gates and thus raising / lowering the threshold voltage of the respective transistor. With two floating gates per cell, four states can be distinguished:

Table 1

In states 1 and 4, the cell behaves symmetrically. to A gate voltage that is greater than that is necessary for the evaluation lower threshold voltage of the memory transistors or the off either transistor. States 2 and 3 can be evaluated can be distinguished with swapped source and drain. It must however, the gate voltage may be greater than the highest possible on Set voltage of the memory transistors. To program the Various methods are conceivable for the memory cell. example the cells can be wisely removed from the Program the channel. This programming is comparable to that of EPROM cells.

One of the two is for programming states 2 or 3 following voltage conditions required. For condition 4 both programs must be carried out one after the other:

Table 2

The voltages Vdd and Vpp required for programming hang on the geometry and layer thicknesses of the memory cell. Vdd can for example +7 V and Vpp +12 V. The cells can either as OTP memory (once programmable memory) be set or deleted and reprogrammed become. Extinguishing is by irradiation with UV light or by on negative gate voltage possible.

Table 3

The cells are discharged by Fowler-Nordheim-Tun between floating gate and associated drain area. The Voltages Vdd and Vnn depend essentially on the geometry and on the layer thicknesses of the memory cell. The voltage dif reference between the floating gate and the respective drain area must be sufficient to generate a tunnel current. Possible Values for Vdd and Vnn are +5 V and -12 V.

Similar to an EEPROM cell, the semiconductor memory cell can also be deleted and programmed by Fowler-Nordheim tunnels.

Table 4

Examples of voltages are Vdd = +5 V, Vpp = +18 V and Vnn = -12 V.  

Due to the different behavior of the cell, which is shown in Fig. 5, a distinction between the states shown in Table 1 is possible. The cell can have four states and thus store 2 bits. In Fig. 5, the current strength as a function of the voltage (on the X axis) is shown on the Y axis. In the states 1 and 4 shown in FIG. 5, the cell behaves symmetrically. In states 2 and 3, the cell behavior depends on the wiring. In particular, check whether VD1 is <or <than VD2. VD1 is the voltage at location D1, which is provided with reference number 9 in FIG. 1. D2 is designated by 10 in FIG. 1. To differentiate the states 2, 3 and 4, the measurement of the cell can be used in two circuits:

VD1 <VD2: D2 = Source, D1 = Drain; Example: VD2 = 0 V VD1 = +1 V

VD1 <VD2: D1 = Source, D2 = Drain; Example: VD1 = 0 V VD2 = +1 V

The course of an evaluation can look like this, for example:
In a first step A, the gate voltage (see reference numeral 11 in FIG. 1) is set to the value VG1, VG1 being between the low threshold voltage and the high threshold voltage of the memory transistors. If a current flows, the cell is in state 1 (see also Table 1 and Fig. 5). In this first step it is irrelevant whether VD1 <or <is VD2.

In step B, the voltage at drain region 1 (see reference number 9 in FIG. 1) is selected to be greater than the voltage at drain region 2 (see reference number 10 in FIG. 1) and the gate voltage is set to the value VG2 (see FIG. 5) , It is essential that VG2 is greater than the highest possible threshold voltage of the memory transistors. The cell now delivers a current I _B.

In step C, the wiring of the cell is changed so that VD1 <VD2. The gate voltage remains at VG2. The cell now supplies a current I _C. Finally, the current I _B must be compared with the current I _C. If I _B <than I _C , the cell is in state 2, if I _B <I _C , the cell is in state 3 and in the case I _B = I _C , the cell is in state 4.

In short, this means:

Step A: VD1 <VD2 or VD1 <VD2
VG = VG1 (<Vt L, <Vt H)
if current flows: state 1

Step B: VD1 <VD2
VG = VG2 (<VtH)
the cell supplies current I _B

Step C: VD1 <VD2
VG = VG2 (<Vt H)
the cell supplies current I _C
I _B <I _C : state 2
I _B = I _C : state 4
I _B <I _C : state 3

The manufacture of a memory cell according to FIG. 1 is described below by way of example. The process flow corresponds to that of a CMOS standard process until after the gate has been structured. The gate oxide under the floating gate can be, for example, 40 nm and the polysilicon of the control gate can be 400 nm thick. The substrate is then etched free. This can be done for example by wet etching with HF. The substrate and sidewalls of the control gate polysilicon are simultaneously oxidized to form gate oxide under the floating gates and to form oxides between the control gate and the floating gates. The oxide thickness under the floating gate is typically between 10 and 20 nm. A low oxide thickness will be chosen if Fowler-Nordheim tunnels are provided for programming and erasing the semiconductor memory cell, while a thicker oxide for programming with hot Charge carriers and possibly deletion with UV light is provided. The thickness of the oxide between the control gate and the floating gate is made about a factor 2 to 3 larger than under the floating gate by the doping of the control gate. Instead of thermal oxidation, a dielectric can also be deposited at this point, or a combination of thermal oxide and deposited dielectric can be used. About 150 nm thick polysilicon layer is deposited and n ⁺ -doped. This can be done, for example, by occupying the gas phase. POCl ₃ is preferably used here at 900 ° in order to achieve phosphor coating. The polysilicon is then anisotropically etched back to produce poly spacers on the side wall of the control gate. The poly-spacers present between adjacent cells and on logic transistors and any undesired dielectrics, such as the previously deposited nitride, are removed with a paint mask. Either an isotropic wet etching or a dry etching with a high selectivity from silicon to oxide can be used here. The further process control for the generation of source and drain regions and the metallization proceed as in a standard CMOS process.

To process the high compared to the operating voltage To enable programming voltages are under different well areas and gate oxide thicknesses for logic and HV-compatible MOS transistors necessary.

In Fig. 3 the structure of an asymmetrical cell array is Darge presents. The word lines 12 are used to contact the control gate. The dashed lines on the side of the interpreted bit lines 13 run perpendicular to this. The bit line contacts 14 are indicated by crosses. The field oxide islands 15 serve for isolation. The floating gate spacers 16 are indicated by dashes and separate the control gate from the floating gates. Outside the field oxide islands 15 , the common source terminal 17 is hen vorgese. The field oxide islands 15 are generated by a LOCOS process. The control gates of the cells one above the other in a column are connected via continuous word lines 12 . A respective first source / drain region of adjacent rows is contacted together and the source / drain regions of a row of cells are connected via a common bit line. The second source / drain regions of opposing cells who are connected to each other via a common diffusion line and form a common connection. Each cell can be selectively selected via a word and a bit line. In Figs. 3b and 3c sections through the Fig. 3a. In particular in Fig. 3b it is clear how the bit lines 13 with the bit line contacts 14 are connected to the control gates 3 . A section along a word line 12 is shown in FIG. 3c. It is also clear here that the bit lines 12 always run exactly in the gap between two field oxide islands 15 .

In Fig. 4 the symmetrical structure of a cell array is Darge presents. Here, too, the word lines 12 serve to connect the gate, that is to say to connect the control gate. The bit lines 13 are perpendicular clauses in this structure between the Feldoxidin 15 contacted so that the bit line contacts 14 are always in the space between two field oxide 15th Likewise, the floating gate spacers 16 and the floating gates lie outside the region of the field oxide islands 15 . The control gates of the cells one above the other in a column are also connected here by continuous word lines 12 . Here, the source / drain regions of four neighboring cells from two adjacent rows are connected. The nodes lying in a row are connected to a common bit line 13 . A cell is selected by choosing two adjacent bit lines and one word line. In Figs. 4b and 4c-sections are shown along the lines AA and BB. In Fig. 4b of the section is represented by a row of cells. The section in FIG. 4c runs parallel to it, but through the field oxide islands 15 , over which the bit lines 13 with the bit line contacts 14 are provided for connecting the source / drain regions. The field oxide islands are therefore not continuous, but are interrupted to enable the connection to the source / drain regions to be carried out.

Both in the asymmetrical structure of the cell field and in the symmetrical structure of the cell field, cell areas of about 5-6 F ^{2 are} achieved. With 2 bits per cell, this results in an information density of 1 bit / 3 F ² to 1 bit / 2.5 F ² .

Claims (5)

1. arrangement of semiconductor memory cells in a cell field,
with highly integrated, non-volatile semiconductor memory cells with two floating gates ( 1 , 2 ) and a control gate ( 3 ) and both floating gates ( 1 , 2 ) capacitively shared by the control gate ( 3 ) are controlled
the control gates ( 3 ) being connected in columns with continuous word lines ( 12 ) and the source / drain regions being connected in rows by bit lines ( 13 ) and field oxide islands ( 15 ) and bit line contacts ( 14 ) being provided,
characterized by
that the bit lines ( 13 ) are arranged above the field oxide islands ( 15 ), the field oxide islands ( 15 ) having openings for the passage of the bit line contacts ( 14 ) and
that the bit line contacts ( 14 ) are arranged offset from one another in columns. 2. Method for operating a highly integrated, non-volatile semiconductor memory cell with two floating gates ( 1 , 2 ) and a control gate ( 3 ), the two floating gates ( 1 , 2 ) being capacitively shared by the control gate ( 3 ) controlled who, where
the floating gates ( 1 , 2 ) are read out by applying different voltage states and multiple evaluation, so that four states can be distinguished,
characterized,
that in a first step the gate voltage is set to a value which lies between the possible operational voltages of the memory transistors,
that a current of the cell is measured and
that the process terminates if current flows,
that if no current is measured in the first step, a gate voltage is set in a second step, which is greater than the greatest possible threshold voltage of the memory transistors, and the voltage on a first drain is set higher than the voltage on a second drain region,
that in a third step the gate voltage is further set such that it is greater than the greatest possible threshold voltage of the memory transistors, and the voltage in the first drain region is chosen to be smaller than the voltage in the second drain region; and
that in the second and third step the current of the cell is measured and this is evaluated. 3. Arrangement of semiconductor memory cells according to claim 1, characterized in that the floating gates ( 1 , 2 ) are individually programmable. 4. Arrangement of semiconductor memory cells according to claim 1 or 3, characterized in
that each floating gate ( 1 , 2 ) is assigned a drain area and
that the floating gates ( 1 , 2 ) are assigned a common source region. 5. Arrangement of semiconductor memory cells according to claim 1, 3 or 4, characterized in that the floating gates ( 1 , 2 ) are arranged laterally from the control gate ( 3 ).