DE1938912C - Arithmetic and logical unit with error checking - Google Patents

Description

(A _n -B _n ) V (A _n -C _n -,) ν (B _n -C..0
and a sum function according to the relationship

(A _n ν B _n νC._.) -Ίϊνίν C ^)

form, where A _n and B _{n are} the operand bits of the respective position and C _n ^ _{1 is} an incoming carry in this position.

6. Arithmetic and logical unit according to Claims 4 and 5, characterized in that that the carry generator (20) the carry from more than one neighboring lower Place this together with the OR functions from the logic gating circuits (18) Receives places supplied and that the carry generator is designed. dall he did the transfer after the relationship

C _n = A _n B _n ν (A "vB _n ) -C _n ^ ₁

viA ... vB _n - _x ) (A _n vB _n ) C _n . ₂ V (A _n . ₂ vB "- ₂ ) {A" - _i ν B _n -i) (A _n νB _n ) -C _n . _s forms.

The invention relates to an arithmetic and logic unit "for carrying out the operations "Addition". »And«, »Or«, »Exclusive-Or <> with Transfer-dependent summation for the purpose

the error check of the carry and sum bits through parity preview with exclusive-or-link the operand parities as well as the carry parity and by comparing the predicted with the actual result parity.

It is known in adding units to check the sum to be formed for possible errors a test circuit the parity, i.e. the odd number or the even number of the sum, to be determined beforehand and compared with the actual parity of the sum formed. The predestination is done by changing the parity of the operands and the parity of the during summation processed transfers can be combined by an exclusive-OR link. This me-

method is disadvantageous insofar as in the known adding units an individual error is always the same Number of errors in the generated carry and sum bits. Due to the incorrect transfers become incorrect

Sum parity predicted. However, since the sum, which is also falsified, delivers an equally incorrect parity value, the presence of an error can no longer be determined.
Adding units have already become known

ι »(United States Patent 3,234,373). which this disadvantage thereby avoid the buzz? is generated depending on the carry. So if for example if a faulty transfer is generated in one of the adding stations, there is not only a falsification the total number of the next higher position and possibly the carry-over and the total number the next but one position, which has the same number of errors in the carry bits and in the sum bits

but the sum will also be erroneous at the point where the erroneous transfer occurs originated. The equal number wedge is therefore the error in the carry bits and in the sum bits disturbed, and the error is by comparing the actual result parity with the predicted Result parity recognizable.

The known adder is only suitable for performing arithmetic operations. In data processing systems, however, it is often necessary that the arithmetic unit not only arithmetic, but also various logical links between the operations, such as and, or, exclusive-or for which a result check is also desired. .,

It is the object of the present invention. to tackle a combined arithmetic and logical unit, in which the previously explained principle of error checking for both arithmetic and for logical combination operations of the operands can be used. In accordance with the invention, this is how achieves that a function generator circuit is provided. which are dependent on operation control signals for the logical operations "AND" and "OR" one related to the respective operation 2 "; The pulled parity function is generated, namely the OR function for the AND operation and the AND function for the OR operation. and that a test circuit is provided. that by means of an exclusive-or link the operand parity with the parity function regardless of the result of the execution logical operation whose parity forms, which then compares the parity with the actual Is subject to long-term results

The arithmetic and logic unit of the invention has the ^v orteil. that through education before. separate pa itity functions in the logical combination of the operands, an error check of the result can be carried out in the same way and at least partially also with the same circuits as the error check of the arithmetic results.

The same circuit is also for the exclusive-or operation usable for parity comparison, although here an additional parity function. not is produced. The latter is not necessary for the exclusive-or operation because it is logical Exclusive-OR operation of the operand bits none odd-numbered change in the number of significant bits and therefore no parity reversal can be done. It is therefore sufficient for the error check if the result is an exclusive-or link the operand parity is fed to the comparison with the actual result parity.

Further advantageous refinements of the invention can be seen from the claims. Below an exemplary embodiment of the invention is explained with reference to drawings. It shows

F i g. 1 is a block diagram of a known adding unit with transfer-dependent summation,

F i g. 2 is a simplified block diagram of one point of the arithmetic and logic functions, for example Unit,

F i g. 3 is a detailed block diagram of a location in the arithmetic and logic unit according to FIG Fig. 2,

F i g. 4 a simplified block diagram of the complete arithmetic and logic unit and F i g. 5 shows a test circuit as used in connection with the arrangement according to FIG. 4 can be used.

In Fig. 1, a known adder is shown, which makes use of the principle of summation as a function of the transfer. This adder consists of a carry generator 10, a summation function generator 12 and an exclusive-OR circuit 14. Assuming that the adder is designed as a binary full adder for a binary digit, the carry generator 10 generates from the binary operands A and B of the digit? i and the carry C from the next lower digit! the transfer C _n . For this purpose, the carry generator consists of a logical network which, in accordance with the Boolean relationship C _n = (A _n ■ B _n ) + (A _n ■ _{C._ t} ) + (B _n

is constructed.

Herein means that every log ^ .he multiplication in the carry generator 10 in a known manner by a known AND circuit and each logical Addition is embodied by an OR circuit.

The sum function generator 12 forms the same input signals A _n . B ", C _n _, a sum function SF _n . The Boolean expression for the sum function SF _n is as follows:

SF _n = M ₁

The sum function SF _n is fed together with the carry C _{n to} the exclusive-OR circuit 14, which supplies _{the binary sum S n at its output.}

Such an adder structure has the advantage that individual errors can be recognized with a relatively high degree of certainty. The error check with adders is mostly done by predicting the parity of the sum. Parity is understood here to mean the binary value that is necessary. to convert the checksum of all bits of a value to an odd or>. to add an even binary value. Everyone numbers. which is fed to the arithmetic unit is therefore provided with an additional bit that serves as a parity indicator. The relevant numerical value can be checked for correctness by recreating its parity and comparing the result with the parity bit carried along. The same scheme is used to check the result of a binary addition. Independently of the sum formation, the sum _{parity P x} i is predicted by an exclusive-or link of the parity of the operands and the processed carries.

This happens after the relationship

Pg = PaVPbV-Pc,

where P _{4 is} the parity of operand A. P _{B is} the parity of operand B and P _{c is} the parity of the carries processed during the addition. At the end of the addition, the parity of the sum formed is determined and compared with the previously determined parity for a match.

This test procedure only works successfully if an error occurs in the transfers or in the total. However, if an equal number of errors appear both in the processed carries and in the sum bits, the predicted sum parity P _s agrees with the actual sum parity, although the

Sum is incorrect. By the adder of FIG. 1, this deficiency is counteracted in that the sum bit is formed in each position in the manner explained depending on the transfer generated in this position. If this 5 carry is incorrect, then not only the sum bit of the next higher bit position is corrupted. In addition, a wrong sum bit is also formed in the relevant position, so that a wrong ~ "'' ** '- ■ --— --..-; r ^ icrhd nit« in the 10

the

same

are present if, as a result, the operation to be carried out is not an AND link and also not an exclusive OR link. If signals appear on lines 44 and 48, the arithmetic and logic unit is in a state in which it combines the operand signals A _n , B _n appearing on the input lines 50, 52 according to the logical operation "OR". The signal on line 44 blocks the transfer generator circuit 20 and the signal on line 46 blocks the sum function generator circuit 22. The OR result is formed in that a bit function representing the OR operation of the operands is transferred from line 28 under the effect of the control

_the

bit of the place that the. ^ , rag has generated ^ J Ungtachhei

Number of ^^^^ Τ ^ Λά wrong sum bits. so dall d

^dC _D r _e ^ar ^ S "ah AusXungsbeispiel der uie π g. <-« β arithih d

Invention of »a« ™ logical unit where the sum ^

Ä Ä Ά £ edätrfe AoToUe

Tue _2Q

also on logical
anthmeusche and

rfe to expand the

contains
contains

Unit one

a Auswlhltorschaltung 26, which more than collecting a ^Sel * ^niIo ^ ^d '.j "| _i4fu: supplied _{ACTIONS of BF.}

STcS S ⁿ dimensioning rZräund the totals. The ° ^ f " ^ra ^ ^ge "! " _Men transfer C

UIlU IUgUViIk. i ^ u ....... ".".

The carry C _n is transmitted on the one hand via a line 32 to the next higher digit position and on the other hand via a line 34 to an exclusive-OR circuit 36, the second input of which is connected to the output of the summation function generator 22. The exclusive-or circuit 36 delivers

~ "~" ng a goodbye Or-OR circuit 38 is transmitted to output line 40. In the corresponding manner if present a control signal on lines 42 and 48 and in the absence of a control signal on lines 44 and 46 the selection gate circuit 26 is controlled for the passage of a Bufunktiop "AND". The Exclusive-Or-Ope- and 25 ration is performed when control signals are on abut over lines 46 and 44. The exclusive-or link of the operands takes place in the sum function generator 22, which arbciici. a 30 By the control signal on line 44, the carry generator 20 is blocked, so that when the Processing of the operand bits, no carry occurs on line 32. The result of the sum fun Action generator circuit 22 is via the exclusive-or circuit 36 and the OR circuit 38 to the output line 40.

The parity function generator 24 generates when performing logical combination operations of the bit functions BF _{n is} a parity function PF _n, which is used to check the result of the link. This is done in such a way that the parity of the operands and the parity function PF _n are linked by exclusive-or. The result of this link corresponds to the parity of the re-

will.

sulfates of the logical combination operation to be carried out. A comparison between the parity of the logical result appearing on line 40 and the result obtained using the parity

^ uf SafSkSmetische and l _{OgL cal} in ckr bSpecific binary digits with Durch-LiiST logical operanons föhdOt * "SÄ- ^ m _r ^ ^ _mm , *** _T

The parity function PF _n required in each case is carried out by the control signals on lines 42 and 44. For the operation «» OR., ₅₅ which is indicated by a signal on lines 44 and 48 and by the absence of a signal on soldering lines 42 and 46, the pantätsfunktionsgenerator delivers on its output line 56 the AND operation exclusive deT input signals A _n , B _r for the and function. ai SS eS S ^ af »» AND 6o which is indicated by em sgTal on lines 42 and 48 and by AND-connec- tion oSr erne Ex- absence of a signal on lines 44 and 46 unu c » γ * J [A Leituneen delivers the Parity generator circuit on Leip _o ^ glue ^ _s ^ or-linking the

44 and 48 join J ^ s conge »!« To «n ^ ^ below table

i ££: Si ·, wW the bS ^ of the parity functions when predicting the result parity for the operations

^ ηΓ ^^ OR and AND clearly in the TabÄeujet

on line 44 the display K supplies the kesunate. P "the parity of the correct result"

t ^! ί! taSdnmi 42.44. 46 If a signal »» ADD ν EO «occurs on Him Sv & amd * and logical iunri uic« u exclusive

fct *

938 912

(Complement to odd) and VP _R the predicted parity.

Table 1

Λ B. P. A f- P _n Λ (- PF = 1 H Pr OR 1 I. 0 1 0 0 0 1 0 1 1 1 0 0 1 0 I. 0 0 0 0 0 1 0 0 0 1 0 1 I. 1 0 AND I. 1 0 1 0 1 0 I. 0 1 I. I. 1 1 0 1 I. 0 0 0 I. 0 0 1 0 0 1 0 1 1 0

The carry generator circuit 20 in FIG. 2 differs from the carry generator 10 of the adder according to FIG. 1 designed in such a way that not only the transfer from the next lower value place is taken into account when the transfer is formed, but also transfers from other lower places. For this purpose, the circuit 20 is connected via the lines 58, 59 to carry outputs and to bit function outputs, such as the output line 61 of the point η . Deviating from the "arrangement shown", the operand bits can also be fed directly to the units 20, 22, 24 or 26. The arrangement can be such that the signals C _n , SF _n and LS _n using part of the bit functions BF _n and the operand signals A _n , B _{x are} formed.

The detailed structure of a substantially similar arrangement in FIG. 2 corresponding circuit is from the block diagram of FIG. 3 can be seen. In the bit function generator 18, the AND function is formed from the operand bits A, B _n by an AND circuit 60 on a line 64 and the OR function is formed by an OR circuit 62 on a line 66. The line 64 leads to an AND circuit 68 in the parity function generator 24. The second input of this AND circuit is connected to the output of an inverter 72 which is connected to a control line 70 on which the control signal "AND ν EO" occurs. The AND circuit 68 is thus prepared for a signal transmission in the absence of this signal. The output of the AND circuit 68 is connected to the output line 76 via an OR circuit 74. Likewise, the OR function of the operand bits is transmitted from the OR circuit 62 via the line 66, an AND circuit 78 and the OR circuit 74 to the output line 76 when a control signal is present on the line 70 to prepare the AND circuit 78 . The bit function lines 64 and 66 also lead to the transfer generator circuit 20, which consists of AND circuits 80, 82 and 86 and an OR circuit 88. The carry generator circuit 20 forms the carry, according to the relationship

C. = 4.-B. ν M ,, vflj C _n ,

V (A _n ^ ₂ vB "_ ₂ ) -M" -, vB._, »M ₁ , vß.l C., where in C _n -" C._2 and C. 3 the carryovers from the next lower, from the two places lower and the three places lower of the arithmetic and logical unit and in which, accordingly

»/!" _, Vß "_," and "A _n _ ₂ vfl". ₂ «

are the OR-bit functions from the next lower digit and from the digit lower by two digits. The AND circuit S2 forms the part of the above expression in the second line and the AND circuit 86 the part of this expression in the third line, while the AND circuits 80 and 84 form the two ANDs of the first line of the above expression. The OR function of the relevant point η becomes the AND circuit 84 as well as the AND circuits 82 and 86 from the bit function line 66 supplied. The outputs of the AND circuits 80, 82, 84 and 86 are connected to an OR circuit 88, the output of which is connected to a carry output line 90 is connected. The AND circuits 80, 82, 84 and 86 each have an additional Input that is connected to the output line 92 of the inverter 72 and through which the Carry out generator circuit 20 is disabled when a control signal on line 70 is present.

The bit function lines 64 and 66 are also

3c connected to the buzzer function generator 22, which is the sum function SF, according to the relationship

SF _n = (A _n ■ B _n ν C _n Z ₁ ) ■ (A _n ν B _n ν C ₁₁ ..,)

forms. The component A _n · W _n ν C "_" is derived from the AND bit function of line 64 through an inverter 94 and from the transfer from the next lowest point on a line 96 via an AND circuit 98 and an inverter 100 educated. On

the outputs of the inverters 94 and 100 is connected to an OR circuit 102, the output of which is connected to a AND circuit 104 leads. To form the component in the right part of the above expression becomes the or-bit function of line 66 and that

The output signal of the AND circuit 98 is fed to an OR circuit 106, the output of which is connected to the second input of the Uid circuit 104. at the output of which the sum function SF _n occurs. The second input of the AND circuit 98 is with

the line 92 connected, so that the transfer from the next lowest point on line 96 to the Summennmktionsgeneiatoi 22 only then fed is when there is no control signal "AND ν EO" on line 70.

The sum function signal SF _n is transmitted via an AND circuit 108 to the exclusive-OR circuit 36 if the ADD ν EO control signal is present on a line 110. The same control signal also prepares an AND circuit 112 for

a transmission of the output signal from the transmission generator circuit 20 to the second input of the exclusive-OR switching 36. In the Exclusive-Or-Schalturg36 the generated transfer C _n and the sum function SF _{K is described} in the

Linking way ;. The output of this circuit is connected to the resultant output line 114 via du, - or circuit 38.
At two further inputs of the OR circuit 38

the outputs of AND circuits 116 and 118 are connected which are one of the select gate circuits 26 of FIG. 2 form corresponding unit 26 '. Notwithstanding FIG. 2, the circuit 26 'receives both the operand bits A _n , B _n and some of the bit functions from the bit function generator 18, namely the OR function. Both AND circuits 116, 118 are made effective via an inverter 120 only when no signal is present on control line 110. The AND circuit 116 is also controlled by the output of the inverter 72 via the line 92. This AND circuit is used to transfer the OR bit function to the result output 114 if none of the lines 70 and HO are signal-affecting. , Is transferred _5-bit function of the And line 64 to the output result 114, only when the line 110 is not a leader signal via the AND circuit 118th At this point in time, the AND circuit 116 is blocked for signal transmission due to the absence of a signal on line 92.

The F i g. 4 shows how several stages from the one in FIG. 3 are interconnected to form a complete arithmetic and logical unit 130. Each of the blocks 132 is represented by a circuit as shown in FIG. 3 formed. The inputs and outputs of the blocks carry the ones shown in FIG. 3 designation used. The individual places of the unit 130 are denoted by 1 to η , where 1 means the lowest place and π the highest place. In position 1 are the inputs for the signals C. .., _Q C "-2, C._ ₃ , / I _n -, vß,." / L, _j vB "_ ₂ (lines 96, 122. 124, 126, 128 in Fig. 3) is applied via a line 134 to a fixed bias voltage VSP, the voltage value of which generates 0 input signals on the inputs mentioned. In the same way, the input lines 122, 124, 128 (Fig 3) appropriate lines are connected to the bias line 134. The same applies to the CVj input line 124 of position 3.

The output lines of the blocks 132 for the result digits R ₁ to R _n , for the carries C 1 to C _n and for the parity functions PF _x to PF _n are connected to a test logic 140 which is part of the arithmetic and logic unit 130. In addition, the result signals R ₁ to R _n are forwarded via lines 136 to downstream units of the data processing system in which the arithmetic and logic unit is used. A block diagram of the test logic is shown in FIG. 5. A first exclusive-OR circuit 142 is used to link the result signals R to R of the arithmetic and logic unit 130. The circuit 142 can be in one of FIGS. 6, as can be seen, consist of several exclusive-or elements 146 connected in series. An inverter 144 is connected to the output of the circuit 142 , at the output of which the parity P ₈ of the result generated by the arithmetic and logic unit 130 occurs. The test logic 140 includes two further exclusive-or circuits 148 and ISO. both of which are constructed in the same way as circuit 142. In the exclusive-OR circuit, the carries C ₀ , C, to C «_ ,, from the positions 1 to η - 1 of the unit! 130 are generated during an addition, linked by exclusive OR. The output of this circuit leads to an AND circuit 152, the second input of which is connected to a control line 154 on the

Addition control signal »ADD« appears when an addition is carried out.

The exclusive-OR circuit 150 is used in a corresponding manner for the exclusive-OR operation of the parity functions PF to PF _n , which are generated in positions 1 to η of the unit 130 when a logical operation is carried out, via an AND circuit 156 If a control signal “AND ν OR” is present, the output signal of circuit 150 is transmitted on a line 158 to an OR circuit 160, the second input of which is connected to the output of AND circuit 152.

A single-digit exclusive-OR circuit 162 receives the parity display signal P _{A of} the operand A on one input 164 and the inverted parity display signal P _{B of} the op-margin B on the other input 166. The output of the exclusive-OR circuit 162 is connected to a further exclusive-OR circuit 168, the second input of which is connected to the output of the OR circuit 160. The output of the exclusive-OR circuit 168 leads to a comparator 170. The second input of this comparator is connected to the inverter 144 via a line 172. In the example shown, an exclusive-OR circuit can be used as the comparator 170. It has an output line 174 on which an error display signal F appears in the event of an incorrect operation of the arithmetic and logic unit 130.

7. For explanation of the working method of the arithmetic and logic unit 130, reference is made to Table II below. In this table is the parity check for the operations addition, or, and, exclusive-or on the basis of single digits Operand links are shown. The parity in the table is a supplement to an odd number Based on binary value. Incorrect binary values are marked with *.

Table II

A. B. _c R. 1 iV f-CI ? F = 1 F. addition 0 0 0 0 0 Ö 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 * 0 1 1 0 1* 1 1 0 0 1 0 0 I. 1 0 0 I. 1 0 1 0 1 0 I. 0 1 1 0 0 1 1 0 0 ί 1 0 0 1 1 1 1 1 1 I. 1 0 OR 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1* 0 0 1 0 * 0 1 0 0 1 1 1 1 1 1 1 1 0 AND 0 0 0 0 0 0 1 0 1 0 0 1 0 i 1 0 0 1 0 0 1 1 0 C. I. 1 1 1 I. 1 1 C. Exclusive 0 θ 0 0 0 0 C. or 1 0 1 I. 0 0 C. 0 1 1 0 1 i ( 1 1 0 1 C.

As an example, consider the OR operation of the operands A - 0, B - 1. It is assumed that due to a disturbance, e.g. B. by failure of a transistor, in the circuit of one of the points 1 to η in the unit 130, the incorrect result signal 0 is formed. If the other points are excluded from consideration, the exclusive-OR circuit 142 generates a binary 0 at its output, so that the inverter 144 supplies a binary 1 as a P ^ signal. As can be seen from the table, the exclusive-OR circuit 162 also generates a 0 output signal, since a 1 signal is present at both of its inputs 164 and 166. Furthermore, a 0 signal is present on the line ⁷ 6 of the relevant point as a parity function P _F. The exclusive-OR circuit 150 _{thus does not generate an output signal t5} , so that the ^{AND circuit i56 prepared by a 1-} OR control signal on line 158 remains ineffective. The exclusive-OR circuit 168 does not receive a signal on either of its two inputs. The comparator 170 therefore only receives a 1 signal on line 172, which is why an error display appears on its output line 174.

As a further example, consider the addition of the operands A = 1 and B = 1, assuming that there is no transfer from the next lower digit. A lack ^r exemplary sum bit 1 in turn leads to a distortion of the result parity JF ^., Which then assumes the value 0. The exclusive-or circuit 162 (FIG. 5) provides an output signal since the parity of operand A is zero and the inverted parity of operand B is one. Since there is no carry, the output of the exclusive-or circuit 148 is zero. The AND circuit 152 prepared on the basis of an addition control signal on line 154 thus does not transmit a signal to the OR circuit 160. The exclusive OR circuit 168 therefore only receives an input signal and outputs an output signal to the comparator 170. Since the line 172 is not signal-affecting because of the output signal of the exclusive-OR circuit 142, the comparator 170 supplies an error display signal.

From these examples it can be seen that in the same way for arithmetic * and logical operations the parity of the result signal generated is checked against a parity display generated independently of the result formation and, in the event of an incorrect result, leads to an error display. Since the test extends to all points of the unit 130, individual errors are displayed regardless of the point in which they occur. In addition, an indication of errors is also obtained which are caused by faulty control signals on lines 70, 92 or 110 (FIG. 3) or due to a break in these lines. For example, an output signal R generated by a break in the line 92 at the input of the circuit 26 'can be an or. AND operation can be determined in the test logic, since the correct parity function Pf ensures an inequality between the actual result parity pR and the predicted result parity Pa -V- P _b * PF.

For this purpose 2 sheets of drawings

Claims (5)

Patent claims: 1. Arithmetic and logical unit for performing the addition operations. And or. Exclusive-Or with carry-over-dependent summation for the purpose of checking the error of carry-over and sum bits through parity preview using exclusive-or operation of the Operand parities and carry over parity and by comparing the predicted with the actual Result parity, characterized in that a function generator circuit (26) is provided which is dependent on of operation control signals for the logical operations "AND" and "OR" one to the respective operation-related parity function generated, namely the OR function for Hie AND operation and the AND function for the OR operation, and that a test circuit (140) is provided, using the exclusive-or link the operand parity with the pantätsfunktion independent of the result of the to be executed logical operation whose parity forms, which then the parity comparison with is subjected to the actual result parity ? Arithmetic and logical unit according to Claim I, characterized in that for Examination of the result parity of a first group of exclusive-or circuits (142). which is the parity of the generated result bits, and at least one second group of exclusive-OR circuits (148 or 150) are provided, which are dependent on operation control signals in an addition the parity of the processed carries and, when performing a logical operation, the the parity functions of the individual digits, that also a first single exclusive-OR circuit (162) for linking the operand parities and a second single exclusive-or circuit (168) for combining the output signals the second group exclusive-OR circuits with the output signal of the first individual Exclusive-OR circuit are provided and that the output of the second individual Exclusive-OR circuit is connected to a comparator (170), the second input of which is formed from the output of the first group exclusive-OR circuits. 3. Arithmetic and logical unit nad. Claim 2, characterized in that the first individual exclusive-or circuit (162) one of the two operand parities in real and the other is supplied in inverted representation. 4. Arithmetic and logical unit according to one of claims 1 to 3, characterized in that that a logical combination circuit (18) is provided, the equals from Operand bits form the bit functions AND, OR, and that the function generator circuit (24) consists of gate circuits (78, 68), of which one of the bit functions is applied to each and in dependence on the respective operation control signal as a parity function selectively to the test circuit (140) is switched through. 5. Arithmetic and logical unit according to claim 4, characterized in that at least part of the output lines of the lo- gical logic circuit (18) with a carry generator (20) and a sum function generator circuit (22) are connected, which in a "per se known manner a transfer after the relationship