DE1935258B2 - PROGRAM SWITCHING DEVICE FOR DATA PROCESSING SYSTEMS WITH SEVERAL TERMINAL BOARDS - Google Patents

Description

The invention relates to a program switching device for data processing systems with several Connection units, such as input and output units

3 4

and / or peripheral memory units with which programs are assigned. This means that a central processing unit that requires a main memory is not required to store at least one processing address of the interrupted program and several of the connection units when there is a program change. Rather, this remains in the relevant, ordered control programs as well as storage 5 command counter until the interrupted Proder has data to be processed, is continued with a gram at a later point in time, fast working memory for receiving the remaining program data, such as operand addresses, being processed Operands and operand partial results in the accumulator, the content of the addresses, which is subdivided into areas, from those of index registers, field length specifications, etc., are each the data required for the respective status of a processing or control program, but also in such an arrangement. how to save commands when a program is interrupted and operand addresses, operands, partial results, and the later continuation of the same pro word length information, etc. a program switchover control on request. running times would consist in each of the connection units

Data processing systems that equip from a central with their own processing unit. Processing unit and several connected to it. This would, however, involve a great deal of effort Require input and output units as well as peri-20, especially in the case of data processing peripherals If there are memory finenesses, it is not justifiable to use low-priced systems would probably be used to solve a processing task.

multiple programs. One of these programs is therefore already a time-consuming

the actual processing of the data while running multiple programs nested other programs became aware of the data transport between 25 suitable data processing systems, the central processing unit and the other program work terminating units subdivided into areas Includes controls and certain additional memories (U.S. Patent 3,373,408). Everyone Functions such as the triggering of control operations The area consists of several registers, the Proin the connection units or error diagnosis or program data of a specific program, -registration. With such a number it is 30 One of the registers stores the instruction count were of considerable importance that the switching of the program in question, and the other retunes If possible, registers from one program to the other are general-purpose registers, floating point registers done quickly. Such program switching can and status registers. These registers are used by the benen be very common. For example, the relevant program is used to store addresses, The processing program is always used by a request 35 operands or intermediate results. if tion of the card unit is interrupted when the program control of the data processing disc one of the plant being treated depending on the respective processing area Punch card read data bit group to the spinning program or on request from one should rather be transferred to the central unit. After connection unit to another program this transfer is carried out, the 40 switches back, only the area addressing of the Control of the central processing unit changed to the processing main memory while a program was running back, which is continued until there is no need to save program data. The ardie The next punch card column has been read and the random memory is structured in the form of coordinates, with read data in turn to the central unit via the areas of the one assigned to the program are wearing. 45 coordinate and the registers within each

Since all programs are assigned to the other coordinate under the control of the central area. Will expire processing unit must ^erf The addressing of the areas at each production ° lgt a program change, the memory and the working register in which the respective area address value of the central processing unit register set made either of the directly by the program control or program is running free of the data . These 50 when certain privileged bets occur, for which e.g. B. the command counter reading, provided that the execution of the status operand addresses, operands, the accumulator register of the currently effective area is blocked. However, the switchover only obeys what belongs to it, the programs are to be retained for the later continuation of the program - given the priority given by the program. They are therefore set by 55 by the programmer. Regarding this, a series of storage operations for the transfer of certain machine conditions main memory of the central unit and the program switchover requests requested there, if the program continues, e.g. the operating request is applied from an input / output unit In the known systems, the operations are carried out by means of no priority control aut. in fixed or variable sub-programs System, made in Proceedings of the Eastern, when requested to do so by Computer Conference, Washington D. C, December (1957) that require valuable machine time. 65 due to frequent program changes only

The aforementioned publication also mentions little progress in processing the venchiedie Mentioned the possibility of welding several command counters in front of programs made or that each of which has been waiting for one of the various conclusions for a long time

remain, since Fig. 12 called up for their operation indicates the association of Fig. 13A |

Control program again and again by other changes and 13 B,;

switching requests is interrupted. F i g. 13 A and 13 B a schematic representation

The object of the invention is for data processing of data transmissions that are in the central control _; .. ^ processing equipment of the latter type a program processing unit 5 of the data processing apparatus according y switching indicate that under comparable F i g. 1 when executing certain, for example ge: | avoidance of the disadvantages mentioned, a reduction in selected parts of the program. ;;

the number of program switchovers to the general description -

Cases permitted where the requested program General Description

switchover with respect to what is currently in operation. The data processing shown in FIG Program has a high level of urgency. system consists of a central processing unit a device of the initially described unit 10 and several cooperate with this type this is achieved by the fact that a range of the connection units 12, the optionally Entreadressierschaltung of the main memory consists of a two-stage register circuit depending on the respective purpose, of which the 15 identical and / or different input and output first Level for storage of the area addressing units 19 to 22 as well as several peripheral feeds used area address values and the memory units, such as a magnetic disk unit 15 and second stage for the storage of all of the connecting three magnetic tape units 16 to 18. In the units incoming program switching request central data processing unit is a Serves wrestling, and that a transmission control switch 20 main memory 26, the over the line units tion is provided, which contains the first stage accordingly read in and processed data The programs contained in the main memory 26 are also the highest-ranking of those contained in the second stage Requirement markers adjusts, if this one is saved, according to which the data processing system area other than the one in the first stage carries out a specific processing task. to address designated. 25 These programs also include tax programs

Further advantageous embodiments of the invention which control the operation of the connection units 12 and can be seen from the subclaims. monitor. The programs and the data are in j

The following is an embodiment of the invention various sections of the main memory 26 | application shown on the basis of drawings. It shows housed. The addressing of the main memory F i g. 1 is a generalized block diagram of a 30 taken across a memory address register 28, and FIG information taken from the memory using the program switchover according to the invention Direction-equipped data processing system, entered into a memory data register 30. To be there-

FIG. 2, the relationship of FIG. 3A is written over into the main memory 26 and 3 B, driver circuits 32. For arithmetic and

3A and 3B show a block diagram of the logical linkage of the data to be processed program switching control device and the addressing is an arithmetic and logical unit 34, tion of the main memory of the in F i g. 1 whose output is shown via a manifold 36 with the Data processing system, input of the driver circuit 32 and a

F i g. 4 is a block diagram of a program stage further bus line 37 with the memory address allocation circuit, as it is linked in the program 40 register 28. The arithmetic and switching controller of Figs. 3A and 3B to the logic unit 34 receives data from a first one Transfer of the program interruption request operand register 38 via a shift unit 40 wrestled from the connection units to the program on a first input and from a second Call register is used, operand register 42 via an inverter circuit 44

Fig. 5 is a block diagram of the register input 45 supplied to a second input. The two circuits, the program level register-new and the operand register, which are shown in FIG. 1 are also designated with TDR and priority logic in the program switching control device FDR , are loaded with the data, tion from Fig. 3 A and 3 B, which are taken from the main memory 26 and in

6 shows a simplified block diagram of the fact that the memory data register 30 has been entered, Incorrect decoding in the data processing system 50 The central processing unit 10 contains des 1, a working memory 48, which is used as a memory

Fig. 7 is a block diagram of the comparator with very fast access, for example in mono-Fig. 3A, Ethical Semiconductor Technology, is designed

Fig. 8 is a simplified block diagram of the clock work memory in the example shown in eight Encoder circuit of the data processing system divided into 55 areas 0, 1 to 7, each of areas 1 1 to 7 are at least one connection unit 15 to 22

Fig. 9 is a block diagram of the control signals assigned. Area 0 is for the processing for the program switch-generating part of the program of the central processing unit reser operation control circuit of Fig. 1, fourth. Each of these areas consists of a number

10A and 10B show a combined eighth time diagram 60 each comprising 18 bit positions in word memory locations or and a schematic representation of the register to be executed. In the example shown, each contains Berenden Main memory containing programs to rich eight such registers. One of the registers is used Explanation of a program switching process for storing the command address of the respective as

FIG. II shows a simplified flow diagram of the next instruction to be executed. In area 0 is switching control program for the FaU that several 6 ₅ this is the next command of the processing program, types of program switching requests one that is stored in main memory 26 for execution by the common program level of the central processing unit are assigned to the processing unit, and other areas are these the command addresses of the

7 "'8

Control programs for the assigned connection one after the other in an operation register 52. The remaining registers of each area are provided, followed by an operation decoder 54 the intermediate storage which is in the arithmetic. The manifold 56 is with the output table and logic unit 34 possibly connected to the operation decoder 54; those in her However, data to be processed several times or the wires contained in the memory 5 are only used in part tion of addresses of such or other data. the bit positions of the operation register 52 are controlled. These registers can also be used as a buffer memory. Another part of these bit positions controls via the for the from the connection units 12 to the central operation decoder and the bus, 58 the Processing unit transmitted data or by addressing the register in the respectively addressed operator to the line units transferring io rich of the main memory 48. In addition, the Data serve. Output signals of the operation decoder 54 can also be fed into the registers Control data, such as word length information, indexing or a general control part (operation control constants, etc. are stored. Circuit) 60 supplied to the control signals; for the

The addressing of the areas of the main memory arithmetic and logic unit 34, the shift 48 can be generated on the one hand by the currently running unit 40, the inverter circuit 44 and other parts of the processing program and on the other hand by one of the central processing units. Request from one of the line units 12 follows. The input bus 62 of the main memory. Each of these connection units is assigned to one or all of the areas in parallel, is assigned to one of several of the program levels PS 1 to PS 7 with the output of the arithmetic logic, the priority of which is with respect to an access 20 unit 34 and the other with a collective line connected to the main memory with increasing numbering 64, on which data from the connection grows. For example, the input and output units 12 to the central processing unit 10 have a unit 21, which is assigned to the program level 1, which are carried. An output bus 66 of the lowest priority and the input and output unit main memory leads to the memory address register 22, which is assigned to the program stage PS 7, the 25 28 and to the operand registers 38 and 42. Highest priority. A program switching control is also this output bus line with 50 is used to connect from a terminal unit 12 to a modification address register 68, the incoming request for operation by an increment / decrementing circuit 70i downstream processing unit an address for which is switched. The output of this circuit is to be generated at the area of the main memory 48 to which the input 62 of the main memory 48 is connected and assigned to the relevant connection unit. The modify address register 68 and the incrementing /

If the central processing unit with the decrementing circuit 70 are used for the incremental sequence of a processing program is busy, tion or decrementing of operand addresses is automatically activated by the program switching control for commands with variable word length. Another area 0 is addressed. The central processing unit therefore used when executing the program, it is the one in the command address register of the tion only this part of the main memory 48. This effective area of the main memory 48 contains area has program level 0, i.e. H. the lowest command address during each command drop out possible program levels. management cycle to be incremented by a fixed amount.

The processing program can therefore only run 40 animals in order to execute a setting of the command address if none of the connection units 12 registers on the respective next command in the Proeine Requirement is present. If this occurs, make a program.

the program switchover control 50 performs a switchover in the addressing of the main memory 48 central data processing unit 10 data on a through, so that the collecting line 72 from the central processing »- 45 is fed. The manifold 72 unit as the next command to be executed not the and the collecting line 64 form a ring line, in through the command address register of area 0, which all line units 12 are switched on, signed command, but is the command whose data transfer from the central unit 10 to The address in the command address register of the working line unit 12 takes place via the opaque memory area of the calling line unit 50 edge register 38. Are data from the main memory It is thus a program changeover 26 is transmitted to the connection units 12, so getung instead, which at the time of the failure to do so via registers 30 and 38. Will be Breaking of the processing program in the work, however, from the work memory data to a dei Memory 48 contained in this program are transferred to this program line units, this is done via listening data remain in the area © resemert. The 55 the output bus 66 and the operand processing is with the control program of the register 38. The from the connection units 12 zui calling terminal unit continues until this data is transmitted to a central processing unit Switching back to the processing program can optionally via the collecting line 62 zi lets a selected register of an addressed Be

To transfer or practice the individual areas of the main memory 48 δο rich in the main memory 48

optionally also from the processing program the bus line 36 and the driver circuit 3:

to be able to address, for example, to be brought directly to the main memory 26 after Er-.

are the program switching controller 50 via a 65 In Figs. 3A and 3B is a simplified one Collective line 56 address data depending on the block diagram of the program changeover control] an instruction of the processing program supplied to device 50 of FIG. 1 shown this circuit en1 The commands of the processing program are held in a program level allocator 80, via which di

¹⁰

Assignment of the connection unit ^ ^ Z £ ^^^ J ^ »

to the individual program levels of the central ver from those of J _üthis6her semiconductors

work unit 10 takes place. The structure of the Pro ^ peicner 'bit storage location from a

gxammsSfenzuordners ^^^. SSS ^ 5 SSStaf'vSieBdUatufe consists of the addressing

will be discussed in a later section ^b | ^s ™ ^rie 3; J ° ™ _U adding a register takes place

Program level allocator T ^

Request signals via ^ J

a register cream process

grammstufenregist _e R86 delivered in

will be the newly incoming P ^ f ^^

change signals stored. To the ^ exits

Program level registersistemePriontatslogikbcha ^

tung88 connected the program held by ^de * ^ J ™ ^ ™ i 86

to

eicherstel

SSStafvSieBdUatufe exists The addressing of _all bit storage levels of a register takes place in parallel, in that the Y addressing line of the area in which the register is located is connected to all levels ^^ ^. ^ _{> And e} -

_because ^ _{6 of eight} * addressing lines are connected to all of the bit storage locations of the co-ordinated registers of all _P's . Each bit memory location «er ^ ^ ^ _{value indication}

J ^. ode? Value taking addressed, if at her anyway

Level registers Program levels A ^ ore _{as well as dn} ^ dressing signal

change signals J ^ eüs dasjen.ge with the i _S a ^ s ^ _{addressi des}

Prioritization and all ubngen ^ prints g ^ .J ^^ _ß? ^^

d ^ J ^ ff ^ ftf f i 77 nd

tung88 connected the ^{program levels contained by de} * ^ J level register 86 dialen J ^ eüs dasjen.ge with the ho

S Dar-

priority

The segregated ^ J
a manifold 89 and
Circuits 90 »« ""
register 92, in which

gram level PS .
step register86

Position bes

will that _fall

J ^ j containing signals

Step register and the "te f _p 7 _o ^de _r ⁿ _a ^ _s ^g _tufenreg ister storing register 9" with red gray ₆

designated. Program-

A ^ "^^ XiJ ^ S i

stage regulator

the entrance via
Exit of the P

Applying a signal to the addressing line 77 and _to the addressing line X 4.

The main memory 48 is supplied with data from an OR circuit 114 via a bus 62. The OR circuit 114 consists of ^^ OR circuits, from PP ^. ^^^ ^^ _{this one}

gears with an associated AND circuit in _"ine ⁶ _{r GfU of} AND circuits 116, the second with a corresponding AND circuit of emer group of AND circuits 118, and the third program is received, the corresponding AND circuit its two- 30 from a group of AND circuits 120 verbun _übergr ^ _AND . _{Scarf n n6 will be} dem

J Main memory 48 when a control signal occurs

4SE Zi / ISP Dt i the connection terminal

nj [^ _fefl

^ ^g _f itr

a ₅

is. in the
92

TnSnsm e
gram level

is set

tioned ^ J
_gram levels _d

line 89 and the
smtenregisier

That

Ceningg The comparator 96

Τ ^ ΤΐΓ ^ Program level register92

am g _prQ _

via the collective _program .

Main memory 48 when a web occurs _{in the} p.egister ", 4SE Zi / / ISP" data is supplied from one of the connection units 12 via the bus 64, from 35 via the AND circuits 118, the Ar-96 receives 48 biih control signals

Via the AND circuits 118, the additional memory 48 when a control signal ^ γ ^^ ^ _arithmetiscn . _k , _p -

see unit 34 (Fig. 1), via the AND circuits 120 when a Steu.r _u ^ _{AR Z {J ASp <(} ^ _{n yQn} ^ _Inkrem cn-

_{tier / decree} ntierschaltung 70 to the main memory 48. The control signals mentioned are from the operation control circuit 60 in a manner known _{per se ^^ ^ ^ Dependency VQn dgn respective} output signals

^ _Line i00 45 of the operational decoder 54 generated. The data to be fed to the Ar comparator 96 of the wide memory 48 reach all bit storage locations of the memory _{via f öh A f the bus 62 in parallel.} Storage only takes place p in the bit storage locations of the register RG , _{which is addressed in the manner described}

_The bus 66 serves to extract data from the main memory 4i, which, as described, rm to the memory address register 28 (FIG. 1), the module R switching address register 68, the rDK operand register 31 ^ eg UO to 55 and the FDtf operand register 42 over not represent

W ¹ ^ cvXLneenyfl yibisYVdesArbeits- tied Torschaltongen is connected to these gate columns aa ^ sierleitm ^ en r «, J ^ ^ ^ ^ _{circuits are also} - _{m mr uch} well-known

save 48 the ^A ^ « ^c * | This ^^ ζ _{is dependent on} the operation control part 60 with the one note of the respective instruction in the operation register 52 (Fig. <about the ^? J «» 2f storing stage 93 60 caused although the collection shows for the ™ fSfc, Ania the ieweüs then in line 66 with all bit positions of the working memory 4 of the register 92 ™ Y ™ Steacht wild, if the Re- is connected, a data extraction takes place from ^the ^ S ^ Smrfstufeanfordeningssignal derived only from the bit positions of the currently addressed register 86 no ^P ™ g * S ™ _way , the addressing sters RG. Accordingly, the collective control has halt In to "Kr _ta program levels PS1 to S ₅ 66 as well as the collective line 62 each 18 cores, lines Y 1 b« rt aen » ^ ^. _{Addressing of the} main memory 48 successful

PSl zugeoran ^. J _{n acat columns} by the operation decoder54 via a collector

i ü Jd di Be line 122 depending on the respective owner

^A T inde SanSrdes Compar occurring ^ output signals f _ot the

? , r ^ge rte Artcitsweise of Kompfrators 96 is in operation detailherte aes 1%. ^ _n .

Verbmdung mt F ^ 6 ^^^ J ^^^ Der Jeweüige I ^ alt ^ es ^^^ j ^

% ■? ™ ^ iemiiSder contents of the register ξ ¹¹ " ^?) ^ Se! TuS 104 a group of AND-

? fl ^ iTS! Γ eSe Gm ^ * of OR-scarf circuits 10 ^ ^em * ^ "| ^

^ J _{n aca} pg B8 suberteüt each of these be

of the operational register 52. The bus 122 leads to two groups of AND circuits 124 and 126. The address positions in the output of these two groups of AND circuits which are identical to one another form the input of an OR circuit in a group of OR circuits 128. With the outputs of these OR circuits, the address lines AO, Xl to X 7 are connected. The bus 122 contains 16 wires to which addressing signals are applied from the operation decoder 54 (FIGS. 1 and 6). Eight of these lines are connected to AND circuits 124. These signals designate the address of a register RG from which data is to be extracted during the relevant instruction execution cycle. The other eight wires of the bus 122 lead to the AND circuit 126 and are used to define the address of a register RG into which data are to be entered during the command execution. The AND circuits 124 are conditioned by a control signal "ASP REMOVAL" , and the AND circuits 126 are conditioned by a control signal "ASP INPUT" . Both control signals are generated by the operation control part 60 of the central processing unit in a manner to be described below. The addressing line X 7 is additionally connected to an A 'address generator 129 which is activated at the beginning of each instruction cycle for addressing the register RGO. In the example shown, these registers serve as command address registers; they are therefore also referred to below as BAR .

The program stage allocator

From Fig. 4 it can be seen how the terminal units 12 the program Call PSl to PS 7 are assigned. As already mentioned, the program level PS1 has the highest priority and the program level PSO the lowest priority. The last program stage is permanently assigned to the processing program running in the central processing unit. The connection units 15 to 22 are distributed over the remaining program levels PS1-PS1 according to the urgency of the operating requests they have triggered. The type of assignment affected can be seen in the table below.

Tabel

Table (continued)

description Art Per- Ref. the the gramro- Connection entity requirement step 22nd Card unit Print: data PSl transfer of the central unit to the card unit 15th plates To write- PS6 Storage Read: data transfer of Central unit too Disk unit and «Reverse 21 ■ '■ Card unit Read — Punch: TSS '. ■■ '· Data transfer from card unit to the central unit and vice versa

description Art Per Ref. the the gram Connection unit requirement step 16 Tape unit I. To write - PS 4 17th Belt unit II Read: data PS 4 18th Belt unit II transfer of PS 4 the central unit to the concerned Tape unit and vice versa 19th printer Print: data PS 3 transfer of Central unit too printer 20th write Write: data PS 2 machine transfer of Central unit too typewriter 21 Senate a Read: data PSl and output transmission from unit, optical reader z. B. more optical to the central unit reader 19th printer Paper transport: PSl Tax information from central unit to printer 20th write Paper cart PSl machine control: tax information of Central unit too typewriter 22nd ■ Card unit "PSl 15th plates PSl Storage 16 Jand unit failure PSl 17th iaridunitll mark: PSl 18th Tape unit IIT ' Transfer of PSl 19th printer Error data for PSl 20th write Central unit PSl machine 21 Dptic PSl -it he

Each of the connection units 15 to 22 of FIG. 4 is connected to the relevant program level in register 86 via request lines. For example, a first request line 132 carries a request signal “PS * ANF” from the card unit 22, which triggers a switchover of the control to the program level 7, that is to the program level mi with the highest priority. Another request line 134 of card unit 22 is assigned to program level PS 5 and carries the signal

- »PS5 ANF * - .. Finally, a third request line 136 of the card unit is connected to a line PS1 ANF via an OR circuit 138. The request lines 132, 134 and 136 are ms * tt different functions in the card unit trains

'arranges On the request line 132 occurs respectively

then a signal when the printing device provided in the card unit for printing Vo:

Data on the punch card currently being processed requires a new data group. This request is very urgent, since the transport facilities in the card unit must be stopped when data is unavailable, which means that valuable time is lost for restarting.For this reason, the print request signal on line 132 is switched to program level PS 7 on request line 134 a control signal occurs when the card unit has read a punched card column and the read data are to be transferred to the central processing unit, or when the punching device of the card unit has punched a punched card column and then requires new data for punching the next card column. The punch request is less urgent than the pressure request explained above, which is why the line 134 is assigned to the program stage PS 5. A signal occurs on the request line 136 whenever the error checking devices contained in the card unit 22 detect an error in the functional units of the card unit or in the data to be read, punched or printed. In this case, the card unit must transmit corresponding error data to the central unit, which is also recorded there to facilitate troubleshooting by the maintenance service. The error marking request signal on line 136 has a very low urgency, since errors generally only occur sporadically, so that sufficient time is available for the central unit to call up the error data. The request line 136 is therefore assigned to program level PS 1, which has the lowest priority of all the program levels assigned to the line units 12.

In a corresponding manner, request lines from the other line units IS to 21 are connected to the individual program levels in accordance with the table above. Each of the line units has an error marking request line which is coupled via the AND circuit 138 to the line PSI A NF. In all cases where several line units are assigned to a program level, as in the case of the program level PS1 and PS 4, the line units concerned are equipped with display circuits which are scanned by a switchover control program to identify the requesting line unit. Each of the connection units has an FMA 140 error marking indicator. The three tape units 16, 17 and 18 each have a tape unit display BEA 142. The printer 19 has a print control display DSA 144, the typewriter a paper trolley control display PSA 146 and the optical reader 21 an optical reading display OLA 148 , 142, 144, 146 and 148 are bistable circuits which are switched to the ON state by a signal on the relevant request line. For example, the error flag indicator 140 of the card unit 22 is switched to the ON state by an error flag request signal supplied therefrom on the request line 136. The evaluation of the information stored in the indicators 140, 142, 144, 146 and 148 is described in a later section.

Program level register, priority logic and
Program level comparison

The F i g. 5 shows a block diagram of the new program level register 86 and the priority logic 88 connected to it. The register 88 consists of 7 bistable locking circuits FF, each of which has a setting input, a reset input R, a 1 output and a 0 output one of the program levels PS1 to PS 7 is permanently assigned. For example, the interlocking circuit 152 is assigned to the program level PS 7. Each of the interlocking circuits is set using one of two AND circuits. For the interlocking circuit 152, these are the AND circuits 154 and 156. The signal PS 7 ANF is transmitted via the AND circuit 154 from the request line 132 of the card unit 22 Dif a request query signal is present on the line 158 to the interlocking circuit 152 and stored there. The locking circuit 152 is set via the AND circuit 156 as a function of the program of the central processing unit. This is done by a command in the operation register 52 via the operation decoder 54 and the line PS 7 SET. As the F i g. 6 shows, the decoder 54 contains three subcircuits 150, 151 and 153. The decoder circuit 150 receives the operation code from the operation register 52, decodes it and supplies corresponding output signals to the operation control circuit 60. The decoder circuit 151 receives from the operation register 52 the register address that is in the operation register Contains command. From this register address, the decoding circuit 151 forms the Af address for addressing the registers of the main memory 48. This address is passed via the bus 122 to the AND circuits 124 or 126 in FIG. 3 B. The decoder circuit 153 finally receives the line unit address which the instruction contained in the instruction register 52 contains. The decoding circuit 153 uses this address to form the signals "PS1 to PS 7 EINST", which are sent to the register input circuit of FIG. 5 are fed. A control signal PS-Set from the operation control circuit 60 on line 160 is used to condition the AND circuit 156 for the transmission of the PS-EINST signals to the latch circuits of the register 86. The signal on line PS 7 EINST is also applied to an AND circuit 162, the output of which is connected to the reset input of the latch circuit 152. This AND circuit is conditioned for a signal transmission if an interlock circuit of the register set at an earlier point in time via a PS / 1 LF signal is to be reset at the end of the control program that has completed the request. This is done by a PS-FLST signal on line 164, which causes a reset of the latch circuit 152 in the off state, if no request signal for the program stage PS 7 of the card unit 22 vorlie gt. In this case, the line P57 ANt ' carries a signal, so that a reset signal is generated at the output of the AND circuit 162. The inputs of the other interlocking circuits of the register 86 are in the same way via AND

Circuits connected to the appropriate input and control lines.

The outputs of the latch circuits of the register 86 lead to the priority logic 88, consisting of a number of AND circuits, for example, 166, each composed of the latch circuits of program steps PSl to PS 6 is connected at its 1 output with such a AND circuit. All O outputs of the higher-ranking interlocking circuits of register 86 also lead to the same AND circuit. For example, the 1 output of the PS 3 interlocking circuit and the 0 outputs of the interlocking circuits PS 4, PSS, PS 6 are connected to the AND circuit 168 and PS 7 connected. The AND circuit 168 therefore only supplies an output signal when the latch circuit PS 3 is in the 1 state and the latch circuits PS 4 to PS 7 are all in the off state. The output signal of the AND circuit 168 reaches the program level register 92 via a line PSRN 3 or is also used, in a manner to be described, directly for addressing the areas of the main memory 48 of the latch circuit 152 is used. An additional AND circuit 170 is used to generate the signal PSRN-Q when none of the latching circuits of the register 86 are in the switched-on state. The inputs of this AND circuit are connected to all O outputs of the interlocking circuits PS1 to PS7. The output signal PSRN-Q is used via the additional interlocking circuit 93 in the register 92 or directly for addressing the area B 0 in the main memory 48. This area is assigned to the processing program of the central unit and is always effective when there is no request signal from the connection units 12.

In Fig. 7 is the comparator 96 of FIG. 3 A. It contains a group of AND circuits 172, each of which receives a PSÄN signal from priority logic 88 (FIG. 5) and the 0 output signal of the peer interlock circuit in program level register 92. For example, the AND circuit 174 receives the signal PSRN-6 from the AND circuit 166 and the signal FS5 (1st PSR) from the relevant latch circuit of the register 92. The AND circuit 174 therefore only supplies a signal when the switching state of the locking devices PS 6 in the registers 86 and 92 deviate from one another. The outputs of the AND circuits 172 are linked to an OR circuit 176, the output of which leads to an AND circuit 180. A signal “PSR NOT EQUAL” therefore always appears at the output of the OR circuit 176 if the content of the register 92 does not match the program level displayed at the output of the priority logic 88. If the AND circuit receives a conditioning signal via an AND circuit 182 when a PSR UNEQUAL signal is present, a bistable locking circuit 184 is brought into the setting state. The latch circuit 184 supplies a signal »1 in this state. Reset program level register « ^ .PSRRST), from which a control signal» Set program level register old «(1st PSR SET) is derived via an inverter 186. While the "LPSRRST" signal is fed directly to the latching circuits of the program level register 92 and these are stored in the

Resets the off state, the signal »1. PSR EINSTt to AND circuits 90 (FIG. 3 A) and conditions them so that the new program level value present at the output of priority logic 88 is sent to the latching circuits of the register

ίο 92 is transmitted.

The reset input of the latch circuit 184 is connected to an AND circuit 188. the Inputs to AND circuits 182 and 188 are provided by the clock circuit which is im

described in the next section. From the above it can be seen that changing the Contents of the register 92 can only take place if there is a program level value in register 88 that has a higher priority than

so the value already contained in register 92 has. If, on the other hand, an opposite to the content of the Register 92 has newly set the lower-ranking program call value, then the value in register 92 remains unchanged due to the action of priority logic 88.

changes as long as the corresponding program level marking in register 86 is not deleted.

Clock and control circuits

The F i g. 7 shows a simplified block diagram

the clock circuit which is part of the operation control circuit 60 (FIG. 1) and which supplies the clock signals for operating the central processing unit 10. The circuit includes an oscillator 192. the continuously time-shifted clock signals A and B supplies. On the one hand, these signals reach a short-term cycle clock circuit 194, which generates 8 different clock signals RO, Ri, R2, R3, WO, Wl, Wl and W3. These clock signals are staggered in time, as shown in FIG. 7 top right

shown pulse diagram can be seen. The clock signals A and B from the oscillator 92 also pass to various control circuits in the operation control section 60. The pulses A and B occur in synchronism with the clock signals R and W , but are only half as long as these.

The clock signal lines Wl and W 3 of the clock circuit 194 are connected to a long-term cycle clock circuit 196, the long-term cycle clock signals ZYKi, ZYKl, ZYK3 and ZYK 4

generated. Each of these long-term cycle clock signals temporally covers a complete series of the short-term cycle clock signals RO, Ri, Rl, R3, WO, Wl, Wl, W3 generated by the clock circuit 194. The long-term cycle clock signals are relative to one another

also staggered in time, and at the end of each such signal, circuit 196 provides one short cycle end pulse 198. The clock circuit 196 includes a cycle control circuit 200 connected, in turn via a collecting line

202 is in communication with the operation decoder circuit 150 (Fig. 6). The cycle control circuit delivers depending on the command in the operation register 52 via a Bus 204 skip - control signals to

Clock circuit 196. These signals have the effect that the clock circuit 196 skips or falls below one or more of the signals ZYK2, ZYK3 and ZYKA in the time grading.

309520/360

presses This is done in order to, for commands, bus 110 to the Y addressing lines

the less than 4 long-term cycles for their execution of the main memory 48.

need to avoid unnecessary idle time. For -_ operation of the program switching device

The example of FIG. 11 still ^{requires U1C} , τ jj ε · »ιλα inn

Command to be explained in more detail »Add register to 5 The following is based on the J-ig. lUA praise,

Register «only a single long-term cycle, so that 11, 13A and 13B

the long-term cycles 2 to 4 can be suppressed according to program switching explained,

and immediately after the end of the clock signal It should first focus on the combined eighth pulse time

ZYKX a new clock signal ZYKl can be generated referring to the diagram of Fig. 10A,

can. The control signals that are used to execute these ₁₀

Suppression are required, the processing from program level 0 to the program

at this time level 6 is in the operation control register 52 and from there back to the program

the add instruction is shown via the operation decoder stage 0. It is assumed that the

circuit 150 and the cycle control circuit 200 central processing unit 10 with a processing program

generated 15 is busy, so that program level 0 takes effect

The circuits 200 and 196 are constructed in a conventional manner. The program level register 92 is structured in a program manner. They are not included in the object step value 0, while in the program step of the present invention, so that for the sake of simplicity, register 86, all interlocking circuits are understood as a detailed representation of their structure. When the control signals occurred, it was pulled. _ao 1. PSR ADDRESS is therefore the program mare

FIG. 9 shows a further part of the operation O via the OR circuit 108 and the integrated control 60 of the central unit 10. The line 110 (FIG. 3A) to the addressing line is those control circuits which are connected to the YO of the main memory 48 (FIG . 3B) transferred. Generation of the control signals for the operation of the in Es, the area B 0 is addressed, and in Auf-Fig. 3 A and 3B, the program _{switching a5} , the signals » AFP-ENTN «, »ASP-INPUT«, control device are required. Thus, the control signal is of "ASP DECREASE" to condition- the commands 1 to 5 of the machining program of the AND circuit tion 124 (Fig. 3B) for the specific register of this area addressed via addressing lines A'-the. While addressing the main memory through a rend of each instruction cycle, an OR circuit 208, which is known per se, is formed when the 30th manner occurs, an incrementation of the instruction address, short-term cycle clock signals RO, WO and Wl. The / 4SP-EN: nV / 4 // AiE signal is also saved in the register RGO of the area BO. It is further assumed that a 210 of the OR circuit 208 is generated during the occurrence of control signals on input lines 5th command cycle of the machining program. These control program switchover request signals “PS6 ANF ” signals are generated by the disk unit 15 (FIG. 4) when certain programs are present. commands for the short-term cycle clock times R or W This signal is formed by the request interrogation occurring in each case at the end of a command cycle (not shown) in the operation control part 60. An OR circuit 3112 supplies the signal scanned and stored in the program level register 86 control signal “work memory input” {ASP-EIN-. In the following comparison of the content GABE) for the AND circuit 126 (FIG. 3B), if 40 of the program level register 92 with that of the Regian its input of one of the clock signals RO, Rl, R2 sters86 a mismatch is determined, or R 3 is present. Here, too, additional control signals are displayed via lines which are indicated by a PSR UNEQUAL signal from output 214 as a function of OR circuit 176 (FIG. 6). supplied to certain program instructions. At the next signal occurring at the clock time R 2 occurs at one of the clock times R or W. The 45 PS switchover, the content of the register 86 is transferred to the register 92 in the cycle end output signal of the long cycle, so that from this time clock circuit 196 serves as the request point by the following control signals 1. PSR interrogation signal, which the line 158 in FIG. 5 train- ADDRESS no longer leads to the program level value 0, which leads to the AND circuits 154 at the input, but the program level value 6 to the Y-output of the program level register-new 86 to the conditioning lines of the main memory 48. function. This signal is used to address the area B 6. This is done by addressing the area B 6. The following is no longer scanned the command that there is a new program switching request address from area B 0 for the removal of the gene. The conditioning signal 1.PSR- next instruction from the main memory 26 used, ADDRESS is supplied by an OR circuit 216 55 but the address of R 3 set in the corresponding register B6 at the short-term cycle clock times A1, R 2, an earlier point in time , WO, Wi, W2, and W3. This signal is used for the first instruction of the control program of the plates for conditioning the AND circuits 106 unit 15. This is instruction 22. (Fig. 3A), the program level value from the Fig. 10B shows schematically the arrangement of the program level register-old 92 via the collective 60 processing program and the control program line 110 to the Y addressing lines for the disk unit in the main memory 26. To be transferred during the working memory 48. A corresponding subsequent command cycle will now be that of the control signal »2. PSR ADDRESS « is generated for the clock commands 22, 23, 24, 25 and 26 of the control program time RO . The signal »2. PSR ADDRESS «of the disk unit. The command 26 is passed to an AND circuit 107 and conditional 65 last command of this control program. This command defined these for transmission of effect from the output of a switching back to the Programmder priority logic stage 88 supplied new program 0, by causing the operation level value via the OR circuit 108 and the control part 60 (Fig. 1) a reset signal PS -RST on

19 " 20th

Line 164 (Fig. 5) and at the same time a signal on the rungsroutine held on the ^

Line PS 6 EINST generated Since typewriter is received at the time of the command and the ⁰ ^ T ****,

26 the request signal »PS6ANF« no longer controls operations for the paper trolley em * Hieu

is present, so that the display screen ™> «_

155 the signal PS53WF is also present, and the control will next be the optical indicator

interlocking circuit 153, which by then has scanned the protection 148 for its switching state

program step-worth had saved 6 deleted As to takes place in the event that this Annunciation ^cüal ^ f T!

contains no further interlocking circuits of register 1, a branch ^to . ^ ^t ^ ~ ^pr ^! Jl-.

86 were in the switched-on state, the AND of the optical reader 21 now generates the eme transmission ™

Circuit 170 an output signal PSRNO. The 10 read data word to the central unit ^ver ^^ * j

The comparator then shows an inequality of the

Program level values in registers 86 and 82 continue to scan the error flag indicators

fixed and at the next signal »PS-SWITCH« FMA. First, the error flag indicator is displayed

the AND circuit 182 interrogates the register 92 140 of the card unit 22 End siui

switched to the program level value 0 So that 15 of these are in the off state, the. grinned

At the beginning of the next instruction cycle, all other display screens will be changed one after the other

Addressed area BO in main memory 48, with which FMA interrogated. If one of these display

now the command address from the command circuits in the 1 state again, a branching takes place

address register of this area for the removal of guns for the first command of an incorrect marking

of the next command from the main memory 26 20 routine that a transmission of t ewermanue-

takes effect. This is the 6th command data from the relevant terminal new to

of the machining program, which is now effected in the normal central unit. To eat the branches

Way is continued. individual control routines are carried out in a way

Since the program level 6 of the disk storage unit as it is in data processing systems to Ausrun-15 is assigned alone, the branches required in the instruction addressing can generally Deicanni

register BAR of the area B 6 are standing commands. At the end of every ^Ste «n» utoe eme ends

address the address of the first instruction of the control branch to a Rückstellbetenl lll jam, ucr

Be the program that the request of the disk - the program level marking PS 1 in register 00

unit 15 treated. For example, the control can be erased in the manner described. The data cier program of program level 6 the transmission of 30 different control routines, such as muptspucn ^

a data word read in the disk memory 15, field length information and the like can in the

to the central unit 10. If, however, the same main memory area is used, the surrounding

Program level several line units trains control program of Fig. Π so in the tsereicnui,

are assigned, denotes which are stored in the command of the address.

register of the relevant work memory area 35 In the same form, the program's command address also has the first command of a stage 4, a switchover control program for the identification switchover control program, which by scanning a request from an aeröanu of the display circuits, e.g. B. 140, notes from units 16, 17 and 18 on. ,.,. which line unit the request originates from. In the following, on the basis of F1 g.1 i A to JB. B. for program level 1, which 40 explains an example of the individual operations on a data transfer request from the opti-, the before and after ^ ner program switching reader 21, on control signal ^{requests from the device} using the J eweü * ^^! Ii " Printer 19 and from the typewriter 20 as well as areas B of the main memory are executed, on error marking requests from all of the For this purpose are effective among each other as elongated Kecm connection units 15 to 22. 45 corner of the main memory 26 ^ ⁸ ^^ ™} J ™? . Π shows a simplified representation of the memory data register 30, the operand register 38, of the switchover control program for program level 1. The operand register 42, the metic and This program becomes effective when the logical unit 34, the working memory, as a program switchover of the area B1 of the modifying address register 68 the memory addresses of the main memory has been addressed ter 28 as well as the data channel from and to the beginning of the next instruction cycle with the one contained in the instruction line units 12 (bus 64 in Fig. 1 address register BAR of the area, B 0). At the top of ^F "*" ^A ™ ^£! JJ instruction address are entnom- from the main memory 96 each auszuführendeα BefehIe mene command is the first command of Umschaltsteuer- program stage in which ^d ^ ^B _d £ ^e "^ program for the Program Level 1. Within this ₅₅ are registered. Among them are the 'program will be the first pressure control. * - indicated clocks (F 1 g 8) · ^ ™ display circuit 144 to its set state off which operations * ^ Ί £ ΐ * palpated. This bistable circuit is in the process of being. At the bottom of the Fig. ^ ^ 1 state, the switching control branches are the F-addresses designate, m.denen the true program for the first command of a pressure control 60 the individual short-term cycle clocks of the Aroens routine, which on the request of the Printer 19, memory 48 is addressed _below , and, for example, a paper transport. In FIGS. UA and IB, the next triggers. If, on the other hand, the display circuit is in the command sequence illustrated: 144 in the switching state 0, then the next _{step is χ Add the contents of} register 1 to the contents of the scanning of the paper carriage control indicator 146 of the 65 * _{R ister 2}

Typewriter 20 made. In the case of a ^& "wtaruooe from card unit

1-switching state of this bistable circuit finds 2. Transfer data bit group from

a branch to a typewriter control to main memory.

3. Reset program level PS 5. The incorrect address register is thus the command address

4. Subtract the content of register 3 from the content of the address register of area B 5. The content of register 2. of this register causes the command »TRANSFER

In this command sequence, commands 1 and 4 FROM KA TO HSP are called up via the memory address commands of program level 0, ie they belong to register 28 in main memory 96. This processing command running in the central unit reaches the memory data program at cycle time R 2. The command 2 is a command of the pro register 30 and at the cycle time R 3 in the operation program stage S and relates to a data super-register 52. At the cycle time RO of the second command transmission from the card unit 22 to the central unit. cycle was also the address from the BAR Command 3 also belongs to the program io transferred to the modifying address register 68,
The cycle time R 2 of the second command cycle is assigned to the step marking PS S and thus for switching the result storage of the first command cycle to the controller to a lower-ranking program. At that time, the result of the prepress will be. Commands 2 and 3 are parts of the outgoing control addition command at the output of the program, which runs in program stage 5 for operating the arithmetic and logic unit 34 and is used to control the card unit 22. to register 2 in area B 0 of the main memory

At the beginning of the command "Add RG 1 to RG 2" 48 was transmitted. For this purpose, the main memory is addressed by the Ji address generator circuit 129 (FIG. 3 B) still in the program level register 92 at the clock time R 9 , the instruction address from the program level value 0, which is addressed by the area BO addressed via the line YO ent- 20 control signal 1. PSR ADDRESS from the AND switch and to the memory address register 28 transfer 216 (FIG. 8) to the addressing line YO des Arträger. At the same time, this address is transferred to the modi memory 48. The Z addressing address register 68 brought. The command that is still in the operational memory via the memory address register 28 in the main memory address-preceding command cycle from the memory address register 28 becomes the X address from the main register 52 at the cycle time R 2. At the end of the cycle memory taken over and the transfer of the new program register 30 is entered in the memory data R2. From there it reaches the clock step value in the register 92, so that during the time R 3 in the operation register 52. At the same clock time R 3, the area B 5 of the main memory is also addressed from the mode if the fizieradressenregister 68 incremented by 2 in the incrementing / de-30 address to the command register of this area incrementing circuit 70 is increased by 2 and is brought into. At the time WO, the data B 0 supplied by the command address register of the work memory area card unit 22 to the data channel 64 is transferred. On the basis of the bit group in the operation register in the operand register 38, from where the add instruction is present 52, the operation delivers the corresponding control signals 35 to the arithmetic and logical decoder 54 at the clock time W 1 to the unit 34. At the same cycle time, the content of register 1 in the working memory is addressed to the operation control circuit 60, which addresses the register RG 6 of the area B 5 of the working cycle times WO via the AND circuit 124. Memory area BO to operand register 42 and register RG 6 contains the address of the main at clock time Wl the content of register 2 of the memory location to which the data are to be transferred from the work memory area of the same disk to the operand unit. This address is transferred from register 38. Then the content of register RG 6 is brought into the memory address register 28 of both operand registers at the clock time Wl of the arithmetic and also fed into the modifying address table and logic unit 34, which register 68 is transferred. During the following clock cycle from the operation control circuit 60 to the execution times, the received data is controlled via the execution of an addition. This addition 45 metic and logic unit 34, which continues to this when the current purpose for executing the operation EXCLUSIVE instruction cycle comes to an end at clock time W 3 while the ADD OR is being controlled, is led to the bus 36. Command, a read request signal has occurred from the At the clock time WO of the second long-term cycle of the card unit 22, the request-transfer command, these data appear at the request signal on line 158 at the end of this 50 transition of the unit 34 and are transmitted via the driver Command is entered as a PSS marking in the program level circuits 32 in the main memory 26, barrier register 86. Register 86 contains ben. Before that, at the clock time R 1 of the second long-time cycle at the end of the add command cycle, the data address incremented by 1 was a different program level value than the program back to the register RG € of the area B5 of the step register 93. It is therefore transferred at the clock time R 2 55 main memory . With the expiry of its next two command cycle, a program level long-term cycle, the command »TRANSFER switchover carried out, as it is in connection from KA TO HSP <s ends.

with fig. 9 A was explained. Regardless of this, at the beginning of the following command the

however, already in the cycle of the priority Y addressing of the main memory 48 again

logic 88 displayed new program level value for 60 directly from the priority logic 88 depending on the

Y addressing of the main memory 48 uses the content of the register 86. Since this is still a

happens under the effect of the control signal »2. PSR marking for program level 5 is included

ADDRESS ", by which the AND circuit 107 at clock time con- R 0, the addressing line Y5 effective

is ditioned, whereby the output signal sam. The next to be obtained from main memory

»PSRN5 * from the priority logic directly to the address taking command is therefore a command of the program

Control line Γ 5 of the main memory 48 transfer stage 5, the part of the previous command

will. That at the same TakteitÄO by the called control program is It is

X address generator circuit 129 addressed Be with the command »PROGRAM STAGE PS 5

23 24

RESET «. This command is used at the cycle time RG3 VON 7 "G2". It's about

R 2 taken from the main memory and an instruction of program level 0 for the clock. After at the time

time R 3 is entered into the operation register 52. For R 3 of this command also the program level register

At the same cycle time, the command address that switched to 92 to the new program level value

Zeit.R0 from the instruction address register BAR des 5 has been, at the times WO and Wl the

Work memory area B 5 for the modification address contents of registers 3 and 2 of the work memory

senregister 68 had been transferred to two area BOs to operand registers 38 and 42, respectively

Incremented back to the same ZMÄ register. The main memory receives practice

written. During the following clock time Wl the AND circuit 106, the Y address YO and from

the operation control circuit receives the signal 10 from the register address decoding circuit 151 via the

PS-RST generated on line 164. This signal AND circuit 124 the AT addresses Z 3 and Xl.

has the effect that the operation starts at the same time at time W 2 by transferring the operand

register 52 via the line unit address decodes from registers 38 and 42 for arithmetic

the circuit 153 at the register input circuit 84 and logic unit 34 the subtraction operation,

pending signal PS 5 EINST pending signal for 15 whose results are saved in the described

Reset input of the interlock circuit 161 only during the following command cycle

is transmitted. This is how the program takes place.

Step marking for the program step PS S due to the overlapping of the individual command

clears. Since the program level register 86 no longer cycles when using the main memory in

contains further program level markings, if 20 different program stuttn an additional

A signal PSRNO obtainable time advantage is obtained via the AND circuit 170. At the beginning of everyone

testifies. The area addressing of the is carried out by the comparator 96 the unequal command cycle

means: in the content of registers 92 and 86 it is determined where - working memory using the new pro -

by switching the content of the register gram level value, whereby the removal of a dei

92 from the program level value PS 5 to the command belonging to the program level 35;

step value PSO is initiated. is initiated from main memory. At the time

At the beginning of the next command cycle you can use what is required for this removal

the output signal of the AND circuit 170 via still final operations of the preceding

the AND circuit 107, the OR circuit 108 of another program level belonging instruction:

and the bus 110, the addressing line Y 0 30 are executed. This is done in dei

of the main memory 48 carrying signals. At the time R 0, select the area addressing as described

this command cycle is therefore the command address rend of the clock times R 1 and R1 by the up to thenii

from the BAR register of the working memory area still unchanged old program level value in

BO for taking the command »SUBTRACT register 92.

For this purpose 4 sheets of drawings

Claims (7)

Patent claims: 1. Programming switching device for data processing systems with several connection units, such as input and output units and / or peripheral storage units, with a central processing unit that has a main memory for Recording of at least one processing program and several associated with the line units Has control programs and for storing the data to be processed, with a fast working memory for storing the operands currently being processed and operand addresses, which are divided into areas, each of which corresponds to the respective Status of a processing or control program required data, such as command and operand addresses. Operands, partial results. Contains word length information etc .. and the corresponding one predetermined priority arrangement via a program switching control on request one of the connection units or can be individually selected by the processing program, characterized in that an area addressing circuit of the main memory a two-stage register circuit (92, 86), of which the first stage (92) for storage the area address value used for area addressing and the second level (86) for storing all incoming program switching requests from the line units serves, and that a transmission control circuit (88, 96) is provided which corresponds to the first stage sets the highest-ranking of the requirement markings contained in the second level, if this designates a different area address than the one in the first stage. 2. Device according to claim 1, characterized in that the first stage (92) of the area addressing circuit has an additional memory location (93) defined by the transfer control circuit (88, 96) is always brought into the switched-on state when no program switchover request is stored in the second stage and that the additional memory location for generating the address (YO) of the working memory area (BO), which is assigned to the processing program. 3. Device according to claims 1 and 2, characterized in that the first program level register (92) contains the program level value of the current program and as an addressing register for the main memory (48) serves, in that each program level value designates an area address of the main memory, that the second program level register (86) for receiving all of the connection units (12) incoming program switching requests, the specific program levels are permanently assigned are that the priority logic (88) is connected between the two registers, each only the highest of the requirement markings set in the second program level register and that the comparator (96) indicates the request flags indicated by the priority logic compares with the content of the first program level register and in the event of inequality initiates a switchover of this register to the program level value indicated by the priority logic 4. Device according to one of claims 1 to 3, characterized in that an instruction decoder circuit (54) of the central unit a program level marking designated by the respective program command into the second program level register adjustable or one at an earlier point in time due to a program switch request that is no longer available marking set by one of the connection units (12) can be erased. 5. Device according to one of claims 1 to 4, characterized in that the priority logic (88) bypassing the 1st program level register (92) via gate circuits (107) with the area addressing lines (Y) of the main memory (48) is connected that the Gate circuits (107) are controlled at the beginning of an instruction cycle for addressing a new work memory area, while in a later part of the same instruction cycle the old program level value in the first program level register (92) is used again for area addressing in order to complete individual operations of the previous instruction lead, and that the switchover of the first program level register to a new program level value only takes place after this part of the command cycle. 6. Device according to one of claims 1 to 5, characterized in that a working memory area (BO, Bl to Bl) several of the connection units (12) are assigned, that the connection units for each request line (136) unites with other request lines at the same program level are, contain a request indicator (140), and that a register in the working memory area assigned to this program stage contains the start address of a switchover control program which, by querying the request indicator, determines the requesting line unit and brings the control program provided for operating this unit into effect, while other registers of the same work memory area contain data of the different control programs. 7. Device according to one of claims 1 to 6, characterized in that from a connection unit (22) requirements (132, 134) lead to a plurality of program levels and that for each of these program levels in the associated memory area (BO, Bl to Bl) the addressing data for contain access to a control program which is used to carry out the various operations required by the line units.