DE1933163C - Circuit arrangement for inputting binary signals - Google Patents

Description

other transistor (Tb), while the emitter 45 teletypewriters or similar machines on both transistors reversible at a positive potential. By each of the arranged in the keypad, coupled in such a way that a th, the individual characters od. Ti, Tl and Γ3 are drawn, a contact will be suppressed. 50 actuated. To create a clear short

In addition to a resistance Rv , each of these contacts has a resistance-capacitance element Al,

C1 or Rl, Cl or R 3, C3 connected downstream. Each

this /? C element is via five coding diodes 2 and 55 coding lines individually to the five code lines

The invention relates to a circuit Ll to L5 and counter lines LIa to LSa arrangement for inputting binary signals, in particular connected coding field. When you press a binary coder, each input device one of the keys T1 to Γ 3 are at least one code line for the one binary code combination of the character via the diodes 2 character type and one of the number of remaining code 60 some of the code lines Ll until LS on OV lines brings the corresponding number of opposite lines when pressing the Γ1 ζ key. B. the Leif for the other binary character is assigned, the lines Ll, L 3 and LS. In an arrangement where, optionally, through the input device to an identifier, only these code lines, but none of the indicative potential, e.g. B. 0 volts can be connected. whose counter lines LIa, assigned to a binary value, are used in known multi-step code 65 L2a, L3α, L4α and L5α, only devices serving such circuit arrangements may be pressed one key at a time. At the same time to ensure that all steps are taken. early pressing about the keys and Tl would.

3 ⁴

gen Ll, L 2, L 3, L 5 arise, but with the same high resistance Rp ^a ° _w ^ ⁿ ^ _circuit Jr

early pressing z. B. the keys Π and Γ3 would be closed, terner ° ^e ^. _d JL _talldÄg to the base

a code line corresponding to a mixed code is connected via; i ^ine ° V _directly to the

from lines Ll, L 3, L 4 and L & result. In two- one transistor I c ι una u ^ ^ ^^^^^ _the

In these cases it would not be possible to determine on the output side whether the editor of a second inu »^ collector of the one

TtTXt one or two keys were pressed and whether reverse line unmi " ^e '° * ^1. _W i _the stand Rg to the

the combination given is correct at all. Transistor Γα una ^UD " _{istors Tbj} during the

Avoiding such mixed coding on the basis of the ? * Αεκα ^ ¹ ' _m potential + 5V

mechanical key locks against simultaneous emitter ^^ ^Γ ^ jT „ _n d Geeenlinien is on the

Pressing several keys is known. For lying quickly io. Each of the cooe- ■ ui *. ■ _{a remote} .

operating keyboards are such locks unwanted memory 5p for ^a P ™ "'' j ⁶ _{series m} i _t each

spelling mark verDuuutn. _tand r _v

Fig. 1 of each code line Ll. LS key contact let ^ a forew ^^ ^ _{property) that}

according to F i g. 1 of each code line L1 ... L 5 key contact is located J ^ jJ ^ EiSnschaf t that a counter line LIa ... LSa can be assigned, so the ^Scha l ^do 8 ^san ° "y _s f _endruc kes during its

NEN from the criterion that when pressing a i _5, the signal of a ^ersl ^ ¹ _{we diert} d, also comes when a key of each line pair ^tt only one line with whole duration "above" _between. It may be connected immediately after OV, but with mixed coding the second key press »« _{can, but until then} , at least one line pair with both lines can be done with the first. & _{for coding and}

Measures to avoid suppressed second Mgnai nu can be derived from errors. * ° ^Ausv y ^er ' ^un . ^g _i : ^Oin ^ " _{derl a} i _s0 in the retroactive

Fig. 1 shows how with each pair of lines trains mixed characters white _{hd ß dnes of the two}

arranged NOR gates Gl ... GS are monitored. Circuit ^ * ^ Χ By designing the can that both lines characters ™ * ™ & ™ _{Inductivities} not at the same time, even that of a pair can be on OV ("logical zero") . In resistors Rv aJsι in _{suppressed signal ver} . this error case leads to at least one of the gates _a5 duration of a. _{Circuits are} conceivable, the Gl to GS at the output Pius voltage (= logical lengths; » ^{ucn s} _{only at the end of} the first» one «), so that at the output A of a downstream ^Un i ^erd ™ ^CK ""L _{rn bere} its after taking over the ended quintuple gate G 6 _end OV as an error message key signal sondeiT ^ ~> _Stnfc

occurs. The error message from A can be stored as a coded character in _{a single file}

Message also actively operate: it can either affect the ₃ 'The ^On o ^ ^ung _order "ach Fig 3 for a further way of the encoded character, the ^{switch" n} f ^sa "J ¹ ^ _D ^B _iodines Da and Db first example, the. ^{Block output of the} mixed character, or step, üaoei _{smu mmen (} that when you press

have an effect on the coding lines. bridged. cis μ b _{a ben)} then becomes

A particularly simple retroactive arrangement of the key / »« ne ^ _potential value 0.5 V and is shown in Fig. 2. The assignment of one of the lines L1, ₃₅ each ^ »« «VJJ ^ _{f 5 v is} set. Will only

LIa of a pair (at OV) inevitably blocks the opposite line ^ _{is dne} ^ _{entered (} other line against simultaneous occupancy by the test TZ gea ™ '^. _L la to 0.5 V and utilization of the current gain of the gates when it comes aic β _{With the {ast leich} .

suitable rated series resistors Rv. As shown in Fig. 2 ^{_c, the} _t ^{Co de} _n S ^{n U S} _{k s} ^aU _b eider keys remains only the Einzeigt, each of these lines is oe via a diode Dl ₄₀ time printing _{the second def is} or oil ", and an inverter / 1 or Ha with the would of the first Twte De siκ _b ; _{wrote If you lift} another line connected. The detailed circuit arrangement according to FIG. 3, the ^UberDruc ™, _{eitun "s} to 4 V once or also operates on this basic principle. She's going ^ ⁰ SJ "'presses are. Here demfür the production is from five code characters in elec- ₄₅ as long as both ι asie ζ _{suppression of the} second, ironic teleprinters or similar ma- according not ^only _eing egebenen character machines, applicable. The Code lines Ll to L 5 but also of the first eg ^ _{implementation are only} here, as in Fig. 1, each with the binary value 1. The invention J st ^ _{contacts be} . Steps S 1 to 55 and the counter lines L1 α with 5 ^ fS "* also inductive switching up to LSa assigned to the binary value 0 of these steps. Restrict, indulge Each of the code and counter lines is used via a medium

1 sheet of drawings

Claims (3)

accidental overlapping of the effectiveness of patent claims two or more input devices normally effective one after the other, such as keys, 1.Circuit arrangement for inputting binary binary signals to display or to output signals, especially in a binary coder, including 5. with each input device at least one This is according to the invention with a switch Code line for one type of binary characters and a processing arrangement of the type mentioned thereby corresponds to the number of remaining code lines that on each code line pair as a promise Number of mating lines for the switching elements formed switching elements other Binary character type is assigned, the optional io are closed to determine or avoid the by an input device to a characteristic simultaneous occurrence of bits (e.g. drawing potential, e.g. B. 0 volts, lockable "0 volts") both on the code line and on are, characterized in that on the opposite line of the pair. each code line pair (Ln, Lna) as a link to avoid the formation of contradicting 15 signals through overlapping of effectiveness are closed to detect or avoid two or more input devices of the respective simultaneous occurrence of bits according to a preferred embodiment of the Erwohl on the code line as well as on its finding a code line and its counter-line Reverse line. via two transistors each by connecting the 2. Circuit arrangement according to claim 1, da- ao code line via a resistor to the base of the characterized in that one code line each has a transistor and directly or via a diode (Lm) and a counter line (Lna) via two to the collector of the other transistor and through transistors (Ta, Tb) each by connecting the connection of the opposite line directly or via a code line via a resistor to the base diode to the collector of one transistor and one transistor (Γα) and the collector of the »5 via a resistor the base of the other other transistor (Tb) and simultaneous on transistor, while the emitters of both transistors are connected to the collector of the opposite line at a positive potential, in such a way geeine transistor (Ta) and coupled via a resistor that a mixed coding is excluded. to the base of the other transistor (Tb), while the emitters of both transistors on a 30 can be derived from the other sub-arrows. The invention is positive potential, is coupled in such a way on the basis of what is described below and that mixed coding is excluded in the exemplary embodiment shown in the drawing and the character keyed in first explains the second in more detail. It shows Suppressed characters. Fig. 1 shows a circuit arrangement for inputting 3. Circuit arrangement according to claim 1, there 35 binary signals with error message, characterized in that one code line F i g. 2 shows a detail of a similar circuit and a counter line via two transistor arrangement with blocking against the occupancy of the second, in each case by connecting the code line via line when one line is occupied, a resistor (Rg) to the base of one device, Transistor (Ta) and via a diode (Db) at 40 Fig. 3 a similar circuit arrangement as the collector of the other transistor (Tb) and F i g. 2 with transistors, Connection of the opposite line via a diode (Da) F i g. 4 shows a detail of the circuit arrangement to the collector of a transistor (Γα) and after F i g. 3 with an additional device,
via a resistor (Rg) to the base of the keyboard is especially designed for electronic