DE1921816A1 - Device for displaying graphic information - Google Patents

Description

"" 1 Q? 1 81S

Patent attorneys Dipl.-Ing. F. Weickmann,

Dipl.-Ing. H.Weickmann,

DiPL.-InG. FAWEICKMANNrDlPL ₁ -CHEM. B. HUBER

■ SBPÖ "

8 MUNICH 27, DEN

XEROX CORPOEATIOU-, "'Möhlstrasse 22, phone number 483921/22

Rochester, NY14603 / USA

Device for displaying graphical Information

The invention relates to a device for displaying graphic information, in particular characters on the screen of a cathode ray tube through visible, linear and parallel traces of light. This representation can be based on letters, line drawings or halftone facsimile images.

In general, the entirety of the visible can be recorded Information can be divided into characters or letters, line drawings or halftone facsimile images. Record at least one or two of these species graphic information has been implemented since time immemorial.

Even with the development of technology, these types of information in their visibly recorded form as a means of communication cannot be replaced, and their value was especially due to the strong development of information technology increased significantly in recent years »

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3 0 9347/0883

1921811

While the recording procedures by the technical Today's systems for processing graphical data have improved significantly before their progress Recording has not yet achieved an ideal form «

It may be true that for a particular type of graphic information, the processing facilities are not essential can be improved. On the other hand, it can be argued that the currently available data processing devices, have already reached their ideal form of development. It can be assumed, however, that all of these Facilities meet several requirements such as technical simplicity, economy, working speed, high Quality and, in particular, versatility do not meet »A good data processing system must, however, have all of these properties to have. ,

Of these properties only versatility needs to be considered be checked in order to determine the fundamental suitability of a data processing device for graphic data.

In order for a data processing device to be sufficiently versatile, it must at least handle the processing, i.e. the Preparation of all three types of graphical information L> I for either the visual display and / or the record in digital or analog form. Furthermore must a® really good establishment compared to many others? Characteristics of the graphic display versatile sete, ■ for example with regard to the relative size, the resolution, the contrast and the organization in the supplied ir r Data,

A data processing device for graphic data, which is versatile and the others mentioned above; Having properties would have widespread use

3 Q S 8 4 7/0 8 81

while finding automatic photo pen typesetting. With such a These properties must necessarily be present, with the emphasis on the quality that is applied Working speed and versatility is to be laid «,

The rendering quality is a standard requirement for photo typesetting. Without this property it would be a commercial one Use of a data processing facility is doubtful, if not completely impossible.

The operating speed is variable and must be a maximum _f if the costs per unit length of the typesetting are to be comparable with those of the previous optical-mechanical typesetting technology. In general, a good data processing device works with a good quality cathode ray tube that exposes a light-sensitive recording medium. «This can then be developed and used for the production of offset printing plates. Reach the speed limit value as precisely as possible ,, The compromise between good quality and high speed should in no way go too far in order to avoid excessive impairment »This is particularly true for the processing and recording of characters.

One factor that affects the speed of data processing in photocompositioning is the time required to create each character or letter. This is more time due to the high quality level to be required for the character requ © rlich _r than the example of the character generators when printing computers Results Needed time. Due to the higher quality requirements

BATH ORIGINAL 90 9847/08 8S

However, a certain amount of time is kept to a minimum by a good data processing facility »A time saving per character can be achieved by generating deflection fields in the cathode ray tube is reduced as possible for the times at which the electron beam is blanked. In this way, deflection fields are mainly generated when parts of the characters to be displayed are drawn with the electron beam.

Furthermore, time can be saved by applying code compression for alphanumeric characters, in which for long parts of a given character just a coded one Command appears. Such a method avoids the time consuming interaction between the computer or another storage device and the data processing device

As already stated, versatility is an important one Property for a good facility for processing graphic data · This should also include graphic data Process data representing line drawings or vectors. In particular, the recording should be qualitative good line drawings may be possible if the vectors that make them up are either at constant speed or are generated during a constant and predetermined time interval. The latter type of vector generation allows the use of clock-controlled data and thus an optimal buffer storage, which makes switching simple can be used. The first-mentioned type of vector generation enables asynchronous operation of the data processing device, if so desired.

The versatility of a good computing device also relates to the ability to change

309847/088

of variable sizes, such as the density of the electron beam to be realized in the cathode ray tube. This property allows, for example, uniform exposure a 'light-sensitive recording medium with vectors unequal length generated during equal time intervals. This is important for a consistently high quality good record. ·

While the versatility relates at least to the processing of all types of graphic data ₉ , the data processing device should preferably be able to change these various operating characteristics during the recording of, for example, a single document. Although a figure can have the communicative effect of a large number of words, at present it usually consists of a mixture of alphanumeric information and line drawings, which is the only way to fully represent an idea. Such a mixture may also contain Halbtonzeichnungen "This results in an additional property for an ideal data processing device which is to be truly versatile _o

The object of the invention is to improve the processing of graphic data and for this purpose a device for displaying graphical information to be created en that its operating state for processing of alphanumeric data _F line art and halftone facsimile data can change. Furthermore, this device should operate at high speed and enable an improved display of line drawings or vectors. - - '

A device of the type mentioned at the beginning is characterized to solve this problem according to the invention by a memory for storing a sequence of binary data words,

09847/088 »

which correspond to a character to be displayed and in a data processing device the generation of this character is peculiar dark or dark. Cause light touch signals, which are fed to an operating state for the cathode ray tube and control the generation of deflection fields and dark or light scans of the electron beam. The data processing device can be controlled with digital and analog signals and generates a visible display of alphanumeric data, of halftone drawings or of, vector. information, »It contains logic circuits for developing dynamic deflection fields in the cathode ray tube as a function of a sequence of digital code characters that apply to a specific alphanumeric symbol, so that the electron beam is only moved over those linear line sections of the screen ₉ that are the desired symbol overall represent. There is also a circuit for generating vectors of any length either with a constant deflection speed or for a uniform period of time. There are also digital circuits that are used to reproduce halftone drawings in the form of a dot matrix. The strength and focus of the elect -ron-ray can be changed.

Further characteristics and advantages of the invention are evident the following detailed description on the basis of the figures emerged. Show it

JL the block diagram of an application

system suitable for the invention, ...

2 shows a block diagram of an embodiment of the invention according to en Vorrieh- *; tung, '

Pig. 3A-K and 4A-J the code commands for the computer, the

with the device according to the invention

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(S. ι β

is controlled,

Fig. 5 shows a typical produced with the inventive apparatus characters, an enlarged portion of the character shown in Fig. 5,

7A and 7B enlarged parts of the character shown in FIG. 5;

various logical circuit symbols as they are used for functional explanation of ER findungsgumäSön device, Eingatoeregister of the inventive device,

the control circuit for the input register shown in Fig. 9,

the horizontal address register of the device according to the invention,

the vertical address register of the invention Contraption,

the horizontal speed register of the device according to the invention,

Fig. 14_u "15, the vertical speed register and / or the vertical offset register of the device according to the invention,

Speed digital to analog converter of the device according to the invention, the horizontal end register of the invention Contraption,

the vertical end register of the invention Contraption,

the line drawing and blanking control circuit of the device according to the invention, the character generator register of the device according to the invention, the character-eride comparator of the device according to the invention,

BAD ORIGINAL 9098 47/0885 ~~

Fi 6th PiR Dew. 7B Fig. 8A-I »Iff. Fi *. 10 Fig. 11th Fig. 12th FXg. 13th Fig. 14 and 15 Fig.- 16 Fig. 21 lo 19th Fig. 20th Fig. 21

the power density register of the device according to the invention,

the interrupter circuit of the device according to the invention,

an interrupter circuit for vertical monoscope override and writing of the device according to the invention, the black scan register of the invention Contraption,

the adaptation line counter with control circuit of the device according to the invention, daa photo composition (PC) input register of the device according to the invention, the photo composition (PC) control circuit as well as the black generators of the device according to the invention,

the memory address counter of the device according to the invention,

the pedometer of the device according to the invention,

the repetition register of the device according to the invention,

3_3 the horizontal offset register of the invention Device and

the circuits for horizontal and vertical deflection as well as for focusing correction the device according to the invention.

With the system shown in Fig. 1, a light-sensitive Recording medium 1, for example a conventional photographic film via a suitable optical system with a light source in the form of a cathode ray tube to be exposed. The cathode ray tube is controlled with the data processing device 4 for graphic data. This is fed with graphic data that you

Fig. 22nd Fig. 23 Fig. 24 ■ Fig. 25th 26th Fig. 27 Fiß. 28 Fig. 29 Fig. 30th Fig. 31 Fip. 32 and 33 Fig. 34

.90 = 9.84 7/088 S

BATH ORIGINAL

either in digital form with a normal digital computer 5 or with a source 6 f- ^N t? analog signals are fed in.

As will be described in more detail below, the analog signal source have any of many possible forms of subsystem for the purposes of the following description it is believed to be a common monoscope. This signal source 6 can, however, also be a conventional scanner that generates an analog video signal of a two- or three-dimensional object.

The computer 5 is controlled with an input device 7, the particular for generating alphanumeric exposures of the recording medium 1, a strip reader may be, although other input devices can also be used are.

As already stated, the data processing device used in the device according to the invention is so versatile that it can provide graphic data in the form of alphanumeric information, line drawing information, analog Process information and other types of information that can be supplied to her in digital form. It is shown in Fig. 2 in the form of a block diagram.

The device for processing graphic data can work in different modes. For line drawing operations two modifications are possible. One is used to generate linear vectors during a constant Period, while the other is the generation of line vectors with constant speed and variable Time as a function of vector length. Another operating mode of the data processing device 4 is the puncturing mode in which a graphic

47/0085

-ΙΟ-see representation on the light-sensitive recording medium 1 recorded by the combination of identical points to an Easter with the electron beam can be. Furthermore, the data processing device can operate in an analog manner, with each analog signal the cathode ray tube 3 is fed to generate a corresponding recording »Another operation of the Data processing device 4 is the photo composition in which high quality alphanumeric records are made can be.

Fig. 2 shows the overall structure of the data processing device 4 for the various operating modes mentioned. This illustration is, though, for an in-depth explanation of the invention is too general, but allows an introduction to those shown in the other figures detailed logic circuits. As can be seen from FIG. 2, each functional unit corresponds to that Figure denotes, in which their circuit implementation is shown. Furthermore, the arrows show and Data channels the general flow of data in the facility shown. The only inputs or outputs of the circuit shown in Fig. 2 are connected to the computer 5, the cathode ray tube 3 and the analog signal source 6 are connected. All other inputs shown in FIG are connected to internal points of the data processing device and are not shown as direct connections, so as not to disturb the clarity of the figure.

The inputs from the computer to the data processing device are formed by two data multiples which are crosshatched in the drawings. One trunk leads to the main input register 10, while the other leads to the photocomposition register 11, which is in the _;

90984 7/0885

hereinafter also referred to as PC input register.

These data highways provide parallel data bits of the computer to the respective input register. The multiple line 12 forms a data channel of various Main input register 10 stages to other logical ones Circuits, which is indicated by the branches. This multiple line 12 is used in all operating modes used by the data processing device. At the photo composition company the data trunk line 13 is used. It should be noted that not all The registers of the main input register must be connected to the block circuits via the multiple line 12, as shown in Fig. 2. In some cases different numbers of parallel lines are from the Main input registers led to each of the logic circuits. This also applies to the multiple line 13 to · Therefore, both multiple lines are only used for Representation of the existence of parallel data channels. The data bits appearing on each multiple line are entered into the respective logic circuit by a control pulse which is generated by the command decoder 14 or the PC command decoder 15 is generated.

The data multiplexer 12 is used for optional transmission, of data of the main input register 10 sum memory address counter 35, as will be described.

For a better understanding of the mode of operation of the data processing device according to the invention are also used 2, FIGS. 3 and 4, which show the respective data words supplied by the computer via the two multiple lines represent. Each computer word or command consists of a maximum of 24 binary bits. This maximum Number is for explanation purposes only and is intended to be the. do not limit the present invention. Each bit is

09847/0885 BAD

speaks one of the numbers 1 through 24 at the top of these figures. It is used depending on the respective word or command a certain number of least significant bits as code characters for identification · Generally four bits used for this encoding; however, there are cases, where two bits and five bits are provided in a similar manner are. Sa these words are entered either in the main input register 10 or the PC input register 11, they are decoded with the command decoders 14 or 15 »so that a word corresponding to the respective received word Signal is generated. As can be seen from Fig. 2, these signals are supplied to various logic circuits. As will be described, most of the signals are used to enter the information into the input register of the respective logic circuit.

Figure 3A shows the word for the horizontal address input register (LHAR), which in the horizontal address register 16 is a horizontal address for the data processing device stores, for which purpose the thirteen most significant bits are used. This LHAR word can also be used for identification a horizontal page format for use in all operating modes. This will be more detailed described.

Figure 3D shows the word for the vertical address input register (LVAR) which generates the corresponding information for the vertical address register 17, as for the horizontal address register 16 is the case. The vertical and horizontal addresses are for example on the upper left corner of the screen in Fig * I related cathode ray tube, seen from the position of the electron source. This upper left corner is supposed to have the coordinates 0, 0 * Using the two The words described can be sent to anyone by the electron beam

BATH

009847/088 *

Point of the screen are deflected.

f 3B and 3E show the words for the horizontal and vertical end input registers (IHER and LVER), for which the thirteen most significant bits identify a respective vector end point in the horizontal and vertical coordinate system. These endpoints are related to the point 0, 0 described. The I ₁ HER and LVER words are used in the write mode to identify the extent of a vector; they provide this information for the vertical and horizontal end point registers ¹ 18 and 19.

. 3C and 3I ¹ show the words for the horizontal and vertical speed input registers (LHVR and LWR). The most significant bit of these words identifies the sign or the direction of the speed component in the direction of the respective coordinate. This bit is a binary hull in the case of a left-to-right horizontal direction or a downward vertical direction, and a binary one for a right-to-left horizontal direction or an upward vertical direction. In other words, a binary zero indicates a positive direction or a direction from point 0, 0, while a binary one indicates a negative direction towards point 0, 0. This information is entered into the horizontal and vertical speed registers 20 and 21.

lig. 3H and 3J show the words that initiate the line drawing operation, the first word being the command »Start and Stop at Endpoint ¹ * (SSEP) for generating vectors at constant speed. The sixteenth bit of this word is a blanking bit which controls the blanking circuit 22 to blank or light control the electron beam of the cathode ray tube during a respective vector. This bit is used in the command

909847 / 088S

1921815

"Start and stop at counting step Hull" for the same purpose used. This command SSGZ supplies the constant time period with its eight most significant bits during which each vector is generated, the input to the adaptation line counter 23 being made.

fig. 3G and 31 show two command words which are used for resetting; various deflection integrators and to advance the address stored in the vertical address register. That in Pig. The first word shown in Fig. 3G- is the command "Reset Horizontal-Vertical Integrators" (RHVI), which resets the deflection integrators of deflection circuits 24 and 25 for the vertical and horizontal coordinates. The other command word in FIG. 31 is the command " ^{Reset the horizontal integrator feed of vertical address 1} '(RHAV), it is used to reset the horizontal and vertical integrators and to advance the address stored in the vertical address register 17 by one step.

Pig, 3K shows the command word "vertical override Monitor "(VOMR), it is used for identification in läonoskopbetrieb vertical override, which will be described in more detail.

In Pig · 4G-, a command word is "Delete horizontal address ■ Feed vertical address »(GHAS) shown for the Data processing device the information for the del-> the memory content of the horizontal address register 16 and to advance the address stored in the vertical address register 17 by one step.

Pig. 4H shows the command word "input font generator" (LCGR), which in the corresponding operating example used for the monoscope and its control circuits 29 will. The six most significant bits determine in equal measure. "

909847 / Q if necessary

ι 1 t f »

- 15 -

Way ate horizontal and vertical deflection position im Monoskop itself. The next fourteen most significant bits determine the display of the amount in the same way the horizontal and vertical enlargement of the respective generated monoscope symbol or are in the photo composition mode used. This information is put into the font generator register 26 "and the picture size statements 27 entered. Fig. 41 shows the word "input solder density register" (EPDR), in which the eight most significant bits identify the degree of focus to which the Electron beam is exposed. The next eight most significant bits show the intensity of the electron beam at. This information is sent to the power density register 26 fed.

Fig. 4 «T shows the word" Reset Logic Computer "(RSLG), It provides a data processing device which is used to reset the logic circuits of the 4 data processing device to the initial position Command

FIGS. 4A to F show that during the photo composition operation used six computer commands.

fig * 4a shows the command "Initiation of ^{Photo Composition Service 11} (POI), where the thirteen most significant bits identify an initial address, which is written in a

that are brought together in the appropriate light distribution should, specially trained sub-cycle controls the computer in the photo composition operation

flg · 4B e inclines the jump command _# which always follows the PCI word and identifies the desired vertical resolution. The five most significant bits that are entered into the t ßohrittregistersüähler 50 are used for this purpose.

BAD ORiGiMAL

909847/0885 -

; iSI1S! |.

40 E »ig a jump command (JMP), which is used to shift the electronic transmission during the photocompo-bit operation» The nine most significant bits are used to identify the amount of the distraction »the jump required for the horizontal coordinate * Use next * five longed bits denotes the sign of this deflection in the described catfish. These bits are entered into the offset register 51 * The fourteenth bit is used to identify the horizontal direction of the software area in the black and white or repetition words that follow the respective jump command vertical coordinate of the jewell · desired position of the electron beam is required, the next _r fourth bit indicates the sign of the direction of this vertical deflection The next, third bit specifies the direction in which the amount of vertical displacement is included in the repetition words and the black-and-white word β "which must follow this jump instruction.

: 4

nooh detailed besohriettta is the corisontal ones and vertical jump amounts to a mark büiEögtm ^ dl · see an alplmnumerl to be generated in PC mode Symbol E is ordered "

? ig. 42) rigt a black and white command (BW), with Ami possible horieontal traces with dftm Elektroaeußtrehl EathodenetrAhlrbhr «auf dta Bildsöhix»

For the duration of the practice of the trace β as ine β «appears, it will affect a visible area

^l 'lit »

1921811

Dieae Btatiohjain «la / * diehalb riohWg» because IH Jctokompoeitionetoetritto a · aruQfcp *** fee ncm aerweia · duroh dl · Beaiohtimf with the KathodtJWtrohlrOhrt is eratugt. Di β-a « Druokpaatt · causes · »eohwmrzen Draok to the sttllea, exposed with the screen of the cathode ray tube were switched.

The erate and the second part of the black and white word toezeiohnen a willow area, a black beeh ei oh and the prefix of the direction of the white area, for which eleven fits are used «Of these eleven bits are used . the three most significant bits to identify the white portions that existed before the black area was generated. The fourth most significant bit describes the sign of the direction of the white area, and the remaining seven bits characterize the black component. White word must occur, If only part of a black and white word is to be used, the last or second part of this word must be identified by all binary ones in the white area, the white direction and the black area.

4E shows the repeat instruction (RPT) which enables a single word to be used to describe a maximum number of adjacent horizontal tracks which cannot exceed 51 . The most significant bit identifies the direction of a whitening area, which is identified by the next three most significant bits of this command.

9 09847 / OtSS bad ORIGINAL

f he at de * Yö * he * e * a * fia # ¥ *

arleannt, Di · «goes clearly · * aU4 de« no oh the practice of other Jigujen H **? qjr « fourteenth bit identifies anieil 44 * Schwarzbereiohta, and the rest of the Bite with the exception of the Code bits identify the number of he for dearJi oh · »repetitions.

The maximum number of repetitions (31) is given by the five binary bits are used to identify this number * In the same way as the twenty-four bits The thirty-one possible repetitions of the computer instructions are not intended to limit the invention : represent*

lig * 4F shows the end-of-otto-composition (EPC) instruction at : for which the first nine bits are the width of the for the before Specify generated characters in the required area. Identify the next twelve most significant bits in equal proportions the left and right undercut * information of the previously generated character, They refer to kerning in printing technology that part of a letter that goes over the body of the letter protrudes «As will be understood, the character width information and the Kerning information in the computer for generation ; the required space between the characters in order to achieve a high quality photo composition

After explaining the Oomputerbefehle for the different operating modes of the device according to the invention fig "2 sufficiently intelligible few Blookschaltungen except" were Nooh not named · A this * circuits of computer request generator is requesting 34II of certain information _t the Datenverarbeitungaeinrichtung a multiplicity * ·

909847/0885 ^BAD original

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f ** itii # ltui $ tfe irtiged. Furthermore let «in Adraseenahnahmiueeseiihler 35 Torgeeehtoi, the but delivery of Imioraatiaaen to the computer in Fotokompoeitionebetrieb limit »SI» correction positions 36 and 37 for horizontal ones vertical deflection serve tsur corrective compender deomeirle of the Kmihodejis ray tube,

Tor »lÄtr detailed description of the in Pig. A more detailed consideration of the photocompositioning companies, the device according to the invention is beneficial with regard to the generation of a certain series of documents. For this purpose, an L (36 point Bodoniftofcanieoü) is selected, since its generation reveals the extraordinarily high properties of the graphic data processing device of the present invention for Potokompoeitione operation.

In the following the fig «: £ _f £ _f TA. and tB described. Fig. 5 shows the entire letter with a scale which is arranged in a network consisting of squares. In the present case, the area of such a square should be 10 χ 10 grid points. I am a raster point full as an extension do 02 cm and set the 5tt * T »ahnitt the electron beam to you K | ithocl« net beam tube. this hits the Leuofateohir ». Bie in $ coordinates associated Eahlen are merely tsu BeinigeEweckeu and erlelohtern consideration of the din In Figure "6A, 7A and 7B geüeigten f" ilbereiche from Pig. 5.:. 3> ie Btiohetubenbeeeiohniingen in flg. 5 k «aa« #iohaen in; ; alphabetical name succession di «marriage order <3 erueugung ·; tier vsrsohie & inen skins of the BuohetRbwi »£ old 4er invent- j; dttßgeaäß. Apparatus, of course, mim & also - \ "mdere ^ Jte ^ eungefoleen laögllch, as from the following V; 3 «» ear »itoung is still not well known *

It should be noted that the Pig. 5, 6, 7A and 7B represent the generated letter as it comes from the electron source of the cathode ray tube 3 (Pig. 1) is seen

To facilitate a description of Figs. 5, 6, 7A and 7B, the following table of computer commands is provided, their binary code form and reception sequence in the data processing device indicates. On the right side of the table the respective type of command is given on the left side of the letter part generated with a command group, and in the middle of the table the twenty-four bits of each instruction are listed.

It should also be noted that the least significant bit (LSB) occurs on the far right of the computer instruction, while the most significant bit (MSB) occurs on the left Side of the command.

As can be seen from the table, some parts of the letter, such as parts A and H, require an essential fewer instructions than part P. This is due to the advantageous and improved coding method of the invention, which further contributes to the versatility and high working speed. ■

BATH ORIGINAL

909847/0885

MSB O O O 1 1 • 0 O O O O O O O O O O O .0 O O O -ο σ ο O O O o | O LSB r-i JMP O O O O O O 1 O -Ho ο O I ° Q O O O ο. O O O O 1 O 1 JMP A. O O O -O O O O O O O rH 1 O -O O 1 - I O O r-i 1 1 O O RPT B. O O 1 1 O 1 O O 1 O O ο -O O O O O O O O O 1 1 1 JMP C. O O O O O O O O O 1 O ι 1 I-I O -ι O O O rH 1 1 .0 -O RPT D. O 1 O 1 O O 1 O O rH O O ■ ο O O O O O O O O 1 1 JMP E. O O O P. O O O O rH 1 O O O O 1 1 rH 1 O r-i 1 rH O O RPT O O O O ο. O O O 1 O O O: O O 1 1 1 1 O 1 •1 1 O RPT O O O O O O O O ί O O O O O 1 1 1 1 1 O O O rH O RPT O rH O O O O r-i O ο ■ 1 O 1 1 1 1 1 r-i O O O 1 J. r-i 1 JMP O O ■ ο O O Ι O O O 1 O .0 1 1 O ■ 0 O 1 1 1. O 1 O Q- BW O 1 1 O O Ο 1 1 ο O O O 1 O O O O 1 1 O O O O O BW. O 1 O O O O - « O ι O O O O 1 O O O 1 O "1 O rH O O BW O O 1 ■ 0 O O 1 O 1 1 O O 1 O O O O 1: O O r-i O O O BW " Q O 1 O O O 1 O O 1 1 O O 1 O O O 1 O O O O O O BW. O ■ 0 r-i O O O O r-i 1 O 1 O O rH O ο O O 1 1 1 O O O • BW O' O O .0 O. O - O 1 1 -1 O O O 1 O ο O O 1 1 O 1 O O BW 0 O 1 O O O O 1 1 ο O O O O O O O 1 1 O O O. O BW 0 O 1 O O O O 1 O O 1 O O 1 O O O O 1 O 1 O O O ... BW. 0 O O O O O O 1 O O O O O 1 O O O O - O O 1 O O 'BW " .... MD " .0 O O O O O 1 O 1 1 O O 1 O O O O 1 O O O O O BW 0 O O O O O O 1 O - O O O 1 O O O O O 1 1 1 O O BW Γ 0 O O O O O O O 1 1 γΗ O -ο ί O O ο O O rH 1 O O O • ■ BW ■ - · ο- O O O O O O O .1 O O Q O ο O O ο O O 1 1 O O O "' BW" Q O 1 O O O O O rH O O O O O O O O O O ■ 1 O O O BW '" 0 O 1 O O O O O 1 O rH O O O O O O O O rH O - O O - BW. 0 O O ο O O O O 1 1 1 O O 1 O O O O O 1 O O O O BW 0 O O O O O O 1 1 O O O O O O O O O 1 O O O O .,. BW 0 O 1 O O O O O O 1 rH O ο O O O O O O O 1 1 O O BW 0 O O Ό O O O O O 1 1 Ο ο 1 O O O O O O 1 O O O .--, BW- 0 O O O O O O O O Q-. O Ο O O O O O O O O 1 ο O O BW 0 O O O O O O O O O ■ ο ο Ό 1 O O O O O O O ι O O 'BW- ο O O O O O O O O O ι ο O O O O O O O O O 1 O O BW ~ G
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Y " O . RPT N O O O O O O O O O O
"ο O 1 O O O 1 1 • ι 1 ]. 1 1 ! ■ O RPT O O O O O O O O O -LLo.
OO O 1 O O O 1 1 1 1 1 1 1 O RPT O O
ό OjO O
O O
O ο-
ο. O O
"ο OjO ο I ο ο! ο MjM OJO O
Ö O
O JL ₁ 1
1 1
"1 -ο b ~ 1
"O" 1 O
O" 'RPT
RPT O
ο " OO OjP OO
OJb OO OiM O
O ο_ [ι 0 0.1
Ί ι ο ö ι O
"ο 1 O
TpT ι
O 1 3. O * 1
Y 1
ö " JMP
RPT 1 O 1. O 1 O O O I 0 ·;: O, O O- O
T 1. EPC O 1

'' 90 9847/0 885

As will emerge more clearly from the following description, before the photo composition commands are supplied for graphic data processing equipment with the computer certain information is entered into the horizontal and vertical address registers relating to the relates to the area to be covered by the characters to be generated. This is the mark that is peculiar to the character identified by the reference number 40 in FIG. 5. All jump commands for the letter assigned to this marking are related to this point, as already explained above in connection with FIG. 4C. It Assume further that the computer has the photo composition operation of the data processing device with a Initiated PCI command. The first word after the PCI command is the jump command, which is the first command in the Table is listed. Its twentieth bit denotes a step by one unit, which in the present example is one raster point or 0.04 mm. This command was discussed in connection with Figure 4B.

FIG. 6 shows an enlarged area from FIG. 5 and is used for viewing the next command in the table. This command is a jump command which specifies a vertical jump by the amount ITuIl and a horizontal jump or a deflection of five units. These units each correspond to a grid point, which in turn is indicated by the smallest square shown in FIG. This command generates a static deflection field which brings the electron beam of the cathode ray tube into a first jump position 41 to the right of the marking 40. The fifteenth bit indicates that the "horizontal jump direction is in accordance with a binary ETuIl to right It is further indicated that the next black area in a repetitive word _or;. Black and white word also to the right of the mark ■ ..« -.

90984 7/08 8 5 BADORiGlNAL

19/1816

by the binary zero of the fourteenth bit. The binary one of the third bit indicates that the The step direction runs along the vertical coordinate to the upper part of the letter (Fig. 5).

The next command is a repeat word, the one Indicates black area of 99 units. V / ie can still be seen from the description of the logic circuit, causes this word creates a track 100 black areas in length or 100 grid points. The desired one The number of repetitions for this repetition word is seven.

As indicated by the capital letter A on the left in the table, the jump command and the repeat command are sufficient to generate part A of the letter.

The repeat command then causes the creation of successive tracks of 100 raster points each Lengths that run from the first jump position 41 to the right. At the end of the seventh track of a black area the electron beam is blanked and the static one AbI enkun; rs field of the cathode ray tube takes one State on, the electron beam stops for about seven times erpunkts above the point 41 holds.

The next part P of the letter is followed by two more • -J-OET.-ater commands generated by a jump word and a word of relaxation.

The jump word üemize again draws a vertical diversion with the amount UuIl and a horizontal jump starting from the marking 40 by an amount of 105 Grid points. This jump brings the electron beam in the blanked state into a second jump position, the is indicated by the number 42.

9098 kl I 0 885

BATH ORIGINAL

It should be noted that during a jump, a rewind and a white area, what the functions to be described later, the control electrodes of the cathode ray tube for moving the electron beam biased from one layer to the other in such a way that the electron beam is extinguished. The state of motion of the electron beam should therefore be understood to mean that a deflection field in the cathode ray tube electromagnetic or electrostatic type is generated, which would move the existing electron beam in the manner described. In the following it will also be the Scanning with the electron beam or the creation of a track or a black area explained. This is to be understood as meaning that an electron beam hits the fluorescent screen of the cathode ray tube hits and dabe :. is moved in a certain direction.

The last command required to create Part B. is a repetition word which means repeated scanning with the electron beam by 59 black areas or causes grid points to the right from the second jump position, namely a seven-time repetition, with each repeat track immediately above the previous one Track or scan line lies.

The start command for creating part 0 is a Jump command that deflects 164 grid points in the horizontal direction to the right, starting from the marking 40 and denotes a vertical deflection of the amount zero.

may be
It / again pointed out that this jump command a positive direction of the black area for the following black and white or repetition words and a negative

909347/0885 ^ original

^::: ·>; .- ■ '19?!

tive Schrittriohtung indicates that in the one shown in Hg Coordinate network runs upwards.

Accordingly, the electron beam is brought into a third jump position, indicated by the number 43 is. This goes out of the pig. 5, 7A and 7B. The other command required to create part 0 is a repetitive word that identifies three properties required to produce this part of the letter. These consist in a white degree division area or a division of three units, a black area of eight units and a repetition of 23 times.

As can be seen from the following description, the identification of the white fine division is of three units corresponding to 3/64 of a grid point or a white unit. The effect of this fine division is better off Pig. 7B to recognize the part of the pig. 7A enlarged represents. In Pig. 7-B is shown to be the beginning of the first Black area opposite that by the third Jump position 43 extending vertical line is slightly shifted. Similarly, it is by a similar amount the second black area shifted from the first black area. The third black area is with the second in the same context as the second with the first. The amount of shift of the first black area compared to the one running through the third jump position vertical line equals approximately 3/64 of a Halftone dot, with a full halftone dot one of the squares in Pig, 7B. is equivalent to. The shift opposite of the vertical line at the second blackout area then. 6/64, the third black area 9/64 "

From Pig, 7A it is easy to see that with each further Relocation to the vertical line by 3/64 raster

90 98 47/088 5

BAD ORIG5NAL

• - 26 -

points after generating the letter part O (after twenty-three reps) the entire shift corresponds to a grid point. In this way, the slightly inclined part of the book- " rod parts D and E caused. The part E consisting of twenty-four black areas is around three grid points displaced in relation to the vertical coordinate running through the third jump position 43. With reference to Fig. 7B again consider that the addition of the fine white pitch area is taking place, so that the retrace of the electron beam ends at the beginning of the last black area. This is also from the following description of the logic circuits for the Recognize photo composition business.

The generation of the letter part F is now initiated by shifting the electron beam into a fourth jump position 44, for which a jump command causes a deflection to the right by 132 units and a vertical deflection by seven units. It should be noted that the vertical jump amount is indicated by the complement of the binary number 7. The reason for this will be apparent from the description of the vertical speed and offset register 21 shown in FIG. In contrast to the parts already described, the letter part F is generated by a series of black-and-white words. This is necessary because of its curved boundary line. It should be noted that with reference to FIG. 4D, each black-and-white word has been described as consisting of two parts, where _; each part a white area _? indicates a white direction and a black area *

Because the processing and function of all black and white words are related to each other the description will be .der. Generation. of the Bach bar part P (Fig. 7A) to the first black-and-white word limited. The first part denotes a whiteboard «»

0 9 8 4 7/0885 BAD original

rich of 0 units and a black area of 33 halftone dots. Since the last jump word that brought the electron beam into the fourth jump position 44, a positive black area direction stated, this black area runs from 33 haster points starting from point 44 to reohts and brings a slight overlap with the letter part C. The black areas of the letter part P are shown in Fig. 7Λ for a better overview shown hatched. At the end of this track the electron beam will go to one point brought immediately above point 44 so that the second part of the first black and white word comes into effect.

This second part requires a white area of 3 units and a black area of 30 units. The dashed The squares or grid points shown show the three white areas that precede the 30 black areas lie. Processing the black and white intervening words' for part F is now skipped and immediately that last black and white word considered. It denotes a single one by the zeros for the black area black area to be generated. The second part of this word contains only binary ones created by the circuit be evaluated in such a way that this part of the black-and-white word is not used. That’s the letter part F completely.

To generate the letter parts Q, H, I, K, L and M, it is necessary to shift the electron beam into a fifth jump position, which is indicated by the number 45 in FIGS. This jump is achieved by the first command of the letter part G, which, starting from the marking 40, causes a deflection to the right by 35 units and a vertical jump upwards by 7 units. As can be seen from the table, these letter parts are each repeated with seven

909847/0885

commands, all of which have a white area and a White fine division area with the amount zero and 36 black areas indicate. Each command also identifies a repetition of 31 times with the exception of the repetition word of the letter M, which only does 20 repetitions.

After completion of the letter part M, another jump instruction follows for the part N, which is the electron beam biingt in a sixth jump position 46, which is opposite the Marker 40 is shifted five units to the right and 213 units upwards. It should be noted again that by displaying a negative direction of the vertical deflection, the vertical distance is expressed in a complementary manner is. A Va ederholuiifcswort for 102 black areas, which have to be repeated six times, ends the generation of the letter L, which is an example of letter sucking was chosen.

The last word listed in the table is the EPC command f which is decoded to indicate the end of the letter generation and with the nine most significant bits the Width of the letter occupied by the - just generated Indicating space.

The width of this space is used in the computer to determine the horizontal line for the next letter to be assigned L'arkierunp; evaluated. Has the previously generated Letter, in the present case the letter L, left and / or right kernels, this is additional information in the computer also evaluated to the effect that the correct letter spacing between successively generated letters is provided.

■ 'BAD ORIGINAL

909847/0885

1971816

After briefly describing the various modes of operation of the device according to the invention and their basic principles Aufhaus, as can be seen from FIGS. 1 and 2, are the individual circuits and their function in the following described.

Before the detailed description of the logic circuits the device according to the invention should first be explained the various symbols with which the various logical functions are shown. FIGS. 8A to 81 serve for this purpose, FIG. 8A shows an AND gate, which is equivalent to the more common symbol for an AND gate of the type shown in Figure 8B. Become bi-logical Signals with the binary value 1 are connected to the inputs of this gate at the same time, so the output of the gate generates a logic signal with the value 1. A logical or binary one can be considered a positive A voltage level of, for example, 4 volts can be defined, while a logic or binary zero corresponds to a level of Corresponds to 0 volts or earth potential.

Figure 8C shows two AND gates, each of which has two inputs and has an output which is led to an OR gate. This logical configuration is in its more common Representation shown in Fig. 8D.

Fig. 8E shows the symbol used for a NAND gate. The common symbol for this UAND gate is in Figure 8F shown. The small circle on this symbol indicates an inversion function.

Fig. 8G shows the _{symbol used for a conventional s} flip-flop. The set input s and the reset input r must be activated in cycles in order to influence the flip-flop with the trailing edge of a clock pulse which is fed to the clock input c. The marking

809847 / 0Θ8 * BAD ÖRICKAL

• - 30 -

input M and the delete input E do not have to be cycled can be controlled. If the set input is in the logical state 1, it overrides any signal state at the jerk input. The inputs for marking and deletion always override the set and reset inputs. If an input is not designated in the following figures, it should be assumed that this input is the logical State 1 leads. If an input is connected to earth, it is assumed that it has the logic state 0 leads.

The one in Pig. 8G- shown dashed lines optional inputs for the set, clock and jog function of the flip-flop. Each of these inputs can carry an input signal that is assigned to an AND gate is fed inside the flip-flop.

Fig. 8H shows two NAND gates which are connected in parallel and whose outputs are connected to one another. With this configuration you get ⁴ ; that with the logical state 0 of the output of both NAND gates all outputs connected to this output also assume this state.

Fig. 81 shows this for a conventional monostable multivibrator used symbol.

The symbols used in the circuits are more detailed in Publication No. 64-51-03E., Amendment No. 1, by Scientific Data Systems Inc.

It is also useful to explain the terminal designations of the logic circuits. All entrances are open the left side of each figure while the exits lie on the right side. In certain cases

BATH ORIGINAL 909847/0885

there are inputs or outputs in the middle part of the figure, but then this point should be with the circuit connecting conductors are artificially lengthened to determine whether it is an entrance or an exit acts. This extension brings about a connec- tion of the Clamp with the right side of the figure, it is an output, otherwise it is an input. In order to facilitate a complete understanding of the circuits, uniform designations have been made for the terminals chosen. Each terminal is identified by a number, a hyphen and a letter. The number corresponds of the figure - from whose circuit an input receives a signal or of the figure, whose circuit receives a signal from an output ". For example, means the notation 12-A in Fig. 14 indicates an output terminal in Fig. 12 a signal to that in Pig. 14 so designated input sclerame supplies. The output terminal in is similar Fig. 12 is designated 14-A, indicating that it is a Signal to an input terminal of the jn Pig. 14 shown Circuit supplies. The letter A is used to generally identify the relationship between a specific output terminal with a specific input terminal. Hence there is no further input cl emiae in Pig. 14 denoted by 12-A. These Designation wines enable an easier understanding of the figures.

Furthermore, all inputs or outputs of the register are 10 and 11 bracketed where possible to indicate parallel data flow. For easier recognition the source or location of this data are single brackets in connection with the bead entry ~ register and double brackets with the FC-Eingaoere.?inter used.

The in -Fi-ic. 2 data processing device shown for graphical "nts" contains two urinals, these

4 7 / 0.8 8 5 BATH

Control operation and data flow. The first control circuit is shown in Fig. 10 and controls the photo composition mode, the graphic mode and the analog mode or monoscope operation. The other control circuit is in Fig. 28 and operates mainly in the photo composition mode. The operation of these two control circuits will be described first as it is in the photo composition mode along with other circuits generate a letter such as the letter L shown in FIG.

FIG. 9 shows the main input register 10 which has already been mentioned with reference to FIG. This register receives the computer commands consisting of 24 bits on the parallel data multiplexed lines from the computer. Each individual input and the bit assigned to it are identified by the reference ^{symbol 2 X} , where χ + 1 corresponds to the position of the bit in the computer command and the exponent denotes the place of value within the command. For example, in Figure 9, 2 is the seventh bit. The main input register consists of a common one. Arrangement of bistable elements in the form of flip-flops 50, which are initially brought into their set state by a set pulse at the input terminal Lö ~ i>. The computer command is entered into the register shown in Pig * 9 with an input pulse at the terminal XO-A, which effects a clock-wise control of the bits supplied by the computer on the data bus. It should also be noted that the inverted form of bits 2 to 2 ^J on the output terminals. 29-A and 29-B are available through the action of the inverters 51. The use of these bits is described below in connection with the memory address counter in Fig. 29 for the photo composition operation. The inverted bits 2 to 2 ^ are available in parallel at output terminal 10-C.

909847 / 088S

The on. of the output line 10-C five pending in parallel Bits are transferred to Pig. 10 are fed to a series of inverters 52, which together act as a decoder or'NAND gates act and generate a binary 1 if all five bits have the status of a binary 1. This Pail occurs when the introductory command PCI for potentiometer composition mode the main input register in Pig. IO is supplied. Those with the output terminal IQ-D in Pig. 9 connected parallel lines lead to two decoder circuits 34 via an input terminal 9-D in Pig. IO and are used to monitor the four least significant bits of the computer commands sent to the main input register will. These decoders then generate a transmission signal at their exits. How these transmission signals are used will be described below.

Suffice it to say that each of thirteen transmission signals TS is generated with the decoders 53. It is generally used to control gates that convert the respective bits of the main input register to others Counters or registers conduct «These transmission signals as well as the. computer commands associated with them are as follows listed:

TS-I-IHAR

TS-2 LVAR

TS-3-IHVR

TS-4-1WR

TS-5-MORE

TS-6-1VER

■ TS-7-üCGR

TS-8-LPDR

TS-9-XÄVI

TS-IO-SSEP

TS-II-SIAY

TS-12-SSOZ

IS-1.3-VCIKR-

As shown in Pig * 10 emerges ₉ which are the main input register in Pig directed "9 supplied three least significant bits to a further decoder 54 _g of these bits dependent on a signal SYS processed. That him about

909847/0881

- - 34 -

the inverter 55 is fed from the computer. This signal SYS gives the decoder 54 the information that the signal to be decoded is an operation control signal EOM.

There are three EOM instructions that the computer generates in FIG control circuit shown. The first command EOM-I is processed before the various registers are stored, the command EOM-2 is assigned to the analog or monoscope mode and the command EOM-3 is simple a command that is a counter signal or ready signal for the data processing device, which indicates to the computer that the data processing device information received is ready for transmission to the computer.

With the command EOM-I simultaneously with the signal SYS des Computer generates the decoder 54 an EOM-I signal which is fed to an inverter 56. This signal EOM-I is also fed to one of the three inverters 57 which work together as an ITOR gate. The signal EOM-I ' activates a monostable multivibrator 58 whose output signal, when inverted, serves as a ready signal for the computer. This shows the computer indicates that the control circuit shown in Fig. 10 has evaluated an EOM command and is ready for further data.

The HAND gates 59 and 60 form a locking circuit, which works in the usual way like a bistable circuit. The signal EOM-I sets the latch circuit, creating a pass-through signal for the IMD gate 61 is generated, which is a signal at the output terminal 9-A generated which the Einspeieherujig des on the multiple line caused by the computer supplied data word in the main input register. This signal at the output of the ÜUD gate 61 is also used to activate the multivibrator 62, which after a predetermined delay time

90884770886. "■

A release pre-pulse is generated at terminals 11 -B and 12-C. The puncture of this pulse will be discussed in more detail below in connection with the horizontal and vertical address registers the Pig> 11 and 12 described.

The multivibrator speaks with an additional delay time 63 also responds to the signal at the output of AND gate 61 and generates at the one labeled "Start" Output terminal a start signal. This is also fed to one input of AND gate 64, the other input of which is controlled with one of the transmission signals generated by the decoder 53 «, the output terminal of the AND gate 64 is labeled 26-E, and the signal appearing at this terminal is used in conjunction with the in. Pig · 26 in a manner to be described exploited.

The locking circuit formed from the gates 59 ″ volü 60 is reset with the leading edge of the inverted start signal which controls the HAND gate. The other two input signals for this gate are the inverted common reset signal at input R (the dash indicates the inversion of the signal ) and a REQ signal at the REQ input terminal.

Another signal generated by the computer is the POUT signal, which is received at the POT input terminal whenever the computer receives information about the in Pig. 9 shown main input register can be supplied. An inverter 71 inverts the high signal level of the pulse POT and feeds the signal to one input of the NAND gate 72. The inverter 73 again generates the high signal level of the signal POT and feeds it to the AND gates 61 and 66, so that the signals from the decoder 54 are switched through.

909847/0888

A signal is generated in monoscope operation or in analog operation SYS supplied to the decoder 54 together with a command EOM-I, which is followed by an ECM-2 command, which selects the respective Indicates operating mode. As already stated, the SYS signal is an indication from the computer that a Command EOM is issued, which corrects the decoder 54 Eui Decoding of the first of these commands, namely the command EOM-I, controls .. This command is used to prepare the Main input register as well as those registers that use the at the output terminals 11-B and 12-C with the mönostabil ^ n Multivibrator 62 require the pre-extinguishing pulse generated. In addition, a ready signal is generated, whereby the Signal change between the data processing device and the computer is complete.

The decoded command EOM-I is processed as described above, and the signal EOM-2 obtained is sent from the Decoder 54 via the collective NOR gate formed with inverters 57 to the monostable multivibrator 58 as described supplied to generate a further ready signal. The EOM-2 signal is also applied to the output terminal EOM-2 led. The use of this signal is described below.

For the photocomposing company it is beneficial to start with the principle of operation of the data processing device after the computer commands for that mode have been described. The computer signals the desired photo composition operation to the data processing device for graphic data the photo composition opening order, which is the first Address in the computer memory for direct access for the start command of the respective character to be generated includes. For the example described for the letter L, the jump shown in the table is available.

BATH ORIGINAL. 909847 / 08.88

command at the location of the directly accessible computer memory corresponding to the address contained in the PGI word. Of course, the arrangement of the registers in which the entire table for the letter L is stored is _r consecutive. The graphic data processor decodes the PGI word and indicates to the computer that it must have immediate access to its memory. The computer decodes this request and responds with the question of which address of its memory is desired. The desired address corresponds to the one stored with the PCI word in the main input register, and this address "is sent to the computer via a memory address counter. With this address the computer then sends the command stored at the appropriate location, which in the present example is the jump command .

As will be described in more detail, the data processing device stores this starting address in a suitable counting register, and transmitted to every rom computer This address is switched one step further for the most information.

After the received command with the data processing device is processed, the new address is communicated to the computer to send to the corresponding new address Place to get saved command. This character change continues until the last memory address of the directly accessible memory from the data processing device has been submitted and the content of this address is the end photo composition command, which the Change of characters ended. Like the data processing device, these functions in the photo composition operation controls will now be described with reference to FIGS. 10 and 28.

9847/0 & SS BAD ORIGINAL

. - 38 -

In FIG. 10, a command EOM-I is fed to the control circuit together with a signal SYS. By decoding with the decoder 54, the main input register is connected to the data multiplex of the computer, and a ready signal is generated in the manner described. Upon receipt of this ready signal by the computer ,, _v , the PCI word is entered into the latched input register shown in FIG. ■ -...._, _..-.- .. "

In addition, the five least significant bits are decoded with the five inverters 52 in order to control the AND gates 66 and 67. The signal at the output of the AND gate 66 is fed to the output terminals 28F and 29G. Furthermore, the signal at the output of the most controlled AND gate 66 is inverted and fed to the terminal 29-H. This, inverted signal is also used to control the AND gate 68, whereby the monostable multivibrator 69 is set «, The 'inverted output signal of this multivibrator 79 is fed to the output terminal 9-D ,,, ■■".;. "

In accordance with the definition of the terminal designations described, the output terminal 9-D in FIG. 10 "'corresponds to the input terminal XQ-I) in FIG. 9, which is connected to the marking input of the flip-flops which form the main input register an offset by the multivibrator 69, after receiving the PCI-Y / map given time in an erased initial state. It should be noted that the arrangement shown in Fig. flip-flops shown 9 is _such? that the initial state is a set state, in which the one outputs carry a signal of high level or a signal of the logic state 1. It was described with reference to Fig. 8 that the reset inputs are connected to a logic signal 1, they are not shown in the figure. : - ^Λ - ■; :: "; -.

BAD ORiGlNAL $ 909847/088

'- 39 -

With the control of the AND gate 67, the flip-flop

70 is set and generates a high level signal at output terminals 28-1 and 16-J. Similarly, it produces a low level signal at output terminal 24-K.

The flip-flop 70 is controlled by the AND gate at the set input with the high level signal at the output of the AND gate 67 and the high level signal at its
KuIX output set. The setting of the flip-flop appears with the edge of the signal POiP, which with the inverter

71 is inverted and controls the NAND gate 72, the output of which is connected to the clock input of the flip-flop 70.

Further description will be made with reference to Fig. 28 which shows a part of those required for the photo composition operation Control circuit shows.

V / ie already in connection with that shown in FIG
Circuit has been described, when the PCI word is decoded, a signal indicating the receipt of this word is generated at the output terminal 28-F. This signal is received at the input terminal 10-F of the circuit in FIG. 28, and its trailing edge generates a clock pulse at the output
of the NAND gate 75, whereby the flip-flop 76 from its
the initially reset state is displaced. With this
7ustand a signal of the logic state 1 is generated at the input of the UHD gate 77 and the NAND gate 78,
while a logic 0 signal is generated at AND gate 79 and NAND gate 80. These two signals prepare the gates for further work to be described
Use for photo composition operations.

The signal pending at the input terminal 10-F is used
also to control the AND gate 81, which is a signal

909847/0 8BS BADORONAL

• ·. - t> ι ι 1 * -

■ - 40 -

supplies high level B to NOR gate 82, whose output ÖV signal is applied to an input of NAND gate 83 » This is connected with its output to the clock input of the flip-flop 84. This will cause the trailing edge the pulse received at the input terminal 10-F generates a clock pulse at the output of the NAND gate 83, the flip-flop 84 from its initially reset State switches to the set state. After the flip-flop 84 is set, a high level signal is passed through the Inverter 85 is inverted, as a result of which a signal REQ is generated at the output terminals 10-E and REQ.

This signal is referred to as the access request signal and the flip-flop 84 operates in a manner yet to be described Or rather than the access request flip-flop. As already described, this signal is fed to the computer to indicate that the data processing device is for Reception of data from the access memory of the computer is ready.

29 shows the memory address counter for direct access. During the time in which the access request signal is generated, this is at the output of the AND gate 66 appearing signal which the output terminal 29-G in Fig. 10 is fed to the input terminal 10-G in 29, whereby the thirteen most significant bits in the counter shown in this figure are deft PCI word which is stored in the main input register (Fig. 9). These bits are Supplied via output terminals 29-A and 29-D in FIG. 9. As with the description of the KJI word 4A, represent these thirteen bits the address of the future composition routing commands in the access store rather that for the generation of the Jewfcllfe desired Sohriftielchens is required * When described Example Is this character the Buoh-

909847/0885

... 41 -

rods I ₅ and the first word of the jump command shown in the table. The bits are input via ^ q AND gates 86 into a corresponding number of flip-flops 87, which act as counter registers.

The computer then decodes that with that shown in FIG Circuit generated access request signal and identifies a signal ZAD for the data processing device by means of that the signal REQ was received and recognized. The signal ZAD also serves as an instruction for the data processing device, that the computer receives the address stored in the address counter (Pig, 29). These Bits are then fed to the computer through inverters 88.

The signal ZAD is from the data processing device received at the terminal similarly labeled 28 and is used to generate a clock pulse via the AND gate 89, the NOR gate 82 and the NAND gate 83, its R-ückflanke the access request flip-flop 84 resets. This sends the access request signal to the Terminals 10-E and REQ terminated.

In Fig. 27, the PC input register is for photo composition operation shown, it consists of 22 flip-flops 90, the set inputs of which are connected to the output of an inverter 91 each are. Each flip-flop is an output line a register in the direct access memory of the computer assigned, which supplies the input signal for a respective inverter 91. The 22 output lines of the direct Access memory supply the 22 most significant bits of the photo composition commands of the computer memory to the £ 0 ~ Input register.

After processing the access request signal there are the computer picks up the signal ZAD and recognizes the memory *

& 09847 / 088S

J * * * * J * tt J

t *

i J .J *

'J J

Jt t X

• -42- ₄

address counter (Fig. 29) delivered address, whereby the Output lines of the direct access memory activated and its memory content in the PG input aggregate along with that received from the memory address counter Address to be supplied. This! Transmission takes place with a signal ZDO, which is similar to the one already in connection with Pig. 10 described signal POT functions *

In the circuit shown in FIG. 27, the signal ZDO is received at the correspondingly designated input terminal and fed via the inverter "92 to a monostable multivibrator 93, the output signal of which is inverted by the inverters 94- inputs the bits supplied to the output lines of the computer into the Fl Io-I ¹ I ops 90 ...

Since the photo composition commands consist of 24th bits and only 22 bits with the PG «input register shown in Fig. 27 are received, the two least significant fl $ ts ■; yet to be explained. In the circuit shown in Fig. 28 i these two least significant bits are transmitted via the output lines of the direct access memory of the computer: fed to a conventional decoder consisting of four inverters 94 and four HAND gates 95 is formed »Since this decoding: of the two least significant bits takes place in a known manner, a detailed explanation of this decoder is not necessary.

As has already been explained with reference to FIGS. 4B to 4F, the two least significant bits of the photo composition commands are used to code these commands. Therefore, the decoder recognizes these coding characters accordingly and generates a signal at the output of one of the NJUOJ-Öatter 95, which the respective Fatokom ^ ? pöitionsbefehl features, namely a Sprungt ommand _t a Soh.warz * -W0iß command _for .a how "-

or a photo composition end command, »

* f I t ■

( ι r ι

- 45 -

The output of each NAND gate 95 is the set input each assigned a flip-flop. Those flip flops sifcd with BW »HPT, JMP and EPO and the named Assigned to commands »

The iDaktingang each of these flip-flops is with the entrance ski emme 27-A connected, which depends on the reception of a signal ZDO in the PO input register (Fig. 27) Receiving signal.

The marking input of the flip-flops is connected to the The output of the NAND gate 96 is set. This ensures that the flip-flops are initially in the set state bind before the decoder decodes a PÖ command code.

The arrangement of the decoders is such that when a respective command is received, the set input of the flip-flop assigned to this decoded command receives a low-level signal, while the other flip-flops receive high-level signals. This means that all flip-flops of that Flijp-flops corresponding to the decoded instruction remain upon application of TUs SPaktsignals at the input terminal 27-A In its assembled state, with the exception · It is isurUokgesteilt · Be eel recalled that no input signal for resetting the flip -Flops is shown.

Since the generation of the letter L is an example of the Description of the photo composition company that serves the purpose of the present invention should be described in the preceding The jump command at the right place in the table is considered

909847/088 $

will. This command is stored in the register of the direct access memory of the computer, the one in the POI word corresponds to the address contained in this letter. This command is issued while receiving the The ZDQ signal on the output lines of the memory is transferred to the PC input register (FIG. 27). From Fig. 4B you can see, that the code for this command is 01 and is supplied to the decoder shown in FIG. The jump flip-flop is reset by its decoding and generates a signal ge-P at its one output near level, at its zero output a high level signal. The one generated at the one output of this flip-flop Trailing edge activates the monostable multivibrator 97 for generating a high level pulse of predetermined duration applied to the input of NAND gates 78 and 80 and the AND gate 79 is supplied. The zero output of the Jump flip flops is right m? t an input of the AND gate 77 verbxuiden, whereby this is controlled.

As already mentioned, what is received at the clergy 10 shown in FIG. 28 causes and through the reception and the Processing of the PCI word in that shown in FIG Control circuit generated signal a setting of the flip-flop 76. This produces a low level signal which the AND gate 79, the NAND gate 80 and the AND gate is fed.

The pulse generated with the moncstable multivibrator 97 also serves to trigger a second monostable multivibrator 99, the output of which connects to the second input of AND gate 98 is connected. Furthermore, the pulse generated with the monostable multivibrator 99 triggers high Level a third I.Iultivibrator 100, which a signal low level or an inverted pulse for the input of the NAlJD gate 96 is generated. The other exit

BATH ORIGINAL 909847/0885

this multivibrator generates a high level pulse for the input of the IMD gate 101, which is in the control circuit for the access request flip-flop 84 arranged is. The task of this AND gate is described below. Further, the pulse becomes high level of the multivibrator 100 is fed to one of the inputs of the NAND gate 102, which controls the operation of the flip-flop. 76 in still controls in a descriptive manner.

If the flip-flop 76 is set and the jump flip-flop is reset, a high level signal is generated at the output of the OTD gate 77, which signal is referred to as the step command signal, while a low level signal is generated at the output of the NAND gate 78 for which: with the multivibrator 97 a certain duration is generated. This low level signal is referred to as a non-step command signal "that is, it has a level opposite to the step command signal." These signals are supplied to the output terminals 30-A and 30-B in Fig. 28 corresponding to the A, ~ angsklemmen 28-A and 28-match "B of the pedometer shown in Fig. 30..

The function of the step command signal is to move in the memory part of the step counter the · respectively desired It is very useful to save the five highest expressions Bits of the jump word is specified in the PC input register (Fig. 27). As is apparent from Fig. 30, these five most significant bits depending on the step command signal entered into the memory section via the AND gates 103. This consists of five flip-flops 104, the initially "in the: 'deferred state. Since it is required is to enter these bits into the flip-flops with a clock pulse, -xvird the-non-step command signal through NAND gate 119. "The other input of this NAND gate is supplied with a high level signal controlled, which is triggered by the trailing edge of the non-step

909847/088 5 ORIGINAL BATHROOM

signal fails to coincide, and thus the required acid. ^"T clock pulse for the 5 ¹ IXP J ¹ Iops 104 generates depending on the ^'i presence of a binary 1, the flip-flop 104 are then placed.." -

The counter part of the in Fiλ. Step counter shown 30 consists of five flip-flops 105 ^in: a down counter connected shape and are driven by Zählimpitlse.

ψ A hereinafter referred to as sampling signal of the circuit shown in Fig. 30 zugefühi't via the input terminal 28-0 · and causes the transfer of the bits stored in the flip-flops 104 via di e "AND gate -1Ό.6 "-in the flip-flops 105 of the counter part. The outputs of the AND gates 106 are each connected to the marking input of the flip-flops 105. On. these are the Yieise ■ - flip-flop 105 is set at the transmission in the flip-flop 104 stored bits, so that the binary 1 v / are transmitted erte. It should be noted that the data stored in the memory section are not deleted by this transfer, since these flip-flops after receiving the step command

^ signals at input terminal 28-A and a scan end signal stay in their state.

The type of generation of the scanning end signal is explained in the following in connection with the description of the black area in a repetition word.

The operation of the pedometer is described below. ben. Basically, its function should ensure the correct vertical resolution of the one produced in the photo composition process ensure traces of light. This is done in that the the required step / characterizing binary "In-" "." '., formation in the down-counter part of the flip-flops 105 " is saved. At the. End of a horizontal scan

"- BAD ORlGIMAL

90 98 4770 88 S.

and during the retrace of the electron beam the contents of the down counter are counted by one in Pig. 26 oscillator shown is reduced. These counting pulses are received with the circuit shown in FIG. 30 at the input terminal OSC. If the counter reading 0 is reached, an end-of-step signal EIS is generated at output terminals 15-A, 24-B and 28-C, which signals the execution of the desired step. The puncture of this EIS signal is described below in connection with the Pig. 15 » 24 and 28 described.

V / ie in more detail with reference to the Pi ^. 14 and 15 is, during the time between the storage in the meter part of the in Pig. 30 shown Schaltimg and the Reduction of the content of the counter part to the NuIl state a signal in that in Pig. 14 and 15 shown vertically -Of fs etr egi st it generates that depends on the step direction allows the content of this register to be increased or decreased. A digital anal shock Koiiverter sets are used to convert the count request into an analog deflection signal, there? never vertical position of the electron beam accordingly changes. .

As has already been described, the transmission between the S το " ¹ " upper part and the counter part is caused by an end-of-scan signal received at the Klemiae? BC. The ⁿ r-es signal also controls the UKD-gate 107 "wodnrc: h äa? Flip-flop 108 is set. As a result, the UHD gate assigned to the set ^ a ^ aniT of the flip-flop 109 is activated, c ~ dai? the next oscillator pulse received at the Kleiowe OSC sets the flip-flop 109.

The oscillator pulses are also used as counting pulses Reduction of the counter content used. This is done through the direct connection to one of the inputs of the

BATH ORIGINAL 909847/0885

AND gate associated with the clock input part of flip-flops 105. The control input of this AND gate is connected to the output of an inverter 110. This inverts the signal of the NAND gate. 111, which is the set output of the Flip-flops 109 and the output of the NAND gate 112 are monitored. The NAND gate 112 monitors the reset output or zero output of the flip-flops in the counter part. Will the If the step value is transferred to the counter part, the output will of the NAND gate 112 a high level signal that together with the high level signal at the 1 output of the set flip-flops 109 generates a low level signal at the output of the NAND gate 111. This signal will inverted with the inverter 110 and controls the clock input »each flip-flops 105 of the counter part. In this State, the trailing edges of the oscillator pulses are used in known yfeise to reduce the counter content. Achieved If the counter has the state 0, the output of the Inverter 113 generates a high level signal indicating the counter status. This signal becomes the exit ski emme 28-D supplied. It is also used via the gate 111 and the inverter 110 to block the AND gate ' ter associated with the clock input of the flip-flops 105 '. That is the description of the step counter shown in FIG closed. The utilization of the signals generated with this circuit is in connection with other functions of the device according to the invention for the photocomposition operation described. As will be explained later, this register is used together with the vertical offset register (Figs. 14 and 15) for producing the vertical displacement of mutually adjacent tracks in the photo composition mode.

Reference is again made to FIG. 28. It has already been noted that when ^{the jump flip-flop is divided into R 1} , the pulse generated by the multivibrator 97 causes the generation of a further high-level pulse at the output of the multi-vibrator.

BAD ORIGINAL 9098A7 / 0885

vibrators 100, which is fed to the NAND gate 102. The I ¹ IiP-FlOp 76 is in the set state. This opens the NAND gate 102 and, together with the high level signal of the flip-flop 76, generates a low level signal at its output. This generates a high-level pulse at the output of the NAND gate 75V, the trailing edge of which the flip-flop 76 resets. This resetting ends the step command signal at terminal 30-A.

When the state of the flip-flop 76 is reset, in each case an input of the AND gate 79, the NAND gate 80 and of the AND gate 98 is controlled, the one with the zero output of the flip-flop 76 is connected. This prepares these gates for the next PC command.

The high level pulse at the output of the multivibrator has a dual function. Except for resetting the It delivers the opening signal for the flip-flops 76 AND gate 101. The other input of AND gate 101 is connected to the "Null-Alis" gang of flip-flop 84, which was set by the signal ZAD. This high level pulse at the output of AND gate 101 is passed through the NOR gate 114 and the NAND gate 83 converted to a clock pulse which the access request flip-flop 84 again sets. As a result, a request signal REQ is in the manner described at the output terminal 10-E and the Terminal REO generated. Furthermore, the inverter 115 inverts the "output signal of the NOR gate 114, whereby a count signal is generated at the output terminal 29-D which corresponds to the input terminal 28-D in FIG.

29 shows the memory address counter which tells the computer the memory address for its direct access storage supplies, in which the information assigned to the first command for generating the desired character is given.

909847/0885 bathroom

hand is. As can be seen from this figure, this serves to the input terminal 28-D applied counting signal for the step-by-step shifting of the binary number stored in this counter by one step. In this way, the PCI- "word delivered start address one step further pushed. The next command required to generate the letter L (example) is used in the next Address of direct access memory of the computer stored.

The processes already described are repeated by the computer carried out. This receives the REQ signal, interprets it and identifies a ZDO signal while it the address from the storage address counter shown in FIG transmits and prepares the data processing device using a signal ZAD ensures that it has the contents of its memory according to the last received address to the PC input register.

This memory content represents the next command in the table above, which is a jump command and indicates zero vertical displacement and five units horizontal displacement. As indicated, the sighting of the horizontal displacement is from left to right if the letter is according to Fig. 5 is considered. The step direction is through the third least significant bit as in Figo 5 from the bottom indicated above. It should also be noted that the binary 0 for the fourteenth most significant bit has a direction from left to right for each black area in each subsequent repeat or black command.

The processing of this branch instruction is illustrated in FIG. 28 described. As already stated, identi- "' the decoder fies the jump code 01 and sets the

909847 / Q88S

Jump-Flip-I ¹ Iop back by the second signal ZDO appearing at terminal 27-A. This flip-flop was reset to its initially set state by the low level of the multivibrator 100 at the output of the NAND gate 96 as a function of the pulse. The effect of resetting the jump flip-flop is very similar to the effect of the deactivation of a jump command, but with a certain difference. The flip-flop 76 is now in the reset state, whereby the AND gate 77 and the NAND gate 78 are blocked. This is correct because these two gates control the storage and processing of the vertical step value, which has already been explained. As already explained, the "high level pulse" generated by the multivibrator 97 when the jump flip-flop is reset controls one input of the AND gate 79 and one of the NAND gate 80. These two gates generate a jump pulse at the output terminals 15- F and 33-G as well as a non-jump pulse at output terminal 14-H.

The output of the reset of the jump flip-flop controlled multivibrator 99 causes at the input of AND gate 98 together with the zero output of the Flip-flops 76 produce a high level pulse at output terminals 14-1 and 15-J, as follows is referred to as a delayed jump pulse.

The inverter 116 inverts the delayed jump pulse to generate a no signal for a delayed jump pulse at output terminal 33-K.

In Figures 14 and 15, the vertical offset register is for Photo composition company shown. This register causes the amount of the vertical distance by which the electron beam jumps or is returned. Since this direction for the letter shown in Fig. 5 as an example up or down

909847/0885

197181-6

runs down, the register is an up-down counter formed, "in which the method of counting is indicated by the third least significant bit of the jump instruction Step direction is determined. As in connection with Pig. 40, this direction runs in Pig. 5 up if the third least significant bit is a binary 1 in the jump instruction. The opposite direction occurs for a binary 0.

In the in Pig. 15 determines the flip-plop 120 whether the counter counts up or down or not. Does the step direction run in Pig. 5 up corresponding to a binary 1, the one in Pig. 14 and 15 counters shown controlled upward. this happens by entering the third least significant bit in the flip-flop from the corresponding memory location in the PC input register in Fig. 27. This input is made when the jump pulse is received at terminal 28-F, which is assigned as The clock pulse for the flip-flop 120 is used, which is initially in the "reset" state. Because the reset input this flip-flop is internally connected to a high level signal, the counter is controlled downwards, if the third least significant bit of the jump instruction is a full.

The delayed jump pulse at input terminals 28-1 and 28-J in Figs. 14 and 15 is for keying those Bits of the jump word in the offset register, which indicate the amount of vertical displacement, i.e. the fifth to thirteenth bits. Like from Pig. 14 "and. 15, the AND gates 121, the NOR gates 122 and the Inverter 123 inputs the selected bits to flip-flops 124 which form this offset register. The exit of each flip-flop 124 is connected to a digital-to-analog converter 125 whose output signal amplified with an amplifier 126 and sent to the output

909847/0885 ^{BAD 0R! GINAL}

- 53 terminal 20-A supplied v / ird.

Because the processed jump word is a vertical shift with the amount 0 indicates "the content of the vertical offset register remains 0. ·

32 and 33 show the horizontal offset register for which a description will be given of the processing of that portion of the jump instruction indicating the horizontal displacement. The horizontal offset register produces the same results for the horizontal direction as the vertical offset register of FIGS. 14 and 15 for the vertical direction. The nine most significant bits of the jump instruction identify the horizontal shift and are input to the flip-flops 128 via the AND gates 129, through the no signal for the delayed jump pulse at the input terminal 28-K in FIG. 33 ₁ the is inverted with the inverter 130. The fifteenth bit indicating the horizontal direction is input to the flip-flop I3I through the AND gate I32 also by the output of the inverter 130. As can be seen from FIG. 33, the outputs of the AND gates 129 and 132 are connected directly to the marking input of the flip-flops 128 and I3I.

The one received at input terminal 28-G in FIG Jump pulse serves to pre-erase flip-flops 128 and 131 in FIG. 33 and the flip-flops in FIG. 32.

", Yie was explained with reference to FIGS. 40 to E, act the fine division and the black area are based on the horizontal shift. This information will evaluated by the horizontal offset register, in particular by the part shown in FIG. 32. A complete description of the entire offset register is available At this point in the description of the photo composition business, it is not necessary, however, it is advantageous to

19-1816

•. .- 54 -

the overall organization of the horizontal offset register explain. . . .: -. ■■ - · "-

Basically, the upper parts of both figures form and ~ the lower left quarter shown in Fig. 33 one binary full adder egg ·. Binary addition is used in relation to the horizontal shift, a sum is formed in each case. In Fig. 32, the is contained in the repetition words V / ei ß -fine information in d by th e FlIp-Fl op s 133 formed registers totaled. This information reaches the offset register, In, via AND gates 134 33 become the black areas of the first and second Part of the black and white word with the horizontal jump information summed up, including the one in the lower right Quarter of the figure is shown circuit .. With this The circuit is also included in the repetition strategies White area, taken into account. This will be discussed in the following with the Description of the processing of repeated words and-, the black and white words explained in detail. "■■., - -.-. ■

A complete description of Figs. 14 and, 15 :, that'as Represent vertical offset register for fetocomposition operation, and the horizontal offset register shown in Figs is postponed, it should be noted at this point that vertical information in the jump. word entered into flip-flops 124 (Figs. 14 and 15) ... would and the flip-flop, 120 in a state · corresponding! the step would be brought. In a similar way ,-·:.'; the horizontal information of five units, · di.e ■> ... " from the second Y / location in the table above, is input to the nine flip-flops 128 in Fig. 33, '. : while the bit for the horizontal direction in the flip--, ". · ■. ■; ' Flop 131 is stored. - ■ ■

The binary vertical information contained in the in Fig. 14 .and '. 15 shown vertical offset register is stored fv

9.0-9 8 47 / 08-81

is converted into an analog one with the digital-to-analog converter 125 Signal converted and amplified by the amplifier 126 given to the output terminal 20-A. In a similar way is the horizontal offset information with the converter 135 (Fig. 32) converted into an analog signal and amplified by the amplifier 136 to the output terminal 20-G given.

In Pig. 20 the character generator register is shown. The amplified analog information that specifies the data for the vertical displacement (vertical offset) is Four conventionally designed via the input terminal 15-A Analog switches 137 supplied. This analog signal is further amplified with the amplifier 138 and one Series of three analog switches 139 fed which like the switches 137 are formed. The switches 137 and 139 are dependent on the content of the with The character generator register formed in the flip-flops 140 is selectively opened for a specific vertical displacement net or closed. For the time being, it is sufficient to state that the switched through each of these gates analog voltage has an amplitude that depends on the gate that is closed.

As will the vertical analog offset information the horizontal analog offset information that the in 20 via the input terminal 32-G is supplied, amplified with an amplifier 14-1 and the Input from seven analog switches 142 fed accordingly the analog switches already described are. These switches enable the control of the horizontal], runges and are also activated by the im Character generator register stored jump information controlled. Depending on which analog switch is closed for horizontal and vertical displacement, a corresponding analog signal is sent through the amplifier

909847/0885 _BAD

14-3 or 144 generated and at the output terminal 19-A "or 19-D made usable.

In Pig. 19 receive input terminals 20-A and 20-B indicating the horizontal and vertical offset information Analog signals from the Pig. 20 shown circuit. These signals are to be described with additional signals are summed, amplified and fed to output terminals 34-C and 34-D.

These output terminals 34-C and 34-D correspond to the input terminals 19-C and 19-D in Pig, 34 and are respectively led to a further amplifier 144 or 145. The output signals of these amplifier stages are based on the dynamic focus and deflection correction circuit 146 and then applied to the cathode ray tube deflection system. The details of this Correction circuits 146 are not described since they are not essential to the invention per se and each may have suitable embodiments of known type which are used for focusing and compensating for deflection errors serve, which are caused by the geometry of the cathode ray tube itself.

As already described, the two analog signals indicating the horizontal and vertical displacement each summed with an additional analog signal, before moving on to the in Pig. 34 shown correction circuits are given. These additional analog signals be with the ones in Pig. Il and 12 shown horizontal and vertical address registers generated. As has already been described, the correct coordinate value is obtained from the computer before the PCI word is processed for marker 40 (Pig. 5) is entered in the horizontal and vertical address registers. On this mar-

809847/0888

40 all jump operations are related. Therefore it is necessary to use the analog signals of the horizontal and add the correct horizontal and vertical address analog signals to the vertical shift, to bring the electron beam into the correct position to generate black areas.

A brief reference to the Mg. 11 shows that from the "bistable memory elements 32, for example flip-flops, a conventional digital register is formed, which a pre-clear signal via the entrance gill 10-B. This signal serves to reset the flip-flops 32, as has been described with reference to FIG. 10, before receiving the Transmission signal at the input terminal TS-I. This Together with a start signal, the transmission signal causes the AND gate 33 to be activated, which generates an opening pulse high level to the input of the AND gate 38 supplies. The AND gates 38 cause the thirteen most significant bits of the to be entered via the marker input Word LHAR from the main input register into the respective flip-flop 32. A digital-to-analog converter 39 monitors the one output of the flip-flops to generate an analog signal indicating the horizontal address. The amplifier 47 amplifies this analog signal and delivers it to output terminal 19-D.

FIG. 12 shows a register similar to that shown in FIG Register is almost identical. This register stores the vertical address data. The pre-clear signal is activated via the Input terminal 10-C, the transmission signal via the input terminal TS-2 supplied. The AND gates 48 cause the data bits to be input into the flip-flops 49 via their marker inputs. The digital information stored in the flip-flops 49 is converted into one indicating the vertical address Analog signal converted and amplified to output terminal 19-J.

909847/088 *

Like from Pig. 19, the analog signals indicating the horizontal and vertical address coordinates become via input terminals 19-D -and 19-J to the input the summing amplifier 22 given, namely together with the respective analog signals indicating the horizontal and vertical displacement data.

When the jump command was processed, the analog signals of the deflection circuit of the cathode ray tube indicating horizontal and vertical displacement fed to the static deflection field in the tube for localizing an electron beam onto the first Set jump position 41 (Fig. 5).

The one in Pig. The control circuit shown in FIG. 28 is for reception of the next PC command in the table above. This next word is a repeating word and shows indicates that a white area of 0 magnitude, a white division area, and a black area of 100 units should be written seven times. To transfer this command from the direct access memory of the computer to reach the PC input register (Pig. 27) is the Generation of a REQ signal required. The access request plip plop 84 · was reset by the signal ZAD when the previous jump word in the PC input register has been entered.

The PC input register is for receiving the next PC command prepared by the monostable multivibrator 100, which sends a low-level pulse to an input of the NAND gate 96 is generated. This causes the other two inputs, which are normally at a high signal level this NAND gate generates a high-level pulse which is fed to the output terminal 27-M. This output terminal corresponds to the input terminal 28-M in Fig. 27 and applies this high level pulse to the

909847/0895

1971816

Marking input of the flip-flops 90, which are the PC input register form. This sets the flip-flops before further data is received from the memory output lines of the direct access memory of the computer.

The one with the monostable multivibrator 100 during processing The high level pulse generated by the jump word causes the AND gate 101 to be activated, which through the NOR gate 114 and the NAND gate 83 one Clock pulse is generated, which sets the access request flip-flop 84, whereby the signal REQ is produced. Furthermore, a counting signal is generated at the output of the inverter 115 and the output terminal 29-D.

The same signal change now follows between the data " Processing device and the computer, as it is in connection with the generation of the signal ZDO and the Signals ZAD has been described, which are used to reset the access request flip-flop 84, which the signal REQ ends. The counting signal at output terminal 29-D causes the in the memory address counter to be advanced stored address and prepares this counter for the processing of the repetition word the following operation. The repeat word is now in the flip-flops of the PC input register (Fig. 27) entered. The two code bits 10 assigned to the repetition word become that shown in FIG Decoder recognized, and that the Y / repetition flip-flop associated NAND gate 95 generates a low level signal which resets this flip-flop depending on the signal at the input terminal 27-A, while the other flip-flops are in their initially remain set.

It should be noted that the. Jump flip-flop, which was reset during the processing of the jump word, by "

90984 7/0885

the same pulse generated with the NAND gate 96 was set in its initial state, which is shown in Fig. cleared the PC input register shown.

The iteration flip-flop generates at its zero output a high level repeat signal that goes directly to the AND gate 145 is fed. This signal is also fed to output terminals 32-N, 33-0, 31-P and 25-Q. The one output of the repeat flip-flop produces a non-repeat level signal at the output terminal 25-R.

Referring now to Figures 4-E, 32 and 33, consider. The ten most significant bits of the repetition word relate to the desired white area, which is before the black area. This information is required in the horizontal offset register (Figs. 32 and 33). The repetition level signal becomes this used. As is apparent from Fig. 32 and has already been described, the repetition level signal becomes on of input terminal 28-N receive and control the input of AND gates 134. The other input of each of these AND gate is connected to the output of a flip-flop of the PC input register (Fig. 27), corresponding to the Bits 15 to 20. These bits give the white fine division information contained in the repeat word. As already mentioned, FIGS. 32 and 33 partially show one parallel binary full adder, the mode of operation of which is described in more detail below. Provisionally it is sufficient to state that the white fine division information to an already existing white fine division information contained in the addition part of the adder formed by the flip-flops 146 is.

The direction and the amount of the white area are shown with

909847 / 088S

in I ¹ Xg. 33 is processed depending on the repetition level signal received at the input terminal 28-0. As can be seen from this figure, the repetition level signal controls the inverters 149 via the AND gates 147 and the NOR gates 148 to feed bits 21, 22 and 23 of the repetition word with the horizontal jump displacement information, which in the manner described in the flip-flops 128 has been entered for storage.

The twenty-fourth bit, which indicates the direction of the white area, was processed in a manner similar to that other three most significant bits of the repetition word.

Since the horizontal Jump displacement information indicated by nine bits and since the white area of the repetition word is described by only three bits, it is an artificial generation of the six most significant bits to the three original bits of the white area information is required. These six bits are always zero. However, if a negative Whitening direction is given, the whiteness area is given as the 1's complement of the actual binary number. is For example, the amount of the white area 7 and the white direction positive and indicated by a 0, then is the binary number 0 0 0 0 0 0 111 fed to the adder and to be added with the horizontal distance However, the white direction is negative and indicated by a 1 as the twenty-fourth bit, so that of the adder supplied binary number 111111000 or the 1's complement the previous binary number.

The parallel adder used in the circuit of FIGS. 32 and 33 causes a storage of the running total of the horizontal relays determined by the PC commands

$ 9847/088

• - 62 -

g.erung during the generation of a respective character with that formed by the flip-flops 133 and 146 Circuit. The end of this adding process is the number present in the adder, while the addend is the number is the number entered, which when added results in a sum that replaces the Augend. The addition will done in two steps. The first step is a half addition. Every bit of the adder is complemented, if the corresponding bit of the entered number is a binary 1. The second step is a carryover, in which a carry bit is generated when a bit of the adder is a binary 0 and the corresponding input Bit is a binary 1. A carry bit is also generated if the bit present in the adder is a binary 1 and a carry bit is received from the next inferior position. After all transfers have been carried out the addition is complete and the adder contains the sum of the number entered and the previous number.

This type of binary addition is known and in more detail on pages 190 and 191 of the Logic Handbook, edition 1967, available from Digital Equipment Corporation of Maynard, Massachusetts.

To achieve these two operational steps is in the a pulse generator 150 is provided in the circuit shown in FIG. which consists of three flip-flops 151. These are connected in series, the 1 output with the Clock input of the next flip-flop is connected. The AND gate 152 forms an output of the pulse generator and supplies a transmission signal to the output terminal 33-D, which initiates the carry process described. At the output terminal 33-E, which is connected to the AND gate 153 is connected, a half-adding signal is generated which initiates the first of the two adding steps described.

909847 / 088S

1921818

The pulse generator 150 shown in Fig. 32 is turned on by a signal received by the circuit shown in Fig. 32 at the input terminal 31-D. This signal is generated every time the number of repetitions is entered in the repetition register (Fig. 31) and each time the information stored in the repetition register is decreased by one count. This signal is passed through the NAND gate 155, the output of which is connected to the marking input of the flip-flop 156. When the flip-flop 156 is in the set state, the pulse counter 150 is controlled with the oscillator pulses supplied at the input terminal OSC, so that it generates the desired carry and half-add signal at the output terminal 33-D or 33-E. These signals are also fed to the adding units 157, which contain two AND gates 15β, the outputs of which are fed to an OR gate 159. For the sake of simplicity, these adding units are shown in FIGS. 32 and 33 as simple function blocks 157.

The processing of the whitening bit, the white area and the white fine division area of the repetition word was described with reference to FIGS. 32 and 33. The rest of this word are the black area and the number of black repetitions desired. To adjust the black area information the black area register shown in FIG. 25 is used.

This register consists of seven ropes 198, of which each contains four AND gates 199, the first inputs of which are connected to a NOR gate 160. The outcome of the NOR gate 160 in each part 198 is connected to the input of a conventional digital-to-analog converter 161, whose output signal is amplified by the amplifier 162 and fed to the output terminal 28-G. The output of each NOR gate 160 is connected to the inverter

9 0 98 4.7 / 0885

163 inverted and the input signal to one of the NAND gates 199 supplied. The function of each director is similar to that of a latch circuit that begins ßioii is in the retracted state by the action of a pulse supplied by the monostable multivibrator 164 will. This is controlled with a pulse of the AND gate 165, which monitors a number of signal states, the will be described in more detail. One of these conditions is the signal level of the repetition level signal at the Input terminal 28-R. During the processing of the repetition word, this repetition level signal has a high level. In connection with the other inputs of the AND gate 165 thereby becomes the output of the multivibrator 164 are high. The same repetition pulse received at input terminal 28-Q controls the AND gate 199, which is the eighth bit in the PC input register assigned. In a repeat word for the letter L, the eighth bit is a binary 1, the the associated AND gate 199 turns on and generates a low level signal at the output of the NOR gate 160. This low level signal is inverted by the inverter 163 and causes the corresponding signal to be turned on AND gate 199t that is assigned to the output of this inverter.

The procedure described in the previous paragraph is repeated for each part 198 of the black area register, as a result of which a signal is low at the output of each part Level generated depending on the respectively assigned binary bit of the black area of this repetition word will. As already described, the output signals are used of the seven parts 198 of the black area register is converted into an analog signal which is amplified and fed to the output terminal 28-G. This amplified analog signal is a puncture of the number of black areas that are desired for a track

_ηηηΛ 'BAD ORIGINAL

. ; .- .9 0 9-8.4 3 / .0-8 8 5

If the track is taken into account, it is on hand 28, 13 and 16 to be understood.

Daa verified analog signal from the output dea black area regiatera (Pig. 25) is fed via an input terminal 25-G to a black area comparison circuit 165 which is based on usual way is formed · Daa analog signal is im Comparator 154 is compared with an associated signal, daa is generated with the integration amplifier 166. The input signal to the Veratärkera 166 is via a Analogue age 167 led, which is controlled in a complementary way to analogue age 168, which is shown at Sehlieaaung the integration avatar 166 briefly leaves. The analog ages 167 and 168 are connected to the Auagangaaignal of the NAND gate 169 and the inverter 170, the aea Auagangaaignal inverted, controlled. Before considering the type of control, "Figs. 13 and 16 will be explained. in which the signal source is shown on which the integration amplifier 166 (Pig. 28) works.

Ouch the pig. 13 and 16, the daa horizontal velocity region and the speed digital to analog converter show iat to recognize that depending on a suitable transmission signal at the input terminal TS-3 and a Start signal daa NAND gate 171 (Fig. 13) is driven and an input of the thirteen most significant bits of the Horizontal bottom line from the main input port - giater (? ig. 9) into the Horizontalgesehenzearügiattr causes Daa Startaignal and the transmission oaign »! at the The TS-3 input terminal is connected to the Pig. IO shown Tax compliance generated in a prepared manner. As can also be seen from Pig, 13, there is a horizontal gaach speed controller aua thirteen flip-flops 172, their! exits are connected to each other and to output terminal 16-A * "

_BA D

909847/081 $

The zero outputs of the flip ϊΐορε 1? 2 are with each other and connected to output terminal 16-B · Furthermore, the Zero outputs of the flip-flop monitored with three AND gates 173, the outputs of which are jointly routed to output terminal 19-F, Da3 signal at this output terminal is the non-signal HEI, ea is connected to the inverter 174 inverted and the output terminal 19-E as the signal -HEL .. fed. This signal indicates the presence of a horizontal speed value a in the horizontal speed controller (Pig. 13).

This register generates two additional output signals at output terminals 16-0 and 16-D twenty-fourth bit determines iat “This bit is dated Main input register to the set input of flip-flop 172 fed. The signal at output terminal 16-G is on Signal high swell when the Kc3? Ison1 »? Ä- \ gi39 speed, is positive and is bössiclmat as signal HVS, while the other signal dea ssitgegengese-fcs-feess f © gel has and ala:;.

en 4 © ff Äuagangsfeleaa® 16-A parallel generated Horizon-

w \ s * $ _r al3 3ingcmgssignal over the 13-A am Qeschwin set in Hg _{9 IS daygsgtell}

. In a similar way. At the Horiaontalge »16-B ®r *. dt3? : U; fig » - Ü ^ aaeften S.chml-

practice » this basic practice & lfSBS © 13-B zugefühyi! ·

on g

te® 11% wandelt & m horieontal
in an analogous 3igaal ua _f daa with a @ a Ve * a-ta * fc «r · 176 - ■ and at the output kl amu © 28-B § © is filled ...

BATH ORIGINAL

909347 / OISS

The third amplified analog signal is a function of the desired Horizontal velocity and is fed to the integrating amplifier 166 of the Pig. 28 circuit shown via the analog switch 167 and the input terminal 16-H fed. This signal is integrated with amplifier 166 so that there is a rising signal for comparison with the signal at input terminal 25-G is generated, the black area marked with the repetition word indicates * The comparison is made in comparator 154.

As has already been described with reference to FIG. 3C, the Horizontal velocity can be either positive or negative »depending on the movement of the electron beam either depends to the right or to the left. If the speed has negative sighting from right to left, the binary number representing the speed as a 1's complement

"The circuit shown in FIG. 16 contains this äWith HAHD gates 178 and 179t each of which is an input signal receives via terminal 10-J, which is connected to the flip

'.' ■ ' ίΊορ 70 (Fig. 10) is a high level signal generated during the photo composition operation. The NAND gate 178 receives the HVS signal at the input terminal 13-C, which is a high level signal when the horizontal speed

y _ \ -.-..'- '■. aipeit is positive. Gradually, the NAND gate 179 ' input terminal 15-D receives the non-signal HVS, which at

Speed has a high level. Both ΗΑΪΓΡ-ßatter 178 and 179 have an additional input provided, which is driven by a signal generated in the circuit according to FIG. 8, which is shown in the following is briefly described.

The inputs of NAND gates 178 and 179, which are connected to the Input terminals 28-S and 28-T are connected with connected to the flip-flop 127, which is in the set state High level signal at output terminal 16-S, and on. Low level signal generated at the output lever 16-T.

90984 7/088 S BADORiGlNAL

This flip-plop monitors internally with the set input associated AND gate the fourteenth bit of the jump instruction, which is the sign of the black direction in the following Indicating repetition and black and white words. The control circuit for this flip-flop 127 is designed in such a way that only the inverted form of the fourteenth bit is taken into account will. In addition to the signal for the AND gate assigned to the set input of this flip-flop, the one at the zero output the jump pulse generated by the jump flip-flop is also monitored. In this way, the set input is maintained the processing of the jump word triggered * if the fourteenth bit of the jump word is a binary 0.

Referring to Fig. 4G, recall that a binary 0 indicates a positive black direction, that of runs left to right, while a binary 1 indicates an opposite, negative direction.

The flip-flop 127 is therefore set and generated at the Output terminal 16-S has a high level signal for a jump word in which the black direction is positive due to a binary 0 is shown. This setting process is carried out by a clock pulse that is generated with the NAND gate 180, which is an input signal from the 1 output of the EPC-Plip-Flop receives, which has a high level during the processing of a jump word. The other input i signal of the NAND gate 180 provides the output of the NAND gate 80. From the description of the step jump word and the jump word it follows that the flip-flop 76 during the Processing of the step jump word is set and during the processing of the jump word that follows it, is reset. Therefore the input signal is: for that NAND gate 80 from the zero output of flip-flop 76 during processing of the jump word high while the other input signal for the NAND gate 80. from the output of the multivibrator 97 a level conversion from low

90984 7/0885 BAD ORIGINAL

to the high state and back because this multivibrator generates a high level pulse. The trailing edge of this The pulse forms at the output of the NAND gate 180 the input of the inverted form of the fourteenth bit of the jump word clock pulse required in flip-flop 178

A high level signal is therefore applied to the output terminal 16-S and a low level signal at the output terminal 16-T produced. Both indicate that any black area, which is processed after the operation of the flip-flop 127, in the positive direction or from left to right runs.

In the circuit shown in Fig. 16, the high level signal is applied to the input terminal 28-S, while the low level signal is applied to the input terminal 28-1. Assuming the letter L chosen as an example and a low level HVS signal to indicate a positive horizontal speed, NAND gate 178 receives two high level input signals and one low level input signal, resulting in a high level signal at its output. The NAND gate 179 also receives two high level input signals and one low level input signal, thereby generating a high level signal. The high level signal at the output of these gates is fed via the driver circuit 181 to the AND gates 182 which are assigned to the 1 output of the flip-flops 172 of the horizontal speed register (FIG. 13) and to the input terminal 13-A in FIG are connected. This means that the binary number indicating the horizontal speed is fed to the digital-in-analog converter 175 via the AND gates 182 and the NOR gates 183 and converted into an analog signal which indicates a horizontal speed value which is amplified by the amplifier 176 and the exit

909847 / 0S8S bad original

input terminal 28-H is supplied.

Bs should be noted that the digital-to-analog converter 175 receives the 1's complement of the speed value through the inverting effect of the NOR gate 183 that however, the converter itself generates a signal that corresponds to the original binary number of the speed.

The outputs of NAND gates 178 and 179 become also fed to an inverter 184 which converts the high level signals into low level signals, whereby the AND gates 185 'the zero outputs of the horizontal = are assigned to the speed register. These zero outputs carry the 1's complement of the speed binary number to input terminal 13-D.

That in the above Üafa-83.1? for the letter L chosen as an example, the * V / iec o ^ retrieval word is thus "processed" with the data processing device according to the invention up to the following degree "bus sign bit of the white" * ⁴ direction and the amount of the white area as well as the Vi3iss-Peinteilimg3ber © ie .h (all of which are marked by zeros) is old am. in Pig. 32 and 33 * shown horizontal offset register "received"; the amount of the Sohwarzb © reich is received with the Seliwarzbereichregister (S ¹ Ig, 25) imd i »-l? i analog signal, daa dea gohwarsberiiofaswrgltiuher 154 (Pig. 28) is fed to the Hbri _{previously shown in Hg 9 13} ~ zontalgeschwisdig & © itsregisi; ®r entered horizontal speed = * speed value A? fc with the digi-tsl "Analog Conirerter for di © Gsschwindigksit" shown in Pigs 16 and the result of this conversion was processed with the integrating variable 166 (Fig. 28 ) recovered *

Before a Erläutornng the effect ä®a Auegangseigaals. Compare era 154 for a Vargl ^ ioh swiesheii den

19? 1816 - 71 -

the analog signal indicating the desired black area and The type of control of the display switches 167 and 168 is described with the integrated speed signal.

As has already been stated, the AND gate 145 when the repetition flip-flops are reset at the beginning of the Processing of the repetition word with the one at the Hull output this flip-flop occurring signal is driven high level. The other input for this AND gate is at the input terminal 31-D, that of the output terminal 28-D of the retry register in FIG. 31 corresponds. As will be described in connection with the desired number of repetitions, »has this signal a high level in this operating state. This creates a high level signal at the output of the AND gate 145 »which controls the AND gate 186, the output of which is connected to the NOR gate 187. The other entrance dea AND gate 186 is connected to NOR gate 188, that monitors the output signal of two AND gates 189 and 190 » The AND gate 189 monitors the two signal levels ati the input terminals 30-D and 32-J.

The input terminal 30-B corresponds to the output terminal 28-D of the step register in FIG. 30. Y / ie already carried out this signal is high when the Contents of the counter part formed with the flip-flops 105 this register is zero «This is the case before a scanning end signal is received at terminal 28-G of the Step registerSo therefore has the output signal at the Klemiae 28-D goes high, causing the AND gate is controlled via the input terminal 5Q-D (Fig. 28).

The input glue 32-J corresponds to the output clamp 28-J in Fig * 32? in d © r the horizontal offset register is shown. As can be seen from this figure, the OUTPUT terminal 28-J has during the generation of a transition

9Q984 770885 ^{BAD 0PJG1HAL}

carry signal with the pulse generator 150, which is used for binary addition the horizontal offset information is used in the manner described, a high-level signal. Therefore is on of the output terminal 28-tf in response to the activation of the pulse generator 150 by the non-repetition pulse signal immediately thereafter a high level signal which is sent to one input of AND gate 189 (Pig. 28) via the Input terminal 32-J.

The appearance of these two high level signals on the Inputs of the AND gate 189 opens this gate'-and generates a high level signal at the output of NOR gate 188. This controls AND gate 186, whereby a high level signal is produced at the output of the NOR gate 187.

The trailing edge of the input of AND gate 189 over the carry pulse applied to input terminal 32-J generates a clock pulse for the monostable multivibrator 191, which has a high-level pulse at its output generated whose trailing edge a second multivibrator

192 controls which a low level pulse on an input of the NAND gate 169 leads. The other input of this NAND gate 169 is with the output of the NAND gate 193 connected. This NAND gate 193 monitors the output signal of the NAND gate with one of its inputs 169 as well as the exit shark of the NAND gate 194- which together this one input of the NAND gate

193 are supplied. The other input of this NAND gate is connected to the output of the NAND gate 195. This in turn monitors the output signal of the NAND gate 194 * 196 and 169. <

Recall that in Pig. 28 shown flip, Plop 127 because of the positive ones indicated with "the jump word

'BADORiQHsSAL 909847/0885

Hichtuhg des Sehwä ^ zböreiches would be set The high level signal at an input of the NAND Öattera 196 and a low level signal at an input of the NAND gate 194 generated * The JiAND-Ga "Her 194 receives also a signal from the output of the Schwarzbereldhs comparator 154 'Which one in the absence of comparability has a high level * This non-comparison signal is with inverted to inverter 197 and fed to the input of NAND gate 196 as a low level signal. In this way hewirlct the positive generated with the multivibrator 191 Pulse a high level signal at the output of the NAHD gate 169 and a low level signal at the output of the inverter 170, whereby the analog switch 16? closed * the analogue age 168 is opened »This controls the integrating amplifier 166 and generates a rising Signal which is an I ^ inction of the via the input terminal 16-H received analog speed signals. This increasing signal continues * until its eye-sight amplitude is practically equal to the amplitude of the analog black area signal at the input KiemmS 25-G. If this is the case, the comparator generates I54 Low level signal on NAND gate I94f and the inverter 197 inverts this signal to a high level signal at the input of the NAND gate 196, Däduroh will NAND gate 169 blocked and a low level signal at its output it generates the analog output 167 opens and the analog switch 168 eohliaflt, where # i the integr end of amplifier 166 is reset #

Wi0 would already be carried out, the signal generated at the output of the amplifier 166 and fed to the outputBklemmö 2.Ö-2 * is further amplified by the amplifier 141 in Mg * 20 and optionally fed to the amplifier 143 via one of the Anslögsöhäli 142, which is fed to the output 19-Ä ar-This signal is delivered again with the amplification * 198 βά the output a ^ lejMi 34-0 in Jig «Ϊ9

BATH ORIGINAL

produce "the ait of the" diversion shown in Pig, 34 to control the deflection system of the cathode-dial tube connected is. The final ascending «Abienkungsaigjiäl * that is fed to the cathode ray tube, has a "sufficient duration and length to pass the electron beam move the desired number of area units, for example over 100 units »

At the end of this first trace of the repeated word, in As described, the analog switch 167 is opened by the NAND gate 169 and the analog switch 168 is closed. Closing the switch 168 causes a short circuit of the integrating amplifier 166 »which resets it. This moves the electron beam into its first horizontal position 41 (Fig. 5). Y / ie is highly declared, takes place this return also during a vertical deflection.

For such a movement of the electron beam to generate it ate 8chw * 3P3bir © icha or. If there is a visible trace on the Sehina et Kathodans ixahlrötoe, the beam inside the tube must be lighted. This is done mil; the iß fig * 19 and 2Ö shown «$ t # Hteä circuits.

2a jitYr9 * e «fcif ^ MtQZ% 4ss HAOT-0att $ r 169 cloth tinfü Au0gangii» pi3li a & dl «tlf &&#l9-> f» while Inerter ltd 'tin SigÄml an dl «Äms ^ ngslclesiiio 19-W ^ *' in fig »19« ntap? «®ht! i aim $ Auagaiigeklemcien 'BinganfelcJlMBeoA 29-? mä 28-W · Hitr iat au recognize / '. da® Äuogangsiigiml- ά · β.ΙΙΑ1Γ0-Ο * - | 1ι · τθ 169 an input d * ö. HAH3} ~ Öattera 200 is suggested, while the output signal of the inverter 170 'dineoi.Eingsxig- the SAND-Öätters 201 is performed «Di« a $ btid © a IAHD- (Ja-lt @ ^ are tiit their outputsn T «rbundt» u »4 ^ rasugen #in gsatliisaatä Singätiga * ii? dea Multititeft-iov aö2 uni 4en ^ iüsss singing-; ··.« a

11s 4 1Ί ο ι i ι ^BAD

4 1Ί

NAND gate 203 * The second input of WAND gate 201 is connected to the output of NOR gate 204, which generates a low level signal during photo composition operation, as can be seen from the description of vector operation. This low level signal is inverted by the inverter 205 and fed to the other input of the NAND gate 200 as a high level signal. The third input of the NAND gate 201 is connected to the zero output of the flip-flop 206, which is controlled with the blanking bit in the words SSEP and SSGZ (Pig. 5H and 3J). This zero output normally carries a high level signal during potentiometer composition operation. When porting the operation of the integrating amplifier 166 in Pig. 28, ie when the analog switch .167 is closed and the analog switch 168 is opened, a high level signal arises at the input terminal 28-V, while a low level signal arises at the input terminal 28-W. These signal states, together with the other input signals of the NAND gates 200 and 201, generate a low-level signal at the outputs of these HANI chatter. As has been explained with reference to FIG. 8H, when the outputs of two NAND gates are connected, a low-level signal at one output causes the same signal at the other output. Therefore the input of the NAND gate receives £ 03 * the; where the outputs of the NAND gates 200 and 201 are connected, likewise a signal of low level.

Before the signal level was increased at input 28-V »led the offsets of NAND gates 200 and 201 have a signal high Levels. Therefore, when the signal was transitioned at the terminal 28-V high at the input of multivibrator 202 creates a falling pulse edge that generates a pulse caused a low level at the input of AND gate 207. The other output of the ilul ti vibrator 202 produces one High level pulse whose trailing edge triggers the multivibrator

0 9 8 4 7/0885 ^BAD

208 activated. This generates a low-level pulse at the other input of NAND gate 205. The low level pulse occurs coincident with the low level signal at the output of the NAND gates 200 and 201 causes an and " a high level signal at the output of NAND gate 203 which has the same timing as the high signal Level at the output of AND gate 207. This signal is designated as a light key pulse and the control electrodes Cathode ray tube fed to generate a tracer and affect the distraction. It should be noted that this light button signal is delayed by approx. 1.5 microseconds .The leading edge has what the multivibrator 202 is used for. The light key continues until the output signal Both NAND gates 200 and 201 become high, which is the case when the black area comparator shown in FIG 154 assumes a comparison state and the integrating amplifier 166 for black keying turns off. At this point the signal at the input terminal 28-V returns to its initial state low level, the signal present at the input terminal 28-W in its initial state of high level back, producing a high level signal at the output of NAND gates 200 and 201. This locks that NAND gate 203, whereby the'Helltastimpuls simultaneously ends with the end of the track.

The light key pulse generated by the AND gate 207 (FIG. 19) is also fed to the output terminal 28-B. In Pig. 28, this terminal corresponds to the input terminal 19-B, which is connected to the NAND gate 209. That other input signal "of this NAND gate is via the Input terminal 10-1, it is connected with the one shown in Fig. 10 \ generated flip-flop'70 and has a high level during dec operation required to generate the desired letter. Therefore, the initial of the IiAIiD gate 209 before the generation of the Helltast-

_nnnn BAD ORIGINAL

. _see .909847 / 088 5

19? 1816

: .... j vises a high level, and along with the front - .. 'lanke of the light pulse is a trigger signal with the ivAMD gate 209 generated, which activates the multivibrator 210, This then generates a high-level pulse which is fed to output terminal 30-0. This impulse corresponds the end-of-scan signal, which was already mentioned in connection with the explanation of the in Pig. 30 called the circuit shown became.

From Pig. 30 shows that this scanning end signal is received at the input terminal 28-C and causes a setting of the flip-plop 108 and an input of the binary data indicating the step value into the counter part. The step value is stored in the memory part formed by the flip-plops 104. Upon receipt of the end-of-scan signal, the step counter starts counting down the step value until the value 0 is reached. At this point in time, a signal is generated at the output terminal 28-D. The use of this signal is described in more detail with the explanation of the processing of the black-and-white words. In addition, the AND gates 211 and 212 monitor the zero state of the Plip-Plops 105, which form the counter part, and generate a high level signal at the terminals 15-A, 24-B and 28-C. This signal is referred to as the end-of-step signal (EIS). It is also used within the in Pig. 30 for resetting the flip-plop 109 »whereby the generation of the oscillator pulses for the counter part is terminated. ^{Perner generates a signal of high level at the output terminal 15 - 1} E when the flip-plop 109 is reset and a zero state is set in the counter area with the NAND gate 112.

The following is part of the vertical offset register for poto composition operation using the Pig * 15 be ** wrote »The step so posture in the vertical direction

'909847/0885 BAD ORlGiNAL

1 ^C J? 1 81 6

• - 78 -.

for vertical displacement after completion of a track with the signals at output terminals 15-A and 15-E of the in Pig. 15 effected step register. before the input of the step value in the Pig. 30 had the signal at output terminal 15-A a low level due to the output signal of the UMD-G-atters 211, which is a low level signal at the 1 output of the flip-plop 109 detected. The signal level at the output terminal 15-E had a high level due to the Effect of the NAND gate 111 due to the signal is low Level at the l output of the Plip-Plop 109.

In Pig. 15, these signal levels are received via input terminals 30-A and 30-E, so that the low level signal at input terminal 30-A is applied to the inputs of NAND gates 214 and 215 causes a high level signal to be generated with these NAND gates. Both outputs are connected to each other and applied to one input of NAND gates 216 and 217. The NAND gate 216 may be referred to as a counting gate and generates a high-level count signal whenever vvif a step movement in the vertical direction is to displace the electron beam in the cathode ray tube. Initially, however, this count gate 216 monitors the high level signal at the output of NAND gates 214 and 215 as well the high level signal at input terminal 30-E. Therefore, these two high level signals generate a count signal low level, which is the level input of the Plip-Plop 124 in the Pig. 15 and 14 associated AND gate is fed. Like from Pig. 15, this counting signal is at the output terminal 14-G »that of the input terminal 15-G in Pig. 14 corresponds. Therefore has during of the initial period before the step amount is saved in the memory part of the Pig. 30 circuit shown the count signal has a low level, whereby the clock input of the Plip-Plops 124 of the vertical offset register.:in

90984 7/088 5 BAD original

14 and 15 is blocked. As already in connection with the description of this offset register has been carried out, its logical function is similar to that of an up-down counter, where the counting direction is determined by the output of the flip-flop 120 shown in FIG is determined, which is controlled with the sign bit of the step direction, which in the jump command on the third Bit position. The 1 output and the zero output of the flip-flop 120 are connected to a counter evaluation circuit 218, which consists of two AND gates 219, the outputs of which are led to the input of the OR gate 220. The exit of the OR gate is led to a driver stage 221, which sends a signal for the set input and the reset input AND gates associated with the respective flip-flop 124 are generated. The output of OR gate 220 isc also fed as an input signal to AND gate 219, which is provided in the next counter evaluation circuit 218. The operation of the offset register during the Vertical steps is controlled with the count signal at the output of the NAND gate 216. As explained with reference to FIG remains, the outputs of NAND gates 211 and 212 remain upon receipt of the scan end signal and storage of the counter part of the step register high by the set flip-flop 109. The output however, the NAIID gate 111 changes its level to one low value via the input terminal 30-E in Fig. 15 the NAND gate 216 turns on, producing a count signal high level is generated at the output. This counting signal opens the clock part of each of the plip-flops 124 and enables the offset register to be controlled with the oscillator pulses sent via the OSC input terminal (Figs. 14 and 15) are supplied. The effect of these oscillator pulses is that the content of the offset register "* depending on the state of the plip-flop 120 upwards or else "'is chosen." This counting process is set for '' the duration of the counting signal to Auor.aiig des!. 'AlID-Ga

\ > / §0 915 A 3 0 OB 8 5 BAD

19-1816

216 continues, its duration in turn, the counting duration of the counting part of the step register shown in FIG. 30 to the state zero, for which purpose the same oscillator pulses. as used in the vertical offset register.

The vertical step control from the vertical offset register is via a digital-to-analog converter 125 and a Amplifier 126 (Fig. 15) applied to the deflection circuits shown in Fig. 34.

It is summarized that the generation of the initial parts of the letter L was carried out, the IASS step jump word is processed and that the next jump word was also _processed; to inflate the electron beam in the first jump position 41 (Fig. 5). In addition, the next computer command, in the repetition word, has been processed, and the electron beam has been> ^ e% above; $ branched and moved 100 black units to the first jump position 41 to the right. At the end of this track, the electron beam was blanked and brought into a position which is shifted above the first jump position by an amount determined by the data of the step jump word. The next tracks determined by the number of repetitions specified in the repetition word can now turn in a similar way to the first track.

In order to complete the description of the processing of the repetition word, the exploitation of the third through seventh bits of this word. As already stated in connection with FIG. 4-E, serve these five bits to identify the number of tracks to be generated with a single repetition word. These bits are put in the repeat register shown in FIG through AND gates 230 by the signal ZDO entered, which is supplied via the input terminal ZDO will. The eleven bits are also used to control the input

909847/0885

ORIGINAL BATHROOM

1971816

ο- being combination, that of that shown in Fig. 28 ■ Attention to the other two inputs of the AND gate

;. yes we will. As shown in FIG. 31, the

Bits passed through the AND gate 230 to the marking input of five flip-flops 232, which are connected to the AND gates 233 form a down counter ". The content of this counter is calculated for each coincidence of the sampling signal at the output terminal 31-X in Fig. 28, which corresponds to the input terminal 28-X in Fig. 31, with that at the input terminal 28-P received repetition pulse reduced by one step, The NAND gate 234 evaluates this coincidence. The AND gate 236 monitors the zero output of the flip-flops 232 and generates a high level signal when the counter has reached zero. This signal is sent to the inverter 237 inverted and as a signal low sweep given to the output terminal 28-E. Furthermore, the inverts Inverter 238 the output of AND gate 236 and leads it as an input signal to the NAND gate 239, - its Output to terminal 32-D. This NAND gate generates a pulse of • low 'level every time when the counter has executed a counting step. This is done by triggering the multivibrator 240 on each Counting step signal at the output of the NAND gate 234. That NAND gate 241 delivers this pulse to the multivibrator 240 and monitors the counting signal and the output signal of the AND gate 231 via the inverter 242.

It can happen that the repetition word identifies the number of 0 repetitions. In this case, a signal is generated at the output terminal 32-Q via the inverter 243, which identifies this state KMnziäöniT of the input pulse from the output of the UID gate ^ 231 with: the high level signal from the Äüs'gahg ^? Of the AND gate 2 * 36, "the" with "the AND gate; 244 is established. As will be explained, "this""signal * 'is used to generate a" display the next word

1 9: ^j 1 816

send signal to initiate another access request to effect. . "

From the description of the repetition register shown in Mg. 31 it emerges that a track marked by the black area disinformation _{y of} the repetition word is generated as often as is given in the repetition word. Each time the track is created, the content. of the repetition register is reduced by one counting step _: until the state 0 is determined with the AND gate 236 and a low level signal is generated at the output terminal 28-E, which leads to the input terminal 31-E in FIG. 28-ge ~ ' ^: will. This signal is used to block the AND gate

The one at output terminal 32-B. Occurring signal of high level when the counter content 0 is determined in the repeat longitudinal register by the NAND gate is the in -H ¹ Xg ₀ ; 52 'shown horizontal offset register via' the input ': terminal 31-R.

The NAND gate 250 monitors these signal levels at the · - - ~ Input terminals 28-lf and 31-R, which with content 0 des- ¥ le - .. ^ repetition register fill both high-level signals .'- ä-These are "monitored with the AND gate 250- · which -" K likewise the Sigiia ^ l lying on the input terminal 28 ^ Y " monitored; - '- ^ - "- ■.-... ^. i:: -...,?

As can be seen from FigV 28 ", this input ^ - · terminal corresponds to the ^: A ^ gangskienime" ■ 3 & ή [ψ _: d | ii ^J with-dem- ·

des tlÖ-GaSfer ^^

holds elnerL state notes ³ BegelBy- mentt ⁱ - ^ _f s ⁱ '

counter (Fig. 30) assigned isif, tüld 'Ψβχΰά ■ dä.ö' ^ i ^ 156 in Fig. ^ 52 reset

8 it ΨΜΦ9 5 ORIGINAL INSPECTED

- - 83 -

When the trailing edge of the carry pulse occurs, the generator 150 is deferred. As a result, a high level signal is generated at the output port 28-K, which signal is fed to the input terminal 32-K connected to the input of the AND gate 190. Therefore , when the memory content of the repetition register is 0, the electron beam is controlled back and an end-of- step signal coincident with the high level signal is generated at the zero output of the flip-flop 156, as a result of which a high level signal appears at the output terminal 32-Y in FIG.

This high level pulse is applied to the input terminal 28-Y in FIG. 32 and is converted by the NAND gate -250 into a pulse of low level indicating the next word which is applied to the output terminal 28-S. This pulse indicates in a manner to be described that a repetitive or black-and-white word has been completely processed. In this way, the access request flip-flop 84 can be set to indicate another access request signal for the computer.

In the circuit shown in FIG. 28, this pulse indicating the next word is received at the input terminal 32-3 and inverted by the inverter 251, which controls the AND gate 252 and in this way generates a clock pulse for setting the access request flip- Flops 84 generated. Furthermore, a counting signal is generated at the output glue 29-D, which causes the address stored in the memory counter (Fife. 29) to be shifted by one step. The pulse indicating the next word is also passed through the driver 253 and generates an output pulse for the output Kiem..ie 27-WU at the NAND gate 96. As already explained, this output pulse is used to transfer the repetition flip-flop to its set start .status, and for deleting the contents of the PC input register, see chap. (Fig. 27) so that it is ready for the next word from the computer's direct access memory.

I E BAD ORIGINAL

1 9? ι 8 1 6

There is a jump command, a step jump command and a repeat command with regard to their processing and puncture in the data processing device according to the invention is an equally detailed description of the creation of those parts of the The letter L is not required, which basically contain similar functional steps. Therefore, the description will now be made of the generation of the Te-.Is shown in FIG F of the letter L.

As can be seen from the table above, the part F of the letter ^ by processing a number Realized black and white words after a jump command. The following is a full description of the invention the processing of a single black and white word explained with its two parts, using the first black and white word listed in the table.

First of all, it should be noted that this is the first black-and-white word previous jump word for part F the electron beam brings into the \ ierte jump position 44, which is shown in FIG. 5 and Figure 7A is shown. Assuming that the black and white word is in the PC input register (Fig. 27) is entered and its two least significant bits have been decoded with the decoder shown in Fig. 28, the black and white flip-flop reset.

This will cause the low level pulse with the multivibrator 255 generated at output terminal 32-Z. The signal high level at the zero output of the black and white flip-flop, \ velches is referred to as a black-and-white level signal, is used to control an input of the AND gate 256 and der'UND gates 257, 258 and 259. It is also referred to the Output terminals 32-EE and 33-FF.

In the Γη'Fig. 32 horizontal offset register shown . - -, -! - .- ■ .-. · .. 9-0 9 3 4 7 / ij ^ 'ggr - - BAD ORIGINAL

19 71816

three tOTD gates 266 are provided, the third to thirteenth bit of the black and white word in the PC input register (Pig, 27) monitor. These gates state when the second part of the black and white vortex contains meaningful information and eleven binary ones is marked, Since the SchwaFS-Weiß-Wart specified in the table contains information in both parts, the outputs of AND gates 266 carry a low level signal that inverts with your inverter 267 and as a high level signal to an input of the HEfD gate and output terminal 28-1.

This output terminal corresponds to the input terminal 32-Ϊ4 in. Pig, 28.J and its signal is fed to the set input d§s aps §70 3u§ ©, §rdneten WD ^ gate ^. The entrance of this IJTO ^ Ga.tters is wit the d.eg ^^ faaagp guriiqk provided Plip-flops 870 so d§, ß. 4th get ^ input of this Plip ^ Plops is controlled »The Ta ^ tiijigang is connected to the 8P7 via the inverter g.71, whose input is controlled by the signal (im 8öhwar ^ Weiß ^ Plip **? LQps, U & in . an.d§reg input signal is 4as the sampling "liidesignal _?

with 4§m Multi vibrator 210 when the lower edge occurs

at the HAIB-öatter 209 via the entrance, A high-level signal is produced by this. * Hence

wia? d, the ÜliD ^ dgttt ^ 35? at the end of the last

i mil? the end pulse high mm kpingidentical with the measurement of the QPS «Dahea? is the TQrdeyfXginfee äea over the InvertCT a? l a 870 »

Since d, 8ts flip-flop WlQ was initially zjurüakgeatellt »

§9 with the signal of the

of the driven, whee *? we then. his

SQ a 8 4 _{7/0 a 81 BATH}

! 921816

• - 86 -

Output before setting flip-flop 270 a signal high Generated levels. This arrives at an input of the AND gate 272 and at the output 33

From Fig. 33 it can be seen that the high level signal at the output terminal 33-DD drives the AND gate 273, the other input of which is connected to the input ^{terminal 28-Fi 1} vev-? is bound, which carries the Sehwarζ white level signal. The high level signal generated at the output of the UHD gate 273 is used to add up the whiteness of the first rope "the black-and-white word" indicated by the first twentieth _t - twenty-second and twenty-third lit., where the amount The horizontal offset is stored in the gumming part of the horizontal offset register, which is formed by the flip-flops 128. This is done by controlling the ül {D -? & atter 274, which with the NOiM * attern I48 and the Inyertern 149 verb; unde.n sinä _f Das, Yorzeichen des V / eiiäbei'eißhs, which is indicated by the yierund = twentieth bit, wi ^ d, wi? * D in a similar way

to the seahs most significant bits of the horir-.

Mmstliish gu produce like this em-τ in connection with the processing of the how · = erolng; occurring Y / ice area has been described «,

How be3 ei "fcs erläuter1;? _R is the gusmieirupgs ^ ^ or Anspei ehe.rungaprpgeß by the pulse generator 150 (fig i 3t) initiated by the cluroh the Multivibr ^ toa 25 | ifigf · 28} eraeugtea is pulse eingesehaltet, Piese.r impulse wiycl in d§i> ia Pig »32 bowed 3cnaltun.g over the Ein = *: gai) igs3Elejim # | 8 ^ · Ζ« ugefühii ?, Dadureii disfigures an impulse · =;

m output of NAND ^ Graiiters 155 "of the 156 aietssli and the generation dei" Halbaddition§ ^ and iflseyiiragaimpuise einlei1 in the manner described; e> _t?

Of? high pulse generated at the output of NAHD gate 155

BATH ORIGINAL

909847 / Q88S

ei Γ ί> f r ρ;

87 -

Level ^; 'w ± rfl'ie-rner: fed to output terminal 28-T. He will':-! the "iri '^ Ptgi 28 shown circuit at ■ -d'er.- input kleiar.e 32-T received and, together with the high level signal at the output of AND gate 259, generates a high level signal at the output of AND Gate 272 which "is fed to the output terminal to 25-AA.

The input terminal corresponds to the circuit shown in FIG 25-AA of the output terminal 2.5-AA in Fig. 28. As for the processing of the black area data of the With the repetition word, the high-level pulse causes the black area amount to be entered via this input terminal of the first part of the black-and-white word, seven bits indicating the parts 198.of-shown in "FIG Black area glsters. V / ie also already described was,: this information entered with the converter 161. and converted via the amplifier 162 to output terminal 28-G.

It can be seen from Fig. 28 that this corresponds to the o black area of the first part of the Sehwarz-.ieiß-.Vc-rteo corresponding , .., analog signal one. Input of the black area comparator 154 supplied .is; «. As with the repetitive word, a analog speed signal generated and with the integrating Amplifier 166 Amplifies until a comparison signal is generated with the comparator "154" which this Integration process ended. In view of the description already given of this part of the shown in Fig. 28- " th circuit .solL in the .following ledii? iieh the type of introduction: " of the integration process.

'V / ie "already.-filled-in-v / urde, controls the black-V, ^r eii3- ^^^ Qel ^ ifyi & ü

Output directly to de :: i clock input of flip-flop 262 comparable ■ 'l: is ^inhibited: which; a .stufe e ± newly. _: z;, veistafigen ^ Z-inlsr ^ forms, the other 3tufe by dac flip-flop 263 .rebjl-

will be. These FUp-I ¹¹ Iops were brought into a set initial state with the high-level pulse at the output of the AND gate 261. The AND gate 261 monitors the signal, normally of a high level, present at the input terminal B., as well as the signal ZAD of a high level at the input terminal of the same name.

As can be seen from Fig. 28, three AND gates 276, 277 and 278 monitor various outputs of the counter stages for determination of the processed part of the black-and-white word.

If both flip-flops are set, then flip-flop 276 generates a high-level signal which inverts with inverter 279 will. Its output is connected to an input of the NAJJD gate 280. The other input of the NAND gate 280 is connected to the output of AND gate 277 via inverter 281. A signal results from this high level on out / rank of the NAIID gate 280, whereby the AND gate 282 is driven. The other input of the MD gate 282 is with the high level signal at the zero output of the black-and-white flip-flop. Therefore a high level signal is generated at the output of AND gate 282, which is the input of another AND gate 284- is fed. This is also controlled with the output signal of the OR gate 188, which is the output signal dos UNif-Gattero 189 monitors and its signal high level at the end of a transfer step in the offset register which is indicated by a high level signal at input terminal 32-J. Since furthermore the counter portion of the step counter prior to receiving an end-of-scan signal did not receive the uohrittv.ert, that lies The signal at input terminal 30-D is also at a high level. Therefore, AND gate 284 is opened and generated a high level signal at the output of the OR gate

909847/0885 BADORlGfNAL

1921316

187, which coincides with the trailing edge of the carry pulse at the input terminal 32-J, changes to a low level. This falling signal edge activates the multivibrator 191, which generates a signal to start the black scanning integrator. The multivibrator 192 is thereby controlled in the manner described. The high level pulse at the output of the multivibrator 1 _; ) 1 also controls AND gate 256 and resets flip-flop 262, indicating that the first part of the black-and-white word has been processed. This situation is determined with the AND gate 277, which generates a high level signal. This is inverted with the inverter 181 and fed to an input of the NMD gate 280. This results in a high-level signal at its output and an injection of AND gate 282, the other input of which has already been activated by the black-and-white level signal. This results in a high level signal at AND gate 284, the complete opening of which is still dependent on OR gate 188. The high level signal at the output of the AND gate 27-1 is referred to below as the 01 count signal and is also supplied to the output terminal 32-GG.

The output terminal 32-GG corresponds to the input terminal 28-GG _1. The high-level 01 counting signal is fed to the input of the AND gate 268 via it. Since the second part of the black and white word is being processed, a high level signal is generated at the output of inverter 267. The other input of the AND gate 268 is controlled with the scanning end signal via the terminal 28-HH. This signal is given a high level when the black area scanning of the first part of the black and white word has ended and the ^x trailing edge of the light pulse controls the multivibrator 210 (FIG. 28). Therefore, if the scanning for the first part of the black and white vVor te s ended, a high level signal is generated with the AND gate 268, whereby am

90 9 S 4 7/088 S BAD

• - go -

Output of the NAND gate 155 a high level signal occurs, which ^{causes the E 1} Iiρ flop 156 to be set and the pulse generator 150 switches on in Pig. 28 is conducted, the inverter 271 generates a clock pulse to set the flip-flop 270. In this set state, the AND gate 256 is activated and generates a high level signal at the output 33-C0 »

As can be seen in FIG. 53, this signal is received at the input terminal 28-00 and passed through the opened AND gate 285. The output of the AND gate is connected to the NAND gates 2d6, so that the tenth, eleventh, twelfth and thirteenth bits of the black-and-white location, which correspond to the amount of white area and the direction of the white area, are supplied via inverters 149 correspond to the second 'part of the Black-V / white-V' / location. The summation tml of the horizontal offset register, which is formed by the flip-flops 128, with the circuits 157 and the half-addition and carry pulses at the input terminals 32-D and 32-E, a summation of the V / eissTo range ψ with the stored horizontal displacement (Offset) in the described manner »Simultaneously and without generating the transfer signal, the input signal at the UIiD gate 189 in FIG. 28 receives a high level via the terminal 32-J and generates a high level signal at the output of the OR gate 188 Activation of the AND gate 2841 which was previously activated with the 0 1 counting signal * This high level signal is passed through the OR gate 187 and actuates the when the carry pulse occurs. Multivibrator 191 for switching on the black scan integration amplifier 166, whereby the black area is processed for the second part of the black and white word.

BATH ORIGINAL

909S47 / 0 88S

When the AND gate 268 shown in FIG. 32 is driven with the O 1 counting signal to generate a signal high level at the output of the NAND gate 155 and switch-on of the pulse generator 150, an output signal is generated at the output terminal 28-T. This impulse high Level is used to drive AND gate 291 in Fig. 28 and generate a high level pulse at the output terminal 25-BB.

In the circuit shown in FIG. 25, this pulse is received at the input terminal 28-Eß and is used to input the seven bits indicating the black area in the second part of the black-and-white position into the parts 198 of the black area register. The digital-to-analog converter IGi converts this digital information into an analog signal, which is amplified and fed to the output terminal 28-G. This analog signal forms in the in Fip. 28 circuit shown, an input signal for the black range comparator 154, the zunef also iniegrierte analog horizontal velocity signal during the black region whose track or ^scan: is IHRT. V / ie in the black area of the first part of the. oohwarz-.Yeiß- '. Vorteo this SiQial is located on the Aungaii.Tol'leniMe 34-IvK.

As already oesoh-rubbed, the oi.-nal high from deu i. '. Ul ti vibrator lyi via the UIJD gate 256 to set the: flip-flop 262 and to hack the flip-flop 263 the two ^ i ¹ Jfigen 3in ^: narrators .used. Here, an i3i <; na3 iiohen level a :: i iv.iuv ~ an _f ~ of the AND gate 278 is generated, which is referred to as the 10-count signal and indicates that the second part of the ^ black - '. White- V / ortes is processed. The 10 counting signal is sent to the output terminal 32-JJ, which is supplied to the input terminal 28-JJ in the circuit shown in FIG. 32 shown corresponds. This signal causes the high level signal at the input terminal 26-Y, which together with the step end signal

909847/0 8 85

and generating the high level black-and-white level signal, a generation of the next word indicating signal am Output of the NAND gate 287, which is connected to the output terminal 28-S is connected. As already mentioned, this pulse indicating the next word causes the access request flip-flop to be set, which a new access request signal generated for the computer.

Then the next black and white word is processed and ■ repeats this operation until the entire part F of the letter shown in Fig. 5 is complete.

It should be noted that the second part of the last Schwarzi '/iss-V / ortes is not used to generate the part F of the letter and contains only binary ones in the table above. In this case, AND gates 266 in FIG. 32 generate a high level signal at the input of HAII) gate π 288, whereby the pulse identifying the next word at its output coincides with the edge of the step-scan desirpial at the input terminal 30-P occurs. In addition, the high level signal am / ran · ⁰ "of the IJIiD gate 266 is applied to the output terminal 28-M, whereby the actuation of the multivibrator 191 by the action of the NAND gate 290 is prevented.

Iiach the processing of the part for generating the letter N in Fi. "5 required Yfiederholungswortes and after Erzeup.uig an access request signal to the flip-flop 84, the" V / ort ErO in the PC ^{Eingangsrof-:} oter (Fi " . <_7) "- 'nr.ezehen. I.iit the decoder in Fig. Wirci dao EPC-V / crt aOiiodiert and bev / irkb a reset of the Ei'C-Flip-FloLS. The falling edge at the 1 output of this flip-pile triggers the LiuI vibrator 293, which sends a low level signal to the output terminal 10-F erzeup "; and to the Z'njvaxir. Dos inverter? 94

9098O / 08SS BAD ORiGSNAL

1?? ^] 8

-, 93 -

The inverter generates a high-level pulse at its output, which is sent to the computer and represents a PC interrupt signal which terminates the photoconnection operation. The low level signal at the outlet terminal 10-F is used in the scarf shown in FIG. 10. ⁰ : to reset the flip-hop 70 which has remained in its set state during the photo composition operation.

Awake of the description of the dc3s fofco composition operation with the The device according to the invention is hereinafter referred to as "vector operation or, the graphic operating mode is described.

As already stated, the inventive Data processing device vector information as well Process alphanumeric and semitone anal ο '? data. at The processing of vector information are two modes of operation possible:

1. the generation of vectors with constant deflection speed,

2. the generation of vectors during a constant Period.

'' The first operating mode is called SSBP mode, v / which has already been set out in connection with FIG. 3H. This abbreviation means "start with stop at the end point", what characterizes the conditions in this operating mode. The beginning of a vector is indicated by the in Fig. 3 and 4 registers shown stored horizontal and vertical addresses are defined. The end point of a vector is through the registers shown in Figs entered horizontal and vertical endpoints defined, or by the words shown in Figs. 3B and 3E LHER and LVER. In this way, a horizontal and a marked a vertical coordinate. It will be a

BAD ORfGi-MAL 909847/088 $

ι q? ι 8 1

horizontal and a vertical increasing deflection signal generated until the signal size corresponds to the analog Si. ₍ corresponds to jnal, which specifies the desired coordinates or end points. The vector obtained from this is the desired vector. This then runs from the start address to the intersection of the end point coordinates.

This operation is discussed in more detail in connection with the in Fig. 19 described circuit shown. This is however, a few preconditions must first be considered.

The first step is to enter the horizontal and vertical addresses in the respective registers. this will achieved by a signal EOH-I, which is a required for entering the horizontal and vertical address Start signal generated. The thirteen most significant bits of the words LHAE and LVAE are used for input depending on Transmission signals that are sent to the input terminals TS-I and TS-2 of these registers occur. As is apparent from Figs. 11 and 12, this digital information becomes an analog signal supplied to output terminals 19-D and 19-J.

The second step is the input of the desired horizontal and vertical speed in the in Fig. 13 » and 15, with which the vectors are to be written in this operating mode. For the Horizontal speed, this is done in the manner already described for the photo composition mode. the Vertical speed is treated in a similar way. In the circuit shown in FIGS. 14 and 15, the Input terminal TS-4 supplied a start and transmission signal, whereby an input pulse is generated at the output of the AND gate 300, which controls the AND gate 301 and inputting the contents of the main input register corresponding to the twelfth to twenty-fourth bits via the

BATH ORIGINAL 9 0 9847/0885

1 Q ') 1 P 1 β - 95 -

NOR gate 122 causes flip-flops 124. Since the twenty-fourth bit indicates the sign of the vertical speed, the signal levels at the output terminals 19-P and 19-Q indicate this sign. If the flip-flop 124 connected to these output terminals is set, the sign bit was a binary 1, which indicates a direction from bottom to top on the screen. ^{A high level signal is then present at the output terminal 19-1 J} and at the output terminal 19-Q a low level signal. the signal at the former terminal is the signal WS, the signal on the latter Klemiue the signal IJiel t-VVS, In Fi / ^r. 15 monitor three AND gates' $ 02, the outputs of the flip ^ flops 124, the Vertikalgescliwindigkeitsre / ^1; -.!. the form most SignalDegel at the Auniranr ^^ lemme 1 ^(-S indicates the presence or absence of a CU'schv / indigkei tswertes i; .. register Is this,!. A .gial level is low, a speed value is stored in this register. This signal is referred to as a non-VEL signal and is inverted with the inverter 304, if a signal VEL has high levels at the output; sklemme 1 °, -λ errchoint. The digital value of the speed we d converted into an analog signal, at the output kienime 2G-A in Fi ^. Ii? appears.

The next step is entering dea, yertea of the gev ;; ': ii:; cli ten intensity and focuscienuig of the ilektronenntstrahls of the cathode ray tube for the. Vektorerseiirurir: in dar in ·· '· -. 22 darires divides i I -ΊοΐΛΐη rsdi ^ htererinter, This HIiη ^r abe o: ^% -foli't aurcL Verwer.'i ^ aiu 'des, Vort.es ii. · Dj ¹ , v; ^ o-lureh a ' ^r uortra {iuni "i3S" i times an dm * • "ingaui-eklem:.: ^'. ';' --- ^ rr-- ^s u" t -.v'rd-, the together: ^ n with a otartsi.gnal ai ^ Durchsteueruiir the oI, tterj ^ - uewirkt 7, v o ".'- _Ta."? duj eh .ier clock input IANR xer _flip-Flo:? '5 ^^ anirentendet y.'i3? U, <■> ■ -.li ^ .a.ei-- "■ · i'ipter; i.-den ,.: Jer öe i \: eiii'" an ^v einea jea-gii FIi ! '-! - lops *' ·. ^ iot r .-. i ⁴ "■ a Ci ^ ^: A? r \ .ster '; oA ± ie.- ^ auptein ^ ai ^ rre.:. · ters e'its; r ^ or.> :, ■ ; dem ninthem- ti ei vie run: "v, -aiiciirsxen 1: vnro ^ le ;;. ., ' ⁿ . ai.

^909847/0885 BADORlC ^ L

Hand described by Fig. 41, these bits are used in same way to describe a desired focus blocking and intensity of the electron beam. The 1 outputs the flip-flops 308 come with the digital to analog converter 309 connected; of the two analog signals corresponding to the Focusing and intensity of the electron beam generated. The amplifiers 310 amplify these signals and carry them the corresponding control electrode. !! -the cathode ray tube to.

The next step is to enter the desired horizontal and vertical endpoints for the endpoint of the vector in the horizontal and vertical registers in FIGS. 17 and 18, respectively The input terminal TS-5 in FIG. 17 is generated which, together with a start signal, opens the AND gate 312 and generates a clock pulse for the clock input of each flip-flop 314 of this register. The set input of each of these flip-flops is connected to one of the flip-flops of the main input register corresponding to the twelfth to twenty-fourth bit. The zero outputs of these flip-flops are connected to a digital-to-analog Konverte _r ygrbunden 31g which generates a horizontal endpoint indicative analog "signal which is amplified with the amplifier 316 and the Ausgangsklemjae 19 is fed -IfI.

The vertical send register shown in Fig. 18 is the entrance gills. TiJ-6 a transmission signal depending on the location IiVER fed. Together with a start signal, this causes the UNP-q-attater 317 to open the clock input of flip-flops 318 of the register drives. The set input of each flip-flop 318 is connected to a flip-flop of the main input register corresponding to the twelfth to twenty-fourth bit, The Hull .auc; ranks of the flip-flops> lo are with

_{no Λ;} BATH ORIGINAL

9098A7 / Q885

1 g 21 816

a digital to analog converter 319 coupled to the analog signal corresponding to the vertical end point. This is amplified with the amplifier 320 and the output terminal 19-N supplied.

The final step in creating a vector with constant Speed is the transmission of the port ooEf in the main input register. This word generates a transmission signal at the output of the decoder 53> that of the input terminal TS-IO of the circuit shown in FIG. 19 is supplied will. Furthermore, a start signal is generated which (in its inverted form.) With the leading edge of high Potential passes to low potential and a similar edge is generated at the output of AND gate 331, which the SSEP flip-flop 332 is set. Through this and through the deferred The initial state of the SSCZ flip-flop 333 is at the output of NAND gate 334 generates a high level signal which is applied to NAND gate 330. The other input signal this NAND gate 330 is the inverted start signal, which at this point has a low level. The output signal of the NAND gate receives accordingly 330 a high level, whereby a start pulse SSEP at the output of the monostable multivibrator 335 after a predetermined Delay time is generated. This impulse sets one Horizontal locking circuit 336 consisting of the NAND gates 337 and 338, and a vertical latch circuit 339 composed of NAND gates 340 and 341 consists. The outputs of these two latch circuits are monitored with the NAND gate array 204, the temporally coincident with both outputs of the interlocking circuits a start / stop signal is generated. This will fed to the inputs of AND gates 343 »344 and 345. Furthermore, the start / stop signal serves as a direct one Input to the NAND gate 201 and indirectly to the NAND gate 200 via an inverter 205. The other The input signal of the AND gate 343 is derived from that shown in FIG

909847/0885 ORIGINAL BATHROOM

1 9? "i 816

shown circuit via the input terminal 13-E in the form of the signal HEL, which is also applied to the input of the AND gate 349. This signal HEL. will also the NAND gate 338 of the horizontal lock circuit 336 is supplied.

Similarly, a signal VEL becomes the signal shown in FIG circuit shown via the input terminal 15-R. Input of AND gate 344 and AND gate 349 supplied. Furthermore, the signal VEL is applied to the NAND gate 341 of the vertical locking circuit 339 ..

The HEL signal comes from the horizontal speed register and has a high level when a horizontal speed value was entered in this register, v / as is generally the case in SSEP operation. Similarly corresponds the signal VEL indicates the presence of a vertical speed in the vertical speed register in FIG and has a high level in. SSEP operation. With control the AND gate 34; and 344 with the signals HEL and VEL, the start / stop signal opens gates 343 uxid 344. The outputs of these gates are connected via inverters 351 and 352 to one side of an analog switch 353 and 354, respectively. The other side of the switch goes straight to that Output of AND gate 343 or 344 connected. In this way, analog switches 353 and 354 remain in place of a signal HEL and VEL as well as a start / stop 3 signal.

In the closed state, the switch 353 carries a horizontal speed signal via the input terminal 16-K of the digital-to-analog converter 175 (Fig. 16) to an operational amplifier 355, which this analog speed signal integrated and in connection with certain correction signals via output terminal 34-C to the horizontal deflection system the cathode ray tube supplies.

BATH ORIGINAL

909847/0885

1 9? 1 81 6

Wit it emerges from fig, 19, is de? Operational amplifier 355 by, a further analog holder 356 short-circuited, The state of this switch is determined by the output signal of flip-flop 357 hey, that's right. This is explained below described in more detail «

Like switch 353, switch 354, in its closed state, conducts a vertical speed signal from digital-to-analog converter 125 (Fi ₁ ?. 15) to an integrating operational amplifier 348, from which it is transmitted via output gills 34-D to the vertical deflection system of FIG Cathode ray tube arrives. It should be noted that the integrating operational amplifier can be short-circuited 348 with another Analogsehalter 35a of the flip-rFlops is controlled 359 by the state, the action of the AnalQgschalter 356 and 358 is _t the integration effect of the operational amplifiers 355 and 348 in the overall Eliminate the closed state.

The flip-flops 357 and 359 are in the initial set state, whereby the integration amplifiers 355 and 348 are short-circuited. This has its ubiquitous in the common reset input signal via the input terminal of the flip-flops. A delay circuit or a manostable multivibrator 36u ensures that this initial state is maintained after the common backlash signal has been generated. It should be noted, however, that the input signal of the reset input of the flip-flops from the Ulij-G-attern 349 Uiid 350 wxrd _? whose one input; is again connected to the small parts 13-E and 15-R of the signals HEL and VEL, therefore -, vird di§sgr Ejngan? taking into account the already, ßrfalfttgn. ^ gs.Qtoeibung controlled for SSEP operation. The put on. The inputs of AND gates 34y and 350 are common to the QD-ER gates

9098A7 / Q88I BATHROOM

360 connected »that supplies a transmission signal in SSEP or SSCZ operation. Therefore, if you choose any jedeii _; - .. of these operating modes a pulse is sent to both AND gates 349 and 350 and thus to the reset inputs of the flip-flops 357 and 359. In order to divide these flip-flops back *, a clock signal must be received at the clock input. These inputs are jointly applied to a start signal which is generated practically simultaneously with the SSEP transmission signal of the circuit shown in FIG. This signal is the one at the input of AND gates 330 and 331, but is inverted. The flip-flops 357 and 359 are thus reset and supply a voltage to the analog switches 356 and 358, thereby opening them and allowing the integrated operational amplifiers 355 and 348 to operate so that the analog signals applied to the switches 353 and 354 can be amplified .

The flip-flops 357 and 359 are set when the Processing of the analog signals characterizing the horizontal speed and the vertical speed is completed. This state is made with a comparator 361 for the horizontal part and with a comparator 362 noted for the vertical part. Each Ver-P analog circuit compares the analog integrated speed signal with an analog signal that identifies the end point of the respective horizontal or vertical deflection is assigned.

In the case of the horizontal part, the integrated horizontal speed signal becomes an analog signal which indicates the horizontal end point whose value is obtained from the horizontal end register (Fig. 17) via the Input terminal 17 ^ ·! is fed. It is similar for the vertical part of the vertical speed register its integration with the comparator circuit 362 with an analog signal indicating the vertical end point

909847/0885. _BA p ORIGINAL

whose value from the vertical end register (Fig. 18) above the entrance gill 18-N is supplied.

If the comparator circuit 361 determines the comparison case, this becomes a low level signal for the horizontal reset Circuit 363 generated for SSEP operation. The reset circuit 363 contains the NAND gates 364, 365, 366 and 367. The NAND gate 364 inverts the signal of the comparator 361 and provides an input to NAND gate 365. The non-inverted horizontal comparison signal becomes direct is given as an input to NAND gate 366 which is also an input from the output of the latch 336 receives. This is also the case for NAND gates 365 and 367. In addition, a signal HVS is applied to the NAND gate 365 passed through the input terminals 13-G and in inverted form as an input signal to the NAND gate 366 via the input terminal 13-H.

For the letter I, the "HVS" signal has a low level and generates a high level signal at the output of the NAND gate 367. Therefore, if the signal gets low Level of the comparator 361 is generated, the output signal of the NAND gate 367 has a low level, the latch circuit resets so that their output signal is now at a low level. This effect is on the output of the horizontal lock circuit locates and does not affect the start / stop signal at the output of circuit 204 as long as the interlock is active circuit remains set.

However, if the vertical comparator 362 provides the comparison case between the integrated vertical speed signal and the analog vertical endpoint signal, see above a comparison signal is generated and the input of the Vertical reset circuit 570 supplied for SSEP operation, which operates similarly to the horizontal reset circuit 363.

909847/0885 ORIGINAL BATHROOM

'- 102 -

The only difference besides the fact that it's looking around is a vertical comparison signal, is the input a signal VVS through the input terminals 15-P from the vertical speed register shown in FIG.

When the vertical reset circuit is operated to reset the vertical latch circuit 339, terminates the start / stop signal and generates a low level signal at the output of circuit 204. As a result AND gates 343 and 344 are blocked and an input signal is generated at NAND gates 201 and 205. That NAND gate 205 inverts the output of circuit 204 and generates an input to the NAND gate 200. A black area signal from the circuit shown in Fig. 28 is also applied to both of the input terminals 28-V NAND gates 201 and 200 led. For the NAND gate 201, however, it is inverted. The NAND gate 201 also receives a signal from the flip-flop 206 controlled by the blanking bit. This determines by its state whether The electron beam is blanked during the sampling time effected by the integration amplifiers 355 and 348 or is healed. The state of flip-flop 206 is determined by the absence or presence of a blanking bit is determined in the SSEP word initially entered into the main input register (Fig. 9).

As has already been explained in connection with FIG. 3H, the sixteenth bit of the SSEP 'port is a binary 1 if a visible trace is generated or the electron beam is light-scanned shall be. This bit is a binary 0 if the electron beam is to be blanked. Is a If a visible track is desired, the flip-flop 206 remains in its initial reset state and generates a High level signal at the input of NAND gate 201.

909847/0885 ^BAD OR ^{| GlNAL}

- 1Ö3 -

Üäs Söh ^ ärzbereiehssignäi at the input terminal 28-V sometimes has a low level during SSEP operation. Therefore, the NAND gate 201 is switched on with a blackening range signal of high level (via the input small size 28-W), a start / stop signal of low level and a set-off signal of high level of the flip-flop 206. As a result, a high level signal is generated at the output of the NÄND gate 2DL. The input signals of the NAND gate 200 are an inverted stop / start signal of high level and a blanking signal of low level ~ _f, whereby a signal of high level is generated at the output of this NAND gate.

Before the creation of the Start- / Stöp-Sighale, the joint Output of the NAND gates 201 and 200 a signal high level. This signal received a low level when a start-ZStop signal was generated at a high level »whereby a falling edge resulted which actuated the multivibrator 202. This cultivibrator creates a High-level pulse, the edge of which is the multivibrator 208 actuated, causing a low level pulse of about 23 microseconds duration to one input of the NAND gate 203 is fed. The other output signal of the multivibrator 202 is a low level pulse of 1.5 iv microseconds Duration and arrives at an input of the AND gate 207. The NAND gate 203 generates a high level signal, as long as the output signal of NAND gates 201 and 200 has a low level. The AND gate 207 therefore produces a high level light duty pulse during the high level at NAND gate 203 with the exception of a duration of 1.5 microseconds, generated by the pulse of the multivibrator 202. This light pulse is the control electrodes the cathode ray tube s

Furthermore, the light key pulse is fed to an ODSR gate 371. The trailing edge of the light pulse is activated via the üDER ^ gate 202 to a time delay circuit 372; e-

9098 4 7/0885 BADORLGiNAL

which generates a very short low-level signal at the input of AND gate 531. This AND gate is blocked and generates a low-level pulse at its output, the leading edge of which the SSEP-J ¹ up-flop 332 resets. In this case, a low level signal is generated at the output of the NAND gate 334, which signal causes a high level signal at the output of the NAND gate 330, which signal is used as an interrupt signal for the next command. It is supplied via the output terminal 23-T the computer interrupt circuit (Pig. 23) and causes the generation of an interrupt h there character which is fed to the computer before the next command signal.

If a series of vectors is desired, the beginning of each is at the end point of the previous vector, the integrating amplifiers 355 and 348 with the analog switches 356 and 358 not bridged. In this way the last analog signal at the output of this amplifier will be maintained and increased by the next generated vector signals. However, it is the creation of a number of vectors desired, each of which has a unified initial. point, an RHVI word can be used to "reset the Horizontal-vertical integrators "are used * Dier This word generates a transmit signal at the input terminal TS-9, which is the set input of the flip-flops 357 and 359 is controlled so that the next start signal at their clock input causes these flip-flops to be set, whereby switches 356 and 358 are closed. This will reset the integrators .355 and 348.

It may also be desirable to generate a series of horizontal vectors in the form of a grid. To this To facilitate this, the word RHAV can be used * that via a transmission signal at the input terminal TS-II a resetting of the horizontal ink shown in FIG.

90SfU7 / 088S BADORIPiNAL

grators as well as an advance of the vertical address register (Mg. 12) do one step.

After the vector generation for SSEP operation, the Vector generation for SSCZ operation described. In preparation for this operating mode, the. Horizontal and the Vertical address register stored as in SSEP mode. As the speed from track to track by unequal length changes, it is necessary in the power density register (Fig. 22) to enter new values before generating each vector. Similarly, the horizontal and the vertical speed can also be changed prior to writing each vector. this is also in terms of the constant time for generation of each vector is required. Except for these differences, the function is the same as in Pig. 19 shown Circuit for SSCZ operation in the first operating, levels practically similar to SSEP operation.

During SSCZ operation, an SSCZ transmission signal is transmitted via the input terminal TS-12 to the set input of the SSCZ-Plip-Plop 333 and given to an input of the OR gate 360. The effect of the start signal on the AND gate 331 consists in that the SSCZ-Plip-Plop 333 is set from its reset initial state. Through this becomes a high level signal at the output of NAND gate 334 generated. At the output of the delay circuit in Porm of the multivibrator 335, a low level pulse is generated which sets the horizontal and vertical latch circuits 336 and 339 causes.

These interlocking circuits remain in SSEP operation in the set state until the integrated speed signal is compared with the analogue • 'end point signal is determined consistently. With SSCZ operation

BATH-

the resetting of the interlocking circuits by a Causes a signal at the output of the NAND gate 373, which is referred to as the SSCZ reverse signal. The inputs of the NAND gate 373 v / ground to the mull output of the SSEP flip-flop, which carries a high level signal during SSCZ operation, and via the input terminals 26-T with a line adjustment signal driven by the matching line counter and control circuit shown in FIG is derived. Normally this latter signal has a low level, which is the output of the DiAIiD gate 373 generates a high level signal, causing the latch circuits 336 and 339 by controlling the signal supplied from the delay circuit 335.

In the circuit shown in Fig. 26, the eight most significant bits of the SSCZ word in the eight Flip-flops 375 existing adjustment line counter saves. Each bit of the main input register (FIG. 9) is converted into a flip-flop via the AND gate 376 stored. The key-in pulse is supplied via the input terminal 10-E as a function of the start signal and a transmission signal which corresponds to the SSGZ word generated with the decoder 53 shown in FIG. Of the One-key pulse also causes the AND gate 377 to be turned on, thereby creating a clock pulse at the output of the OR gate 378 is generated, which corresponds to the trailing edge of the keying pulse. This sets flip-flop 379 and the AND gate 380 is opened, causing the flip-flop 381 is set with the B-trailing edge of the next pulse of the oscillator 382. If the flip-flop 381 is set, thus causing the signal to go high on its 1 output an opening of the internal AND gates at the set and reset input of the flip-flop 375 »the seventeenth or the least significant of those bits that are entered into the counter. This signal also opens high level the clock inputs of the remaining flip-flops 375.

909847/0885

; ι g? ί B16

- 10? -

The line adjustment counter is with flip-flops 375 and the AND gates 384 constructed as a down counter in which the oscillator pulses fed to the clock inputs of the flip-flops cause the countdown.

The zero state of the counter is determined with the AND gates 385 and 386, which are then a control signal for the Generate set input of flip-flop 387. The other set input of this flip-flop is connected to the! Output of the Flip-flops 381 connected and is set with the oscillator pulse following the zero counting step. That Setting the flip-flop 387 generates a line adjustment signal at the output terminal 19-T.

The AND gates 385 and 386 bring the zero state signal the flip-flop 381 back to its reset initial state, whereby the oscillator pulses the flip-flops 375 be kept away. The high level line adjustment signal at the input terminal 26-T produces a low level signal Level at the output of the NAND gate 373 »whereby the horizontal and vertical locking circuits 336 and 339 reset v / earth. Simultaneously with this, a high-level signal is generated by the start / stop circuit in SSCZ mode ended, whereby the light key pulse at the output of the AND gate 207 is ended. Furthermore, this light key pulse is as transferred to OR gate 371 in SSKP operation, whereby at the output of the NAND gate 330 an interrupt signal generated for the next command and sent to the output terminals 23-T is delivered.

Another operating mode, the raster mode, enables the Representation of an arrangement of raster points, for example for the representation of facsimile information. A SSEP word directs this operation in the for SSEP operation described manner. In contrast to SSEP operation, however, the vertical and horizontal

§09847 / 0885 BAD ORIGINAL

speed 0. This means that the signals HEL and YEL have the amount 0. With the setting of the SSEP flip-flop becomes a short pulse of low level at the output of the monostable Multivibrators 335 generated, which in SSEP operation the vertical and horizontal locking circuit and would put 339. However, since the presence of a signal HEL or VEL is a prerequisite for this setting, this pulse is only passed through both latches conducted as a high-level pulse, which emits a start / stop signal of the same duration and high level on ^ Output of circuit 204 generated. Due to the lack of the Horizontal and vertical speed values remain the gates 343 and 344 blocked during the generation of the start / stop pulse. The blanking circuit, in particular However, the multivibrator 208 reacts to the start / stop signal by generating a short-duration pulse (1.5 Microseconds) - at the output of the AND gate 207 “the one visible point generated on the fluorescent screen of the cathode ray tube. This light button signal is the same as in SSEP mode used to control the delay circuit 372, which causes the SSEP flip-flop to be reset.

| Because the horizontal and vertical speed values are zero are, AND gate 373 with the non-HEL signal and the no-VEL signal while the SSEP flip-flops open, giving a signal to advance of the horizontal address register is generated at the output terminal 11-Z, which is fed to the circuit in FIG. This signal causes the horizontal address to be advanced by one raster point so that the next luminous point can be generated, if this is desired. With the programming of the power density register can be a sequence or a complete grid of intensity-modulated Points for displaying graphical halftone data are generated.

19-1816

Overall, the invention enables the effective and fast processing of all forms of graphic data.

In the photo composition mode, black areas or tracks are created using a deflection signal, with a black area or a light key signal at the same time is produced. This method avoids creating a complete grid for each to be displayed Letters.

It should be noted that also described as an example Letters L also other letters and characters can be represented in the same way. About that furthermore, the photo composition operation is not limited to alphanumeric symbols. Other symbols like. geometric figures, straight lines, and other arbitrary symbols of any configuration may also be used being represented. Of course, such symbols must be made using the photo composition commands in are encoded in the correct sequence before they can be fed to the data processing device.

The frequency of the oscillator shown in FIG. 26 is not critical for the operation of the device according to the invention. A frequency of around 300 MHz has been used with success.

The invention has been described in terms of a preferred embodiment, but numerous changes will be apparent to those skilled in the art and equivalent embodiments possible without dated Deviate basic ideas of the invention. this is also valid for any further training to adapt to certain operating conditions or other display tasks.

90984 7/0885

Claims (8)

• - no - claims: 1. Device for displaying graphic information, in particular characters, on the screen of a Cathode ray tube by visible linear and parallel tracks, characterized by a Memory (e.g. computer) for storing a sequence of binary data words that make up a character to be represented correspond and in a data processing device (Fig. 2) the generation of this character strange distraction and dark or light button signals cause which are fed to an operating circuit for the cathode ray tube (3) and the generation of Distraction fever and dark or light palpations of the Control electron beam. 2. Apparatus according to claim 1, characterized in that the data processing device (! B ¹ Xg, 2) has a request circuit (34) for the successive transfer of the binary data locations from the memory and a decoder circuit (14) controlled with each data word for generation of decoded command signals which are supplied to expensive circuits for generating a sequence of deflection signals and black area signals occurring at the same time as these. 3. Device according to claim 2, characterized in that that the data processing device (Pig. 2) has an input memory (10) for the dated. Memory contains transferred data words. 4. Device according to one of claims 1 to 3 _f -da-! characterized in that each data word consists of several parts, each with at least one bit, of which a first part is the length of a track and a second part is the number of parts required for a character 909847/0885 ^: '■ 19? 18-16 - Ill - Indicates traces, ■ and that the data processing device (Fig. 2) a circuit controlled by the first part for generating a signal indicating the track length and a deflection signal generating the track length and a connected to this circuit and to the second part controlled second circuit for switching on the first circuit once for each individual track. 5. Apparatus according to claim 2 or 3, characterized in that each data word has a distance in the direction of the tracks indicating the first part and one indicating the length of the track assigned to the respective data word second part contains and that the tax attitudes one by the respective end-of-track signal and the first Part of the next data word controlled displacement circuit (Pig. 33) for generating a deflection signal corresponding to said distance and a black area circuit (Fig. 28) for generating a black area signal corresponding to the second part of the next data word and a deflection signal corresponding to the track length specified in this part. 6. Device according to one of claims 1 to 5, characterized in that the data processing device. (Fin. 2) a circuit (21) for shifting the starting point contains each track by a predetermined amount perpendicular to the longitudinal extent of the track. 7. Device according to one: a of the preceding claims, characterized in that the data processing device (Fig. 2) a horizontal speed register (20) for a predetermined horizontal scale value corresponding binary data for generating an analog signal corresponding to this value, a vertical speed register (21) for a ,, predetermined 90fS4 7/0 8S5 BADORLGiNAL 19? ι s 1 e "■ - 112 - Binary data corresponding to the vertical speed value to generate an analogous value corresponding to this value Signals, a horizontal endpoint register (19) for one Binary data corresponding to predetermined horizontal coordinates for generating one corresponding to this coordinate analog signal and a vertical end point register ■ (18) corresponding to a predetermined vertical coordinate contains binary data for generating an analog signal corresponding to this coordinate .. - - "■■ - ^ 8. The device according to claim 7 »characterized in that the data processing device has a horizontal switch (353, Fig. 19) for generating a first start signal depending on a start signal (HEL), a vertical switch (354) for generating a second start signal depending on one start signal <VEL), each controlled with the first and the second start signal integration circuit (355, 348) for generating a Ablenksißnals from the analog horizontal or vertical ^'T eschwindi / -keit3sißnal, a horizontal comparison circuit (361) for the analog horizontal endpoint signal and the horizontal steering signal for generating a horizontal comparison signal with the same size of the compared W nen oi ^ inale, a vertical comparison circuit: (362). For the analog vertical end point signal and the vertical table signal to generate a vertical comparison signal with the same size of the compared signals, a switching device (363, -370) to interrupt the first or * two-tone start signal by the: -horizontal- or vertical- · Comparison signal and one corresponding to the duration of the first or the first. ".second start signal controlled circuit (336, 339) 'ZMV control of the light scanning contains« · ..- "■ _ · y. . Device according to claim ...! ·, - characterized by: marked- * -> ■ ■ net that the file: iVerarb., Eitu.nr: s facility; a light as t- ^% BATH ORIGINAL ■ _: .90 9 8 ^ 77.088 5 υ ν control circuit that generates a blackens he ei chs signal or a start signal is activated and a time matching with these signals unblanking signal, a controlled with the data words, i ¹ ο tokomposi ti ons circuit (15) for generating mutually einschlies send · Black domain signals and AbIenkungssignalen, and a vector control circuit (18, 19) for generating a visible linear track corresponding to a vector having a start and end point. 10. The device according to claim 9, characterized in that that the vector control circuit is a memory device (Fig. 17 »18) for a sequence of binary code groups, of where a first is the starting point, a second is the end point, a third the horizontal and vertical speed of the vector track to be written and a fourth the type of representation indicates a decoder (353, 354, Fig. 19) for the fourth group for generation a start signal, one with the start signal and the third group controlled integration circuit (355, 348) for generating deflection signals and one with the zv / second group and the end point state of the track controlled Comparison scha! do? ', "(361, 362) to interrupt of the start signal. 11. The device according to claim 1, characterized in that each data word comprises a first part for specifying a predetermined amount of a yeißbereich, a second part for specifying a constant length and a third part for specifying the number of tracks required for a character and that the data processing unit ichtung (Fig. 2) an offset register (Fig. 32, 33) for the first part for generating a deflection signal corresponding to the aforementioned amount, a control circuit (Fi-Z. 25) for generating a black area and deflection signal corresponding to the second part, a scanning ■ 9 09847/088 5 BATH ORIGINAL 1321816 end circuit (210 _f . Fig. 28) for generating a scanning end signal at the end of the black area signal and a '7i ed recovery down counter (Fig. 3D for the third part for generating a repetition pulse at each counting step, the scanning end signal in each case containing a counting step causes the repetition pulse in the offset register (S ¹ Xg. 32, 33) for each generated track to bring the visualization into view, all deflection signals are directed to the deflection system of the cathode ray tube and the detection area signals are directed to the electron beam control. 12. The device according to claim 11, characterized in that that a stepping device (Pig. 31) controlled by the scanning end signal is also provided, the one switching step from the vertical position of one generated track to the vertical position of the next Track generated. BATH 909847 / 088S