DE1911012C - Arrangement for a system for reproducing a television signal - Google Patents

Description

management of the transfer of the fields (even-odd; odd, even).

In an arrangement of the type mentioned at the outset, this object is achieved according to the invention by a fourth subcircuit, responsive to the first and second subcircuits, for exciting a correction signal in the absence of the normal sequence of odd and even fields and by coupling the third sub-circuit to the fourth sub-circuit for receiving the correction signals.

Further details of the invention emerge from the following description of embodiments on the basis of the figures. It shows

I ⁷ ig. 1 is a perspective view of the mechanical part of a recording and reproducing assembly for performing the method of the present invention showing the relative arrangement of three of four head mounting and indexing mechanisms with respect to the surfaces of two recording disks;

Fig. 2 is a plan view of the arrangement according to Fig. 1, with parts of the panes broken away, around the four head-mounting and indexing tiechanisms to make it clearer

3 is an enlarged plan view of one of the head mounting and indexing mechanisms of FIG Arrangement according to Fig. 2,

F i g. 4 is an elevation of the head mounting and holding mechanism of FIG. 3;

Fig. 5 is an enlarged cross-section along line 5-5 in Fig. 4;

Figure 6 is a perspective view of a portion of the head mounting and propagating mechanism according to FIG. 3,

F i g. 7 one of the F i g. 6 corresponding perspective view, but with parts omitted and other parts have been broken off to make certain details of the mechanism clearer,

8 shows another perspective view of the arrangement according to FIG. 7,

Figure 9 is an end elevation of the arrangement according to

Fig. «,.

10 shows a block diagram of the electronics according to FIG. 1, FIG. IOD showing how the partial block diagrams according to Fig. 10A, 10B and IOC to one complete block diagram are composed,

11 is a graphical representation of the relationship between the head increment and the incoming Signal when recording and playing back at normal speed,

FIGS. 12A and 12B show the relationship between various Waveforms in the circuit shown in Fig. 10 and the associated indexing of the heads when recording and playing back at normal speed,

Fig. 13 is a graph showing the reverberation of heads in forward and reverse playback can be seen at normal speed,

14 shows different waveforms in the circuit according to Fig. 10 and the associated switching of the heads in normal playback and slow motion playback,

15 shows a circuit diagram of a speed control loop in the control circuit according to FIG.

Fig. 16 is a circuit diagram of a reproduction direction control loop in the control loop according to Fig. IOC,

FIG. 17 shows a sound image of a search frame feed control circuit in the control circuit according to FIG. IOC, FIG. 18 shows a circuit diagram of a slow-motion latch oscillator in the control circuit according to FIG.
19 shows a circuit diagram of a control logic circuit in the control circuit according to FIG.

F i g. 20 is a circuit diagram of a clock motor control loop in the control circuit according to Fig: 10C,

21 is a circuit diagram of a carrier logic circuit in FIG ίο the disk servo circuit according to Fig. 10A,

F i g. 22 is a circuit diagram of a reverse logic circuit in the disk servo circuit of FIG Fig. 10A,

23 is a circuit diagram of a carrier control logic circuit in the disk servo circuit according to Fig. K) A,

F i g. 24 is a circuit diagram of a carrier reset logic circuit in the disk servo circuit according to FIG. 10A,

Figure 25 is a circuit diagram of a carrier reversal logic circuit in the disk servo circuit according to FIG. 10A,

F i g. 26 is a circuit diagram of a carrier error correction logic circuit in the disk servo circuit according to FIG. 10A,

Fi g. 27 A and 27 B a circuit diagram of a synchronous isolation circuit in the electronic circuit according to Fig. 10B,

F i g. 28 is a circuit diagram of a servo reference delay circuit in the electronic circuit according to Fig. 10B,

Fi g. 29 is a circuit diagram of a slow motion reverser in the electronic circuit according to FIG. 10B,

Figures 30A and 30B are a circuit diagram of a quick search logic circuit in electronic systems according to Fig. 10B,

Fi g. 31 is a sound image of a clock generator in FIG electronic circuit according to Fig. 10B,

F i g. 32 is a circuit diagram of a slow motion logic circuit in the electronic circuit according to Fig. 10B,

33 is a circuit diagram of a field changeover switch in the electronic circuit of FIG Fig. 10B,

F i g. 34 is a circuit diagram of a field alternation logic circuit in the electronic circuit according to Fig. 10B,

Figure 35 is a circuit diagram of a half line delay logic circuit in the electronic circuit according to FIG. 10 B,

36 is a circuit diagram of a short logic circuit in FIG the electronic circuit according to Fig. K) B,

F i g. 37 is a schematic diagram of a chrominverter logic circuit in the electronic circuit according to Fig. K) B and

38 is a circuit diagram of a head reset logic circuit in the electronic circuit of Fig. 10B. .

According to the invention is a method of recording broadband signals such as Television signals and instrumentation signals (such as radar signals), and for playback these signals are provided with a modified time-base effect. Generally these procedures are used equal periods of the broadband signal recorded in sequence on at least one magnetic medium, each of the corresponding periods of the signal having a particular head medium recording speed is recorded. At Wk-der-

209 637/356

9 ίο

The corresponding periods would be calibrated from below by means of a disk servo Head-medium-speed as with the direction 15 "regulated disk motor 15 driven-recording reproduced, but outputting which of the disks with the field rate (the chosen periods given are repeated often. are about 60 rev / sec. for NTSC) in rotation ver-die selected periods and the number of 5 sets; there is a phase definition on an outer repetition are provided by the desired vertical synchronous reference, as in the fol-time base effect definitely. The reproduced areas will be explained. Therefore, each period corresponds to a constant output signal full revolution of the disks exactly to a television, that half image the desired time-base effect, beginning and ending in the vertical interval, supplies. . The disk servo device 15 ″ is preferred

For the purpose of explanation, the method according to the invention designed as speed and phase control will be described below with the aid of an and; Parts of such a device are in the order for carrying out this method. No. 644 261 and wrote. The applicant's arrangement 644 234 shown in the figures is described. The verbleieignet specifically for recording and reproducing portion of the disc 15 Bende servomechanism 15 α be on a conventional type canoe a composite television signal.

A variety of recording media, e.g. A highly polished thin layer of a magnetisdiLMi sequential sequence of four equal time periods of the 20 recording files of the optimal coercive force incoming signal is recorded on the recording surfaces, each and every one being recorded. Four radially movable record-erase periods on a different recording surface. and playback heads 16, 17, 18 and 19 are connected to In the case of a television signal, the same period is associated with one of the four disk surfaces, preferably a complete field, where each head is on a hollow cylindrical head, but also some other identical periods, mounted as with support 21 which surrounds an arm 22. This example full images (frames) are selected arm 22 is in turn fixed on a housing of a can. A recording stepper motor 23 is mounted for each recording track. The stepping motor heads provided, which complete one of the fields, are constantly mounted on a base plate 24 at such heights in an endless circular track that the various heads 16 to 19 draw. Thereafter, the head is arranged in the radial direction 30 adjacent to its corresponding recording by one step by means of a stepping motor. The arms 22 and the carrier are guided so that it is enabled a 21 are oriented so that the same sides point to the new field in the next sequence of four fields above; however, the heads 16 to 19 are to be recorded. During the period when mounted so that they face up or down. one head is incremented, other half-images are recorded by the other three heads, depending on whether they are recorded with an upper or a lower image, so that each head records every fourth field the three fields in between should cross over. Specifically, the heads 16 and 17 have jumps. In this way, a large number of down and the heads 18 and 19 up.
Fields stored on the disks. Each 40 The structure of the arm 22 and the typical Mon 'field' can according to a predetermined pattern of the carrier 21 and the head 19 are completely and repeatedly reproduced in FIGS. 3, 4 and 5 in detail. The arm 22 to achieve effects such as slow motion or still images is designed as a combing element, in the range of which; furthermore, the reverse sequence can also run channel 31 a metallic drive belt 32, which is to achieve a reverse running effect with any 45 between its ends on the sliding carrier 21 speed. A device is provided and at its end on a drum 33 a shaft in order to automatically mount a suitable pattern 34 of the stepping motor 23. In this way, by displaying fields in any desired manner, the carrier 21 can be set in a radial stepping speed in a continuously variable movement whenever the motor range is to be selected. A device is also updated. This subject will be described in more detail below for controlling the reproduction of each field. The drive belt 32 continues to run in order to ensure an exact interweaving of the signals, which are shown on the radially inner and subsequent signals at the end of the arm 22 at a small axial angle. The arrangement is easily mounted in a flexible versus vertical direction so that it can be adapted to the number of other uses; 55 returning part 37 of the drive belt on the Troin, for example, it can be the receptacle mel 33 at a different level. The drive belt 32, which is only every second incoming field, is handled several times around the drum 33 in order to achieve a time-lapse effect. wraps. This is mainly because of the

In the figures, an arrangement for recording is most suitable commercially available for the one shown

Use of a standard NTSC color video signal or 60 arrangement of selected stepper motors less

of a black and white video signal. Like steps in one revolution as the number of

in particular Figs. 1 and 2 of the drawing has zei traces which are recorded on the disk II

gen, the arrangement contains four recordings that can be made. The number of turns

dien, which are defined by the upper and lower surfaces and the size of the drum 33 according to the fol-

of a pair of magnetic recording disks 65 with the relationship selected:
ben Il and 12 are formed. These disks are

on a spindle 13 parallel and at a distance from one another - \ y - ^T ₌ ^L

permanently mounted on the other. The spindle is shown in FIG. 1 SC

Here, W denotes the number of Umwindimgen the drive tape around the drum 33, C the number of tracks which are recorded on the disk 11 in a full head running area L , S the number of steps in one revolution of the motor 23 and C the circumference of the drum 33. In the embodiment shown, the number of tracks is approximately three times as large as the number of motor steps, so that the drive belt 32 is fully wrapped around the drum 33 three times. The wrapping of the drive belt for the radially outermost position of the head carrier 21 is shown in FIG. 5, which also shows how the ends of the belt are fastened in a radial slot 38 of the drum by means of adjusting screws 39.

The radially outermost position of the carrier 21 is shown in FIGS. 3 and 4, from which it can also be seen that the carrier engages a safety device 41 for switching off the stepping motor 23 at the outer limit of the barrel L of the carrier in order to avoid destruction of the motor and a drive belt coupling. The device 41 contains a microswitch 42 which is mounted on the stepping motor 23 and has a piston disk 43 which engages with a concave cam 44. The cam is mounted on a piston 46 which in turn is loosely mounted in the ends of bushings 47 formed in lugs on the arm 22. In this way, the piston and the cam 44 have sufficient longitudinal play to actuate the microswitch. A stop 48 is attached to the piston 46 at the outer limit of the area L. In the same way, a second stop is attached to the piston at the inner limit of the area L. The stops 48 come into engagement with the carrier 21 at these limits in order to actuate the microswitch 42 and to switch off the stepping motor 23.

When the arrangement is in operation, the full area L is not used. Rather, the operation of the stepping motor 23 is switched at the ends of a smaller area 1 (FIG. 3). The boundaries of the smaller area 1 are defined by a pair of identical photocells 51 and 52 which scan the arrival of the carrier 21. As will be described in more detail below, these photocells are connected to electrical circuits to control the reversing of the stepper motor. The photocell 52 shown in FIG. 6 has a block 53 in which a downwardly directed light source 54 and an apertured mask 56 are mounted below the source. A photocell 57 is mounted below the mask 57 in block 53 and receives light from the source 54 whenever a plate 58 mounted on the head support 21 is not located between the light source and the photocell. The blocks 53 are each mounted on a pair of pins 61 (Fig. 3) to perform a radial sliding movement and are adjusted in the radial position by turning screws 62 which are screwed between the pins through the respective blocks and which extend from on the motor 23 and support arms 63 and 64 mounted on arm 24 extend away. These support arms 63 and 64 also serve to fasten the pins 61. Compression springs 66 are arranged on the pins 61 between the blocks and the support arms. The inner rotary screw 62 is adjustable from the side of the arrangement by means of a rod 67 which is attached to it by a flexible coupling

68 is attached. The rod extends through part of the support arm 63. During operation of the arrangement the plate 58 interrupts the supply of light to one of the photocells every time the head carrier 21 reaches an end of the operating range I. This results in a change in the electrical signal supplied by the photocell, which leads to a

ίο interruption of the operation of the stepping motor 23 and initiating the reverse movement of the motor. If one of the devices 51 and 52 fails, the motor is stopped by the microswitch 42 when the carrier 21 reaches the corresponding limit of the area L.

On the arm 22 belonging to the head 16 is a pair of advance warning photocell devices 69 ″ and

69 b , which are equivalent to the photocell devices described above. The photo line device 69 "is arranged so that it is actuated by the head support 21 a few lanes before the actuation of the inner photocell device. The outer pre-warn photocell device 69 b is arranged such that it is actuated by the head support 21 several tracks before the operation of the outer photocell means 52nd Pre-warn photocell devices 69 'and 69 serve b, svie hereinafter will be described in more detail, to reduce the normal speed of the carrier before the reversal during the fast search operation.

The arm 22 is also used to hold a certain electronic components containing Circuit board 70.

The way in which the head support 22 is mounted on the arm 22, which allows the sliding movement, is in Fig. 7 shown. It is of course desirable that the carrier 21 firmly on top Faces 71 and 72 of the arm rests for precise adjustment of the head 19 against the recording surface the disc as well as a precise setting of the contact pressure between head and disc to enable. For this purpose, three bearing elements 73, 74 and 75 are inserted into the carrier, with the elements 73 and 74 bear against the surface 71 and the element 75 against the surface 72.

This design results in a three-point mounting for the carrier. Furthermore, a fixed dimension bearing is on the front of the assembly with respect to the rotational direction of the disk. This from The direction of rotation running from the top right to the bottom left is shown in the figure by an arrow 76. For this purpose, a pair of bearing elements 77 and 68 are inserted into the carrier 2t, which abut against a front side 79 of the arm 22. The bearing elements 73 to 75 and 77, 78 are made of hard Made of wear-resistant, low-friction material and extend slightly from the walls of the carrier 21 so that they are the only places where the carrier 21 with the upper and front of arm 22 communicates. To ensure that these bearing elements are firmly engaged to ensure a pair of spring-loaded rollers 81 and 82 mounted on the carrier 21 are provided, which are in engagement with the rear or underside of the arm 22. The roles 81 and 82 are rotatably mounted on arms 83, which extend from the centers of leaf springs 86 through Openings 84 in the carrier 21 extend. The leaf-

13th

Springs 86 are attached at one end by a screw 87 which extends through a tubular spacer 88 and is screwed into the bracket 21. At the other end, the springs 86 are fastened to the carrier 21 by means of a screw 89. The screw 89 can be tightened or loosened in order to increase or decrease the pressing force of the corresponding roller 81 against the carrier 21. Except for roles 81 and 82

actual head pressure is therefore provided by a leaf spring 107 which extends away from an adjustably rotatable block 108 attached to the support arm 97. The block 108 5 is screwed tightly to the support arm. However, the screw (not shown) can be loosened via a screwdriver slot 109 to rotate the block 108. After turning, the screw can then be tightened again. The other end of the

and the bearing elements 73 to 75 and 77, 78 is io spring 107 rests on a gem bearing 111 , which no contact between the carrier 21 and the arm is fixed exactly in the center of the triangular plate 91 , 22 is present. All of the other parts of the support ensure an equal distribution of the pressing forces on the head 19 and the bearing elements 92 and 93, rather at a distance from the arm, as shown in FIG. put. Is it desirable to change the heads?

Details of the mounting of the head 19 on the 15 or the head contact pressure for some reason support 21 are shown in Figs. The dismantling without changing the setting of the block 108 and head 19 consists of a very small element in the spring 107 , so an eccentric shape of a block or plate is rotated with a (not screw 112. This screw 112 is shown in FIGS ) magnetic transducer gap, which support arm 97 is screwed in. If it is rotated, the receptacle 20 occurs transversely to the direction of movement (arrow 76), it runs with a surface extending away from the spring 107. The head 19 is engaged at the tip of a double lip 113 , so that the spring mounts small triangular plate 91, in which the is pulled away from the bearing 111. Pointed corners facing away from a pair of hard, ab- To arrange the head so that it is on one of the

wear-resistant bearing elements 92 and 93 rests against the upper disk surfaces, as is used in the case of Köpringer friction. The head 19 forms 25 fen 16 and 18 is the case, the component 98 and 99 consisting of the blocks together with the bearing elements 92 and 93 is released both from the carrier 21 of the three-point contact of these elements with the recording arm 97 and from the support arm 97. The blocks 98 and nungsfläche to ensure that the head is neither 99 then rotated 180 ° around the Y-axis in the YZ plane nor in the A'-Z plane and tilted on the front side of the in the direction of movement. Correct orientation of the head 19 in the 30 blocks 98 attached. The pin 101 extends from the XY plane is achieved in that the two triangular sides of the block 98 are equidistant. For the plate 91 at the rear end of the screw 102 in the direction of movement, a threaded hole of a long leaf spring 94 is mounted, which is provided in X- in the block. A screw 114 clamps the Y-direction rigid, flexible in the Z-direction and drive belt 32 is formed between a pair of parallel torsionally flexible and which at their 35 flanges 115 , which from the carrier 21 in the rear end in the direction of movement on a channel of the arm 22 run.

from the support 21 extending away from the support arm 96. Fig. 10a shows a cladding 116 in block sound

pictorial form for controlling the operation of the stepping motor 23. This circuit is provided with a control circuit 117 (block diagram according to FIG. 10c), which contains the control devices required for the operation of the arrangement, and with an electronic circuit 118 (block diagram according to FIG. 10b) , soft the signal electronics and the control electronics de-optimal converter efficiency and a 45 holds, connected. A signal that would denote with a book little destruction and wear of the contact surface and a line on it. The equalization of the contact pressures is the complementary signal to a signal of the elements 92 and 93 is achieved by a device which is marked with the same letter without a dash, which denotes a leaf spring 94 supporting. In the following description, support arms 97 are included. The support arm 97 is indicated on a 50 the signals with values 1 or 0, from two blocks 98 and 99, especially on block 98, which means that the signals equal to the binary value 1 by means of a pin 101 and a screw 102 or 0 are. In the following, the strengthening is first of all. The block 99 is attached to the carrier 21. The drawing of a video signal is described. As blocks 98 and 99 are arranged so that they are shown in Figure 10b, there will be a composite Syn-YZ plane. By means of a leaf spring 103 , the blocks are coupled at their upper ends. One can, given to a synchronous isolation circuit 1 21 , arranged between the centers of the blocks, which supplies a servo reference pulse S _r. This leaf spring 104 presses them apart, while a pulse corresponding in time to the first prong of the screw 106 runs freely through the block 99 and is screwed in an adjustable sync pulse in the composite syndrome block 98 , whereby 60 is a chronsignal (Fig. 12a). This reference pulse S _r will hold the blocks together against the pressure of the spring 104 on a servo reference delay circuit 122. By actuating the screw, in which during the recording from an in the 106 , the block 98, the support arm 97 and the following reason, still to be stated, the plate 91 can be tilted in the YZ plane by 15 microseconds until it is delayed. The delayed servo reference the pressing pressures c of the elements 92 and 93 equal to 65 pulses R _d will be on the disk servo 15a . of the disc motor 15 given. The disc servo

The leaf spring 94 is not stiff enough to allow the device 15a to bear the disk movement on the weight of the plate 91 without bending. The delayed reference pulse R _d fixed so that, as above

is consolidated. Therefore the head "hangs" constantly and tries to swing into the correct orientation and position in the XY plane.

In this position and orientation of the head 19, it is still desirable to apply its contact pressure to regulate and ensure that the contact pressures of the elements 32 and 33 are equal to a

15 16

Mentioned the disk for each vertical pulse in the As the diagram shows, the head A is the same angular position. The delay from during the time before the arrival of the half-frame 15 microseconds of the servo reference pulse is made des 1 on track 1 of the associated disk during recording in order to make it possible for flatΛ, the disk during this time playback Position of the 5 period makes a 360 ° rotation. To let the head lead to the disk, whereby a signal is found in the erasing mode, which can be compensated for by the delay caused by the video electronics. The letter £ is indicated.

A video signal, such as a live television signal, during the time interval when the field 1 viewing signal or a television signal that arrives with normal, the signal E _{uc is} equal to 1, which means that the speed of a magnetic tape reproduced io the recording gates belonging to the head A. 124 A is given, an input frequency modulator is opened. Therefore the output signal of the recording 123 (Fig. 10b), which conventional type recording amplifier 51 is coupled to the head A, is given. That can be. The frequency-modulated output signal head therefore records the field 1 on the track 1 of the modulator 123 is recorded on the disk surface A via a recording device. At the same time, a more powerful 125 is applied to four recording gates 124 , 15 direct current erase signal to the next head, one for each of the heads 16 to 19 and thus for track 1 of the disk surface B. When admitted, the four tasks. The DC cancel signal is given sequentially for the duration of a half-frame head amplifier circuit 126 via a receiving gate 124, which can be conventional analog gates of the four cancel and gates (not shown). This gate is _{activated by signals E af} , E _bc , E _tc and E _dc , 20 connected to head B and is transformed for a half of which four are a series of pulses by the pulse E _ac , which acts through the comprehensive same signals. These signals are gates in the reproduction gate circuit 130 , as shown in FIG. 12b and are still activated as follows.
J is explained in more detail, by 90 ° against each other in the During the second interval causes the signal! Phase postponed. The output signals of the recording 25 E _bc that the recording gate 124B the field 2 recording gate 124 are coupled via corresponding recording to the head B , whereupon this field is recorded on the playback relay in a head amplifier track 1 of the disk surface B is recorded; j circle 120 on the corresponding heads 16, 17, 18 the erase signal is given by the Imj and 19 , which actuated the signals on the disk pulse E _bc and belonging to head C erase

Record 11 and 12 . For the following execution gate (not shown) routed so that the head C: stakes it is assumed that the disks 11 and the track 1 on the disk surface C erases. Equal-

12 rotate at the correct speed and that the timely a pulse F _{acj (explained below) arrangement was switched to the stepping motor} recording by pressing a recording head 52 via a motor to be explained below in a playback direction control circuit 127 on drive amplifier 129 A. Given by pressing the 35 23 A (Fig. 10A), the head A of

. Recording head S2 , a signal Q ₁ = ^ 0, which track 1 to track 2 of the disk surface A

leads to the fact that signals P _t and P _{2 are switched on} in a rule.

logic circuit 128 are equal to 1. The presence of the signal P ₄ , which is equal to 1, at four AND gates pulse E _rc during the third line interval causes the recording gate 124 C to transfer the half (not shown) in a playback gate circuit 130 40 image 3 to the head C. couples so that this half causes the signals E _ac , E _hc , E _cc and E _dc to be applied to the recording gates 124 recorded on track 1 of disc surface C. men will; simultaneously causes this pulse that the stepping motors ^ the head D deletes the mode of the track circuit 1 on the disk surface D. ^, JP and the excitation of the heads is explained on the basis of a The pulse F aci is again explained on the motor drive _{four-part diagram according to FIG.} Placed in 45 amplifiers 129 A, so that the stepping this figure, each part of the recording process A motor head A from the track 2 to the track 3 on one of the disk surfaces by the corresponding surface of the disc A on. Furthermore, a head is shown. For reasons of expediency, the impulses F, _{) Ci} on a motor drive amplifier 129 B heads are no longer given in the following by the reference, which causes the step holding mo-S to mark 16, 17 and 18, 19, but by the book 50 is energized and the head B is marked from track 1 on bars A, B, C and D ; the associated track 2 on the disk surface E switches.
Circles and waveforms are marked with the corresponding effect of the pulse E _dc during the same letter. It is also the fourth time interval that the recording gate 124 D takes that the heads at the outermost field 4 are on the track 1 of the disk tracks of the disks. The y-axis 55 couples each area D D stationary head. Furthermore, the partial diagram represents eight tracks of an eight- the pulse E _dc has the effect that the head A repeats the cycle to track disk, the outermost track beginning with 1 by repeating the track 3 on the. Choosing the number of eight spur disc face A clears. The impulse E _bci is again given to head B for the sake of simplicity and illustration, which causes it to be functional; It should be noted that the third track is actually switched to 60. A pulse F _cci is given space for a motor drive amplifier 129 C, which have more tracks, on the array used disks. The four parts of the diagram rather excite the stepping motor C, thereby having a common AT-axis, which is connected at the upper head C to its second track,
It can therefore be seen that each head of a series of fields is divided into different margins of the drawing. Here, an assumed sequence of fields from 1 to 38 is shown, consisting of repeated "Delete — Record" sequences. Movement — Movement ”follows, which in Fig. II are designated by The incoming fields represent the“ RRMM ”(abbreviation of the English designation fields of the video signal to be recorded. Raise-iecord-move-move). Farther

17 "18

the sequential fields in each group are given to circle 134. In this head logic circuit 134, the signal D ₀ of four fields on different disks is divided by two, as a result of which a right-hand area is recorded, the odd half-corner signal L (FIG. 12B) being formed. From the images on the disk surfaces A and C and the signals D ₀ and L , four head time signals E _Ui , straight fields on the disk _surfaces B and D 5 E HÜ, E _co and E _{I) G} generated in the head logic circuit 134 are recorded . The sequence of the recording, whereby these signals are each a voltage from head to head and from disk surface to 'sequence of equally spaced pulse disk surfaces can be omitted by "recording" arrows, which, however, are 90 in each case Phases, which are entered in FIG. 11. are shifted .. The pulse E _A0 has an on-While the heads when recording radially io rise time, which 'move the rise time of the first pulse inward, they also draw ses L or the first pulse D ₀ corresponds. The fall time on every second (odd-numbered) track corresponds to the fall time of the first pulse on the corresponding disk surfaces, where D ₀ . The _pulse E li0 has a rise time which is intended to use the intervening (even number corresponds to the fall time of the first pulse D ₀ , gen) tracks when the heads 15. Its fall time corresponds to the fall time of the first move radially outward. This skipping of pulse L or the rise time of the second pulse track represents the requirement which two ses D ₀ . The pulse E ₍₀ has a rise time, step switching or "movement" actions in Se- which prescribe the fall time of the first pulse L or the sequence. This corresponds to the situation in the rise time of the second pulse D _{0. Drawing clearly} to make these movements are 20 His fall time corresponding to the decay time of the branching steps extending to below 45 ° straight ■ th pulse D _0. the pulse D ₀ has a Andargestellt. However, the movement time of each rise time, which in fact, the fall time of the second pulse head corresponds to slightly less than a fifth of D _0. Its fall time corresponds to the time interval corresponding to an field, such as the rise time of the second pulse L or the rise time of the first two "movement" times of the third pulse D ₀ .

Steps of head A is shown. In this way, the head switching signals E ' _{1! 0} and E', _{) 0} are given to a head return control logic circuit 126 for the entire sequence at five times the speed. The speed compared to the normal recording or signals E ' _A0 and E' _co will be carried out via a carrier playback speed, such as logic circuit 137 and a carrier reverse run, this is given for the logic circuit 138 still to be described below, whereby when recording » fast «search operation is required. at the output of reverse logic circuit 138

Signals E ' _ΛΚ and E' _CK corresponding to these signals O _11n A _1n ., E _cc and E _cd (Fig. 12B) appear are generated in the following manner. As Fig. 12A shows these signals are from the reverse logic circuit, a signal T in the synchronous separation circuit 121 138 is applied to the head reverse control logic circuit 136, generated. The signal T comprises a pulse sequence, at 35 a clock received by the clock generator 132, each pulse is a positive RZ pulse (return-to-pulse C "clocks the zero pulse in the head return control logic circuit 136), which at the end of the last line Zero crossings of the input pulse E 'li0, E' _na , _{horizontal sync pulse of} the composite E ' _AK and E' _CK , which begins with the pre-pulses G zuSynchronsignals, coincide during the compensation so that the zero crossings of the / J pulses of the vertical sync pulse and the one on it - 40 pulses at the output, E. _xc , E _nc , E _cc and E " _c with the following equalizing pulses lasts and coincide before the clock pulses C. Therefore, the beginning of the first line horizontal pulse ends. Zero crossings of the output pulses of the head back signal T is applied to a quick search logic circuit control logic circuit 136 with the end of the last 131, which has a corresponding equalizing pulse of each field at its output output of the signal T _{s is} generated as long as the arrangement is 45 signals of the head return control logic circuit 136 are not in the quick search mode (P ₄ = 1). The half-signal T _s at the end of the last equalization pulse is applied to a clock generator 132, forms a pre-pulse G _{that coincides with the leading edge of each pulse T s} on the recording gates 134 via the AND gates and one with the give.

Trailing edge of the pulse T _s coinciding 50 In the inertia logic circuit 137, the signals E _Mi ,

Clock pulse C generated. In the following, pulses, E _ua , E _co and E _{m} are used} to switch the head carrier

which are clocked by the pulses G and C, 23 transferred in the carrier signal F _A0 , F ₁₁₀ , F ₍₀ and F ₁₁₀ ,

with the index "g" or "c". As Fig. 12B shows, each pulse F _{A0 is} temporal

In the clock generator 132, the pre-pulse B is equal to the sum of the pulses E ₁₁₀ and E ₁₁₀ : the im-

divided by two, so that with a first pre-pulse G 55 pulse F _{li0 it} is temporally equal to the sum of the pulses

the value 1, for the second pre-pulse G the E _co and E _{LI (i} ; the pulse F _cu is temporally equal to the

Value 0, at the third pre-pulse the value 1 etc. an- sum E _no and E _A0 ; the impulse F _m} is temporal

takes, whereupon a square wave signal B _u (Fig. 12A) equal to the sum of the pulses E _A0 and E _no .

arises. In other words, the zero-crossing signals F _no and F ₁₁₀ for carrier B fall

Transitions of the square wave signal B ₀ with the pre-pulse 60 and D are transmitted to a carrier control logic circuit 139

sen G together. The square wave signal B ₀ is given and appear as corresponding pulses

given a slow-motion logic circuit 133, with F- '" and F- _υ at its output. The carrier signals

normal recording mode ( W ₁ , - = 0) at its F- _Ao and F _co for the carriers Λ and C are on

A corresponding square -wave signal D _{0 is} output to the reverse logic circuit 138. at

will deliver. The clock pulse C is also played on the 65 (B ₂ F = 1) generate the carrier signals

Slow motion logic circuit 133 given and generated at F - _A0 and _{F - C} " _o at the output of the reverse run

whose output when recording a corresponding logic circuit 138 corresponding, but complementary

Pulse / _C. The signal D ₀ is based on a head logic signals F _AK and F _CK . The signals F _M and F _CK

are applied to the carrier control logic circuit 139 and appear at its output as corresponding signals F- ',, and F- _c .

The carrier signals F- ',,, F-' _ß , F- _c and F- _u are applied to a carrier reverse control logic circuit 141, in which they are clocked back by the clock pulses C from the generator 132. The clocked back carrier signals superimpose the J _c pulses from slow motion logic circuit 133 (FIG. 12B). The pulses J _c correspond to the clock pulse series C during recording (W _{s - 0);} however, they are delayed by 2 microseconds in the carrier return control logic circuit 141 so that they do not coincide with the NuH passages of the retimed carrier pulses. The superimposed pulses J _(: appear at the output of the carrier return control logic circuit 141 as signals F _AC , F, _iC , F _a: and F _{IH :} . These are RZ pulses (return-to-zero pulses) of 20 Microsecond duration. A signal Q is applied to the carrier return control logic circuit 141 which, when the disk servo is not in operation, blocks the carrier signals φ , thereby preventing the carriers from moving over the disks when they are not rotating.

The RZ carrier pulses are applied to a carrier error correction logic circuit 142; they appear for the inward movement of the carriers (N = 0) as impulses F- _ACI , F- _nCh F- _{(: CI} and F- _{I) C} , at the output of this circuit 142 which in turn control the associated stepper motors 23, whereby the carriers are advanced inward. The carrier is advanced once per pulse. It can be seen that each carrier stands still for two fields each and is then advanced approximately at the end of the last output pulse of the next two fields (two steps).

The carriers 23 are continuously indexed inwards until the head has reached the radially inner limit of area 1. At this point, the head carrier 21A operates the inner photocell devices 51a (Y _A in Fig. 10A). The operating position of the photocell device 51a is carefully adjusted so that it is at the center of the first

Step to the innermost odd-numbered track. located; that is, it lies between tracks 7 and 8, as indicated by an arrow labeled 5-5 in FIG. The Y ^ -Photozelleneinrichtung 51a prevents the associated stepping motor 23 A performs a further inward movement, and enables this motor in a position to move the carrier to the outside. In this connection, a signal Y _{4 is} applied to a carrier reversal logic circuit 143. The signal at the output of circuit 143 which is complementary to this signal is applied to carrier error correction logic circuit 142. In this circuit 142, the signal Y., the signal F- _ACI blocks, whereby a further forward movement of the head A is prevented. The head therefore does not take any further inward step and remains on track 8 while field 15 arrives. The pulse E _{I) C} then causes head A to erase track 8 (field interval 16). The pulse E _{AC then} causes head A to record field 17 on track 8. According to actuate the head carrier 21b, 21c and 21d during Halbbüdintervalle 15, 16 and 17, the photocell means 51 b, 51 c and 51 rf. The generated signals Y ₀ , Y _c and Y _D block the signals F- _IICI , F- _{H (: i} or F- _{Wc /} in the carrier error correction logic circuit 142 after inversion in the carrier reversal logic circuit 143.

When all the inner photocell devices 51 are actuated, the pulses E _lia and J _c coincide. The carrier reversal logic circuit 143 causes a signal M to be switched from 0 to 1. The pulses F _nc , F _{C (>} F _{l) (:} and F _AC then cause pulses F- ,, _CÜ , F- _{(: a)} , F- _ocl) and F- _AC0 to be sent to the associated motor drive amplifier 129 , which results in an outward indexing of the carriers by the corresponding stepping motors 23.

During the half-frame intervals 18 and 19, the head A is indexed radially outward onto the even-numbered track 6 and then continues to the outside normally until the head carrier 23a actuates the outer photocell device 52a, as indicated by an arrow marked SS between the tracks 2 and J is indicated in field interval 30. The operations of heads B, C and D are exactly the same except that each head is one frame out of phase with the previous head and each head reaches its corresponding outer pliotocell device 52 one field interval after the previous head.

When the head A actuates its external photocell device 52 ", a signal X _A from the Pliotocell device blocks the second of the pulses F ^ -, whereby the further outward movement of the stepping motor 23 α is prevented. Correspondingly, the actuation of the external photocell devices by the head carriers 23 of the heads B, C and D leads to the generation of signals X _lh, X _c and X _n , which after inversion in the carrier-reversing logic circuit 143 the second of the pulses F _lsc , F _cc and Lock F _{i) C} , which prevents further outward movement of the respective carriers. All carriers remain in their outer position until the next pulse E _li0 and / _{c is} received; At this point in time the pulses F, _1C , F _(C , F _DC and F. _u: pulses F _BCh F _CCh F _DCh F _ACh, which advances the stepping motors inward. During the half- interval 32, the pulse Efjc causes head A erases field 1 from track 1. During field interval 33, pulse E _AC causes head A to record field 33 on track 1. Similarly, head A erases field 5 from track 3 during half interval 36 and records during the semiconductor interval 37 the field 37 on the track 3. The operations of the heads B, C and D follow in the above-mentioned manner, as is also shown in FIG.

Carrier reversal logic circuit 143 (Fig. 10A) holds the heads at the uni-reversal point (lane 8 or lane 1) tight until either all of the internal or external photocell devices are actuated; d. Hall Heads have reached their inner or outer limit, so they are in correct sequence in opposite Direction to be advanced. This corrects possible errors when one of the heads does not receive an advance signal correctly and falls behind the during the inward or outward movement other heads fall back. Any such error will be no later than the end of the moving part corrected in which the error occurs.

The same operating sequence of the stepper motors

21,

Inverter circuit 151 is described in an application filed at the same time. The chroma inverter circuit 151 is operated when a color signal is reproduced at certain times during an abnormal reproduction operation. The output signal of the chrominverter circuit 151 is applied to a circuit 151 α, which a color phase adjustment of the composite color video output signal with respect to an external color synchronous

and heads results for forward playback with
normal speed from the disks. The only exception is that when playing
the erase signals are not given to the heads
and each head, instead of recording, during his
R-field interval. The operational sequence
for forward playback at normal speed is shown in the left part of FIG.
In the right part of this figure are the ratios for

Reverse playback shown. With backward io reference signal] brought about, reproduction of images is in this context. In circles 150 a and 151 α , it is meant that the sequence of an event signal given from behind is delayed; runs forward by this delay. For example, this is used to compensate for the stanchions, the illusion is created on the circle that. signal given to a broken vase 150a is delayed. In this context, reassembled by itself and as a whole anew, the synergies of the assembled synergy are created. In FIG. 13 it is assumed that a normal speed playback key 59 derived in the synchronous separation circuit is in one. Rizontalsynchronimpulse is pressed via a reference delay speed control circuit 144 , output circuit 1516 on the circuit 151a . Rather, Im causes the signal P _{1 to become} equal to one. Further circuit 151 is b, the horizontal control signal before Seihin is assumed that a forward key SS in 20 ner feed to the circuit 150a varied so that playback direction circle is pressed 127, the circle to its possible rather WEL 150 a is about in the middle causes that the signal P _{4 is} equal to zero. The correction area is working. In this case, the color sync signal given to the absence of the signal P ₄ at each of the four AND circuits 151 α is caused by the gate in the reproduction gate circuit 130 that the phase of circuit 15Oc is influenced in such a way that the signals E _AC , E _BC , E _cc and E _DC on the four 25 in the middle of the operating range of the circle 151 α AND display gates in the display circle 130 . The errors supplied by circle 150 a will be given. A voltage signal is sent to the servo reference delay on a channel. In this way, the circuit 122 is coupled by sequentially varying the phase of the Si playback gate 130 by the same signals R ₀ and thus switching the position of the disc signals E _M :, E _BC , E _cc and E _DC , which 30 changes. This ensures that the circuit 150 a also switch the receiving gates 124. in the middle of its possible correction range

When playing back the heads are played back by.

sponding recording playback relay to correspond The output of circuit 151a is coupled to sponding playback preamplifier in the head amplifier having a video signal processing amplifier 151c overall 126, giving the FM signals from the decision 35, which may be of conventional type . Strengthen the speaking minds. The output signals of output signals of the amplifier are c 151 on the preamplifiers are on the reproduction gate a monitor (not shown) and coupled to a comparison 130 that the reproduced half braucherkreis (also not shown) given image exceeded in a coherent FM signal Figure 13 shows a playback sequence which results in the beginning 40 being coupled 40 to an equalizer circuit 146 with the heads being in sequence for one field. For the signal reproduced by the heads interval are coupled so that the fields 5, a predetermined amount of equalization is selected 6, 7, 8, 9 and 10 in forward mode with normal, the head switching pulses E _AC , E _BC , E _cc speed can be reproduced. It should be used and Epc is used to select the amount of equalization supplied between field 10 and the distortion circle by means of the 45 field 14 a reverse key 53 in the re-selection. The equalized reproduced signal is given direction control circuit 127 is pressed. This is sent to a demodulator 147 , the output of which is a signal Q ₂ in the control logic circuit 128 output signal to an electronic switch 148 , whereby a signal P ₂ is coupled its value of 1. The electronic switch 148 couples to 0 changes. The reverse run _{signal P 2} is given to the fast search logic circuit 131 when a half-line delay circuit 50 is actuated, the signal appearing at the output as P _{2 s} = 0 when is. This delay circuit 149 contains a device that does not operate in the fast search mode. 30 MHz Ampliludenmodulator, one on a mid The signal P _{s 2} is added on the backward pass logic operating frequency of 30 MHz ultrasonic encryption circular 138th The reverse logic circuit 138 delay line and a 30 MHz demodulator. 55 is designed so that it does not work until normal playback (P ₁ = 1) the next electrical _{pulse E BG} occurs after the sinic switch 148 is not actuated, so that the playback P _2S becomes zero is. If the next given video signal is received without delay via an off pulse E _BG , the reverse gear video amplifier 150 causes a horizontal run logic circuit 138 to give a signal K its value synchronously - time base - correction circuit 150 a given 60 from 0 to 1 changes and that the signals E _AG and E _CG , which a phase adjustment of the horizontal are exchanged in the sequence, as shown in Fig. sync signal and its video signal on one; the signal E _CG thus appears at the off-horizontal driver signal, as in the following passage E _AK and the signal E _AG at the output E _CK . Is descriptive. In other words, the signals F _AG and F _{110 are} interchanged in the sequence, whereby the signal F _{A (J} at the base correction circuit 150 α is transmitted via a chroma output F _CK and the signal F _CG am Output F _AK erinvertcrkreis 151 given, which appears the phase. In addition, the reverse run chroma information generates rotates by 180 °. This chroma logic circuit 138 then each time a 20-micro-

second pulse M, when the arrangement is switched from forward running to reverse running (P ₂ s ⁼ ^) ° ^from reverse running to forward running (P ₂ S = I). Signal M is applied to carrier reversal logic circuit 143 by this pulse M causing signal M to change its value from 0 to 1, with the result that the carriers are moving outward and the fields are reversed Order to be reproduced. This results in the effect of running backwards.

To avoid incorrect operation of the logic circuits, the reverse logic circuit 130 is like this designed that the arrangement does not move from forward to reverse or from reverse

is, the reverse logic circuit 138 expects the first pulse E _B0 after the signal X + Y no longer satisfies the disable condition (ie, this signal is equal to 1).

In addition, it should be noted that in reverse operation, the carriers are the photocell devices 51 and 52 at the end of the second run and not during the first run as in forward run mode

change direction. The signals E _AK and ^! E _CK in turn assume their forward running state by passing through the signal. E ^ g or the signal E _{BG are} controlled. The arrangement remains in forward run mode until a reverse run signal is generated again.

The head switching sequence is maintained in reverse operation the normal progression of fields from odd to even; the phase continuity of ίο However, the chroma signal does not become track to track receive. In order to meet the FCC-Norm (Federal Comunitations Commission-Standards), the chroma phase is urgent at the beginning of each field irr with reference to the state at the beginning of the preceding half-line can move forward if one of the 15 images by 90 ° after.

Photocell devices 51 and "52 is operated. When switching during the reverse call operation

Specifically, the carrier reversal logic circuit 143 supplies, for example, from head D to head C, an inhibit signal X + Y to the backward end of a field to the beginning of the field runs logic circuit 138 whenever one of the A 'signals or switched, which is equal to 1 when one of the Y signals was originally recorded. Before proceeding with an aoing. This leads to a chroma phase reversal of the running direction of the arrangement, which results in a reversal of 180 °, which is caused by reversing the

Chromaphase is corrected by means of a chroma inverter 151 switched on in the circle. The use of the chroma inverter 151 is controlled by a chroma inverter logic circuit 152. The signal K from the reverse logic circuit 138, which is equal to 1 when the arrangement is operating in reverse mode, is reached via a field toggle switch 153 (described in more detail below). In order to achieve a proper synchronization, if 30 and appears at its output as K '= 1. The first drive pulse is locked each carrier, this output signal K' is given the carrier by the Photozelleneinrich- inverter logic circuit 152 on the Chromabevor itself. Every time something moves away. This is generated in the following way pulse J _c - which is achieved as above. The first is written from the Photozelleneinrich- causes a new field of the processing wegbewegende carrier is the carrier D. is taken of the 35 disc - which generates Chromaerste carrier pulse F _{l) (:} is determined by the carrier inverter logic circuit 152 a pulse C ₁₁ , which locks the error correction logic circuit 142, since the carrier has the effect that the chrominverter 151 does not pass the phase of the ger into the subcarrier of the chroma information in the field by reversing until the second pulse changes 180 °. In reverse operation, F _AC the carrier Λ for actuating the photocell 40 is reversed each time the chroma phase is initiated by the device; this happens after the first places are switched.

Impulse F _m:. The first carrier pulse F _c ' is blocked, Fig. 14 shows an example of slow motion when the carrier signal F _{l) (} is} equal to 1 and one of the operating modes, such as the switching and reproduction of photocell devices 51 c or 52 c of the heads At normal speed and at three, the carrier 21c only runs after the carrier 45 seventh of the normal speed , and it is prevented from receiving the first one. In slow-motion operation, the carrier pulse F _{AC is received by pressing} the forward key SS in the playback direction control circuit carrier pulse F ' _{B is} blocked when the carrier signal F _CK 127 and by pressing one of three slow motion is equal to 1 and when one of the photocell device keys in the speed control circuit 144 is activated 516 or 526. The carrier pulse 50 released The slow motion keys are F ' _A is blocked when the carrier pulse F _BK equals 1 a slow motion 1 key 58, a line tlupe-2 key 57 and one of the photocell devices 51 α or and a slow motion 3 key 56. If the slow motion 1-52 a is pressed. Key 58 is pressed, a signal Q ₆ becomes 0, which

The arrangement remains in reverse operation, ches in a slow motion control oscillator 154 the Erbis the forward key 55 is pressed. For this 55 generation of a square-wave signal A- causes. At this point in time, the signals P ₂ and P _{2 s take} the value 1 signal has approximately the same frequency as the Frean. The presence of the signal P., _s in the reverse sequence signal B ₀ in normal operation. If the time-forward logic circuit 138 causes this circle lupe-2 key 57 to be pressed, a signal Q ₁ becomes 0, and the arrangement switches to forward operation. This does not happen until the first 60 of the square-wave signal A- causes the signal E _{B (i} after the start of the signal P. to occur, the frequency of this signal now approximately equal to two As shown in Fig. 13. If the reverse run logic third of the normal frequency of the signal D is _0. If the circuit is switched to its forward run state, the slow motion 3 button 56 is pressed, the signal K changes its value from 0 to a Siso to 1, and signal Q _s to 1, which generates the pulse N in the slow motion reverse oscillator 154. The pulse N causes 65 to a manually variable resistor, so that the carrier reversal logic circuit 143 couples the value of the resistor changes its Fre signal M changes from 0 to 1, this signal frequency of twice the normal frequency of the Si in turn causes the carrier 23 the Radiairich- gnals D ₀ to the same current.

209637/356

25 26

The square-wave signal A- will cause the first two illustrated pulses E _{AC on the control logic}

circle 128 and appears at the exit as a single representation of the corresponding

talking slow motion control signal A, which is on a field, since the arrangement in the playback

Field change logic circuit is given. Operates at normal speed. the

the arrangement not in the field alternation mode 5 fourth and fifth pulse E _AC, however, lasts two

'(P _S = O), the slow motion control signal A appears . Field intervals and causes two displays

as a complementary signal A- _A at the output of the corresponding fields, while the third

Field alternating logic circuit and is triggered on a pulse E _{A (:} three reproductions. The im-

Slow motion converter 157 given. In this slow motion pulse E _{m :, E 1x} and E _m: are corresponding to the

converter is the slow motion control signal A- _A through io first and each subsequent one that goes negative

the pre-pulse G from the clock generator 132 temporally as pulse D ₀ , on the second and every further ins

quanusiert that the mean number of zero crossings positive going impulse D ₀ few. on the second

per second of a resulting signal Z _{0 the} same and every further negative going pulse B ₀

the mean number of positive zero crossings of the related.

Slow motion control signal A- _A is when the signal A- _A 15 As stated above, the coincidence of the no longer positive NuH passages per second as carrier advancing pulses F ' _A , F' _n , F ' _c and F' _a and the pulse G owns. Under these conditions pulse J ' _(: the generation of the pulses F _M :, F _m> F _vi: the waveform Z _{0 is} the same', frequency as in and F, _{IC of} the carrier reset logic circuit 141, where the pulse G . the waveform, Z _G is therefore these pulses in the effect the switching operation of the carrier beFrequenz identical to the shaft B. in the Zeitlupenum- _twentieth the occurrence of these pulses in terms of setters 157 (in the following will be described later), the temporal · consequence of the Switching of the heads is shown in means for eliminating ambiguities in front of FIG.
If one follows these notations in the lower part of the impulse G and the zero crossing of the signal A- _A Fig. 14, it can be seen that during playback, with can occur. ₂₅ normal speed, the fields 1 to 8 per one-The slow-motion control signal A- _A and the resulting _m al are reproduced; in operation with three sieve end waveforms Z ₀ for normal _{speed and te} [normal speed are then half for three sevenths of normal speed are three times in Figure 9, fields 10 and 11 twice each, Fig. 14 shown. The signal Z ₀ is coupled to the time field 12 three times, the fields 13 and 14 lupen logic circuit 133 , at its output ₃ o twice each and the field 15 three times, etc. again two pre-pulses G are given after switching on the . For playback with three-seventh normal order in slow-motion mode, a corresponding speed, the cycle 3-2-2 waveform G _(i generates. The slow-motion logic circuit 133 itself every seven fields.

is prepared by a signal W _s , which changes from 0 to 1, T _m slow motion mode changes the variable resistor for slow motion mode. The signal W _s 35 (i _m hereinafter described in detail) sequence given Frewird over the Schneilsuch logic circuit 131 to that of the slow motion control signal A _A via a con-control logic circuit 133, and takes the value 1 continuum of frequencies. Therefore, the Sean changes when one of the slow motion buttons 56, 57 and 58 in the frequency of repetitions and runs for each speed control loop 144 and the forward button selected slow motion speed according to a specific pattern 55 in the playback direction control circuit 127 pressed. However, the timing converter 157 controls the signal Z _{0 in} such a way that one of the Im- Hch two types of repetitions are present in the slow-motion logic circuit 133, pulse Jc which has positive pulses of 20 Mi- A set of fields is provided with of a given necrosecond duration, the number generated by the clock pulse C is repeated several times, while all shows which signal D ₀ occurs first after each zero crossing of the 45 other fields with a different number. If G _{0 is} equal to E _0, as is normally repeated, with these two operating each other, then a pulse J _c will only be differentiated as an integer by every clock number. Sample pulse C generated; therefore J _{c is} identical to C. wise, when reproducing with three sevenths normal-As FIG. 14 shows and as described above speed a set of fields in each case, the signal D ₀ controls the advancement of the 50 twice and all others are repeated three times each time . Carrier and the switching of the heads, whereby each This effect results in the smallest possible variation in the zero crossing of the signal D ₀ causes' each of the apparent speed of the process and head to move one position in its operating cycle: is, for example, preferably by one field five times movement, Movement, waiting (erasing), replay and the others at a replay speed (recording), moved on. In slow motion of three sevenths normal speed again, the signal D _{0 has} fewer zero crossings to admit. Will be a speed reduction of per second than in normal operation. If the zero crossing 2: 1 is selected, then each track is scanned twice, but gears appear during the vertical interval. When the speed is reduced by 3: I, each track is scanned three times because the zero crossing corresponds to the pre-pulse G. At a speed that corresponds to the switching and incremental switching by reducing the speed of 2.5, half of the tracks are controlled by the pulse J _c , which corresponds to the pulse C twice and the other half of the tracks three times. scanned.

As described above, the signals E _AC , As stated above, are consecutive

E _BC , E _{(: c} and E [) _C through the NuH passages of the field in slow motion playback of the same

Signal D ₀ formed. The track recorded when operating with normal 65 is derived, so that the second

speed and with three sevenths normal speed field is identical to its previous one.

speed signals E _AC generated by the signal D _G, In the illustrated arrangement is a device

^e bc> Ecc and E _DC are shown in FIG. The one provided that ensures that the output signal

is a standard line grid on a picture monitor; that is, the signal is a sequence of odd and even fields which is due to a half-line shift of the horizontal synchronization with respect to the vertical synchronization in each field. In this regard, as stated above, the phase relation of the switching of the heads during recording is such that each recorded field begins and ends immediately after the last equalizing pulse of the vertical interval (FIG. 12A). Even fields are recorded and reproduced by heads β and G and start at / 1 and end at A ', while odd fields are recorded by heads A and C and start at B and end at B' . To obtain an artificial interlocking of lines, odd fields are converted to even fields when an even field is required; on the other hand, even fields are converted to odd fields when an odd field is required. This is done by a half-line delay circuit 149 which is in series with the reproduced video signal during the horizontal scanning interval of each field (ie from A to A ' or from B to B'). The use of the half line delay circuit 149 is controlled by a half line delay logic circuit 158 . In general, this logic circuit 158 determines the field type required by the composite studio sync signal, the field type reproduced by the excited heads (odd fields are reproduced by heads A and C and even fields are reproduced by heads B and D) and sets the half-line delay circuit 149 as required one. The half-line delay circuit is always switched off during the vertical intervals B ' to A and A' to B. Specifically, in slow motion, half-line delay logic 158 causes half-line delay circuit 149 to turn on if it was off and turn off if it was on (ie, identical fields are displayed) at the beginning of each rescan.

When the playback signal is switched from one track to the next (ie, carrier movement and head switching proceed from one field to the next), it is not necessary to correct the line interleaving. In other words, since switching from one track to the next constitutes a normal transition from one field to the next, the half-line delay logic circuit 158 causes the state of the half-line delay circuit 149 to remain unchanged during the transition. The half-line delay circuit 149 thus remains in the signal path, if it was in the signal path before switching; on the other hand, it is bridged by the signal path if it was also bridged before switching.

As FIG. K) B shows, the activation of the half-line delay circuit 149 in the circuit is controlled by the electronic switch 148 , which in turn is controlled by the signal R received via the field changeover logic circuit 156 from the field changeover switch 153 . The signal R at the output of the field changeover switch 153 corresponds to the signal R ' which is received by the field delay logic circuit 158 through the field changeover switch. The half-line delay logic circuit 158 is controlled by the pulses B ₀ from the clock generator 132 and the pulses B ₀ from the slow motion logic circuit 133 . The pulses B ₀ indicate whether the station sync generator is generating odd or even fields. In this regard, the signal B ₀ in the clock generator 132 is brought into phase by the signal F _s which is received from the synchronous isolation circuit 121 through the quick search logic circuit 131 (pulse F). Like Figure 12A

ίο shows, the pulse F has the same duration as a horizontal sync pulse, which occurs at the beginning of every even field. The pulse F is formed in the synchronous separation circuit 121 by the coincidence of a monostable pulse triggered by the first sawtooth pulse and a horizontal line sync pulse.

The pulse F is coupled to the clock generator 132 via the quick search logic circuit 131 by bringing the square wave signal B _n into phase so that it equals 1 for every even field and 0 for every odd field (FIG. 12A). If the signal D ₀ (FIG. 12B or 14) is equal to I, either E _A0 or E _{co is} equal to 1. If D ₀ is 1, the signal from the end face A or from the disc face C is therefore reproduced. Therefore, when D ₀ is 1, an even field is reproduced. If D _{0 is} equal to 0, either E _no or E _{l) 0 is} equal to 1, in which case an odd field of the disk area B or the disk area D is displayed. If B ₀ is I and D ₀ is 1, the station is on an even field and an even field is coming from the disk. If B and D are equal (), the station is on an odd field and an odd field is coming from the disk. However, if B ₀ and D _{0 are} different (for example, B ₀ is 1 and D ₀ is 0), then the station is on a different field type with respect to the field coming from the disk. This is accomplished by having the half-line delay circuit 149 connected in series with the signal during that field. The half-line delay logic circuit 158 is designed so that when B ₀ and D _{0 are} the same, the output signal R ' is 1; if B ₀ and D _{0 are} different, the output signal R 'is equal to 0. If the signal R' is equal to 1, the electronic switch 148 bridges the half-line delay circuit. Is the signal /? ' equal to 0, the elec tronic switch ₇ switches 148 the half-line delay circuit 148 in series with the output signal.

. Since the equalization pulse train is identical in both odd and even fields and is not delayed by half-line delay circuit 149 , signal R 'is made I by field alternation logic circuit 156 during the equalization pulse train. This process is controlled by the pulse T _s , which, as stated above, lasts from the beginning to the end of the equalization period.

Furthermore, there is a chroma phase problem in slow motion operation from the measure in Re-scanning certain tracks to produce a continuous signal. When scanning a full The field becomes the phase at the end of the field with respect to the phase at the beginning of this Half image shifted forward by 90 °. If the field is then scanned again from the beginning, the result is a phase discontinuity of 90 ° in the chroma

29 30

signal at the beginning of the scan. This results in switching of the wearer and a one-time head

not just a destruction of the interconnection in the manner as it is related above

seize ens, but also a predominant .Under- with the slow motion operations was described. With

breaking of the color demodulation process in other words, a zero crossing of the

normal recipient. The Chromaphasenverschie- 5 signals D ₀ generated. A release of the image advance button

Exercise is also caused by the on or off 51 that the signal A- ₂ becomes 0, whereby

switch the half-line delay circuit 149 before the signal A becomes 1 again. If the key 51

influences. If you press the activation of the half-line delay again, another image can be

rungskreises 149 delays the chroma phases in order to be reached.

90 °, while its switch-off is the chroma phase io The arrangement shown and described advanced by 90 °. So if the half-line continues to be designed so that it is in an alternating delay circuit 149 can work at the beginning of a re-field recording mode, in which the scanning is switched on, then the half of the incoming fields, i.e. H. each phase shift of 90 ° to the second field caused by it is recorded. This will make the of the 15 recording time of the system caused by the resampling is doubled and one Phase shift of 90 °, which enables a Ge above normal speed. With all-chrome phase shift of 180 ° results. In the drawing, the arrangement is run at half the normal speed. Will the arrangement on the other hand switched off at the beginning of a resampling - then switched to playback at half speed, so compensated for the slow motion driven out by it, so the movement appears as called phase shift the phase shift normal, since the arrangement to play the inforum 90 ° by resampling. As a whole, as long as it takes to record. All The result is that in slow-motion operation that operating states which normally occur when restarting the chroma phase at the beginning of every second would be attainable are also in alternating field resampling of a field a phase shift can be achieved, with the exception that all time exercises of 180 ° occurs. This fact will be flawless speeds twice as fast. Will through use of the chroma phase inverter 151 grain - for example a normal reproduction selected, paused, ■ which the chroma phase each time then the movement appears twice as fast as reverses when the half-line delay circuit is normal.

149 is switched on. As FIG. 10B shows, in order to record the use of the chroma phase inverter 151 in the alternating field recording mode, the field changeover switch is controlled by the chroma distributor logic circuit 152, which is brought into its field alternation position, rather by itself the signal R ' from the field - the arrangement being controlled in toggle switch 153 as described above. Whenever their normal recording operation is brought up. If the signal R 'is equal to 0, the chroma inverter is switched on. If the Si field change position is brought, a gnal takes 7? ' equals 1, the chroma inverter circuit signal A- _{P has} the value 1 at its output. This 151 switched off. . Signal A- ^ is applied to control logic circuit 128. If the arrangement is to be in the operating state for In this circuit 128, the signal A ~ _f causes the still images to be displayed, then a stationary 40 signals P ₃ and P _{4 are the} same. In the field change key 54 in the playback direction control circuit 127, the logic circuit 156 causes the signal P ₃ , which presses 1. Thus, the signal Q 3 becomes 0, which is that the signal A _{A is} equal to the signal B ₀ , wel control logic circuit 128 blocks and the slow motion control made this one point of the signal A from signal A to 1 in normal operation Therefore, the signal Λ has no clock generator 132 is received. Since the frequency is zero crossings, whereby the _{signal Z 0} generated by the slow motion 45 of the signal B _{0 is} equal to half the frequency of the setter 157 and the corresponding A _{A is} at normal speed, the corresponding _{signal D 6} becomes 1. Therefore, the are not switched on the given the slow motion converter 157 signal heads and not that the assembly so that the heads of the same field operates keits slow motion advanced the carrier A _A precisely in Halbgeschwindiggeschaltet. Play back continuously under these conditions. The half-line delay 5 ° erases each head for two fields, then records logic circuit 158 and the chroma inverter logic records two fields, moves for two fields, circle 152 works in the same way as the next track, moves for two half-magnifying glasses. The half-line display is therefore on a further track and the hesitant circle 149 begins again during operation with still pictures. This means that each head records two alternating fields on each track during the horizontal scanning interval. To this the fields turned on. To eliminate the chrominverter head, a signal (Y through the 151 is turned on every time the field change logic circuit 156 is generated. Field delay circuit 149 is turned on. The signal / Y is in the fields from the change field designed so that it can be switched to the head logic by pressing circle 134. This signal is the same 1, the time signals E _AG , E _BÜ , E _co and E ₁₁₁₁ in the feed control circuit 159 are reached in a search and image feed button 51. By pressing 134 as in normal operation in the picture feed button 51 described above, a signal A - ₂ to 1, which is generated. If, however, the signal jY is equal to 0, then this is coupled to the control logic circuit 128. In 65, all head switching signals are blocked, that is to say the up-control logic circuit 12 8 causes the image feed signal / calibration heads are switched off. The field A -. ,, that the slow motion control signal A from 1 to 0 toggle logic circuit 156 is arranged so that the signal goes. This causes a simple feed in the gnal /? ' in alternating field work for odd

Fields is 1 and for even fields it is 0. Therefore the heads do not draw even fields, but only odd fields, with each head only recording once on one track.

In order to realize this, the signal β 'is made the inverse signal of the signal B ₀ . If only even fields are to be recorded, the signal /? ' made equal to the signal B ₀ . So that the arrangement is controlled during recording by the signal Z ₀ and not by the signal B ₀ , as would normally be the case, the signal W _s is switched to 1 by the pole signals, A- _{f also being} equal to 1, such as will be explained in more detail below.

Since all recorded fields are the same (i.e. all are odd) in the alternating field recording mode, it is necessary when reproducing a signal to switch alternately in the half-frame delay circuit at the end of each field, whether or not it is switched from head to head. As shown, the electronic sounder 148 controlling the half-line delay circuit 149 is controlled by a pulse B ₀ and not by the signal R , the substitution being made in the field toggle switch. The chroma inverter logic circuit is also controlled by the signal B ₀ , this being set in place of the signal R in the field toggle switch. In alternating field operation, the pulse K ' is blocked by the field changeover switch. As in normal operation, the switching of the half-line delay circuit 149 is blocked (R becomes 1), that the arrangement is brought into fast forward or backward running by a signal F _r or F _R equal to 0, the signals mentioned by the fast search Logic circuit 131 to field changeover logic circuit 156 can be supplied.

The arrangement is also equipped for a quick search mode which is used to move the heads from one point on each disc surface to another at about four times normal speed. In quick search mode, as in normal speed mode, the heads are kept precisely in step. On the other hand, there would be a loss of field continuity during subsequent reproduction. Therefore, the movement sequence is the same as that in normal speed operation. To place the arrangement in fast search mode, a fast forward key 510 in search frame advance logic circuit 159 is pressed. By pressing this key it is achieved that a signal F _F at the output assumes the value 1. This signal F, .- is applied to the quick search logic circuit 131, in which it causes the pulse 7 'on the output line T _s by an internal clock pulse T /. _{s is} replaced. This signal T / - _s has about four times the frequency as the normal pulse T. Therefore, the clock generator 132 supplies signals G, C and B _G , which have about four times the normal frequency. Therefore, the carriers and the heads are indexed or switched at about four times normal speed. The signal F ₁ .- also _{causes the signal P 2} ^ to 1 in the quick search logic circuit 131. The arrangement then moves forward. Furthermore, the signal F _r blocks the Jf ,, signal, so that this signal becomes 0. Due to the inertia of the carrier drive system, it is not practical to reverse the direction of movement of the carriers at the inner and outer boundaries when they are moving at search speeds. For this purpose, the photocell devices 69a and 69b, which are arranged on the carrier drive 21a, detect the approach of the head A to the inner and outer limits and reduce the carrier speed to normal speed while the direction reversal takes place. When the carrier 21a is at the edge

ίο approaches, either the photocell device 69 α or 69 b is excited. The signals X _AA and Y _AA resulting therefrom are given to the quick search logic circuit 131. In the quick search logic circuit 141, the signal X _AA or Y _AA , which are equal to 1, replaces the internal clock signal of the quick search logic circuit with the signal T, as a result of which the arrangement is decelerated to normal speed. This normal speed continues until the photocell devices X _AA or Y _{AA are} de-energized,

zo when the heads move away from the fringes. If the SchneHvorlauftaste 510 is released, the arrangement enters its operation with stationary Images.

A fast reverse key 511 in the search frame feed control circuit 159 is pressed to put the arrangement into fast search reverse. A signal F _{R is} generated by this measure. The signal F _R is applied to the quick search logic circuit 131, in which it causes the same operations as in the fast forward run. In this case, however, the signal P _{9 s} becomes equal to 0, as a result of which the arrangement goes into reverse.

In both quick search modes, the heads are shunted so that the arrangement works in purely electronic mode. The quick search signal F ₁ : or F _R blocks the electronic switch 148 (R = Q) so that the half-line delay circuit 149 is not switched on.

The arrangement is also designed to enter the still image mode when the quick search switches 510 or 511 are operated. To bring about this state, a signal F ₁ , or F _R with the value 1 is generated by the search frame feed control circuit 149 and passed to the playback direction control circuit 127, in which it triggers the control processes for the operation with still pictures.

As described below, the individual circles are explained with reference to FIGS. 15 to 38. In Three types of gates are used in these circles. One of these gates exercises a two-input logical DTL (Diode-transistor logic) »Nand« function off. A suitable NAND gate for this The purpose is one of the quadruple gates in an ST68 () A-Seric from Signetics Corporation. This Gate is represented by a semicircular block with a small circle at its exit. A second gate performs a four-input logical DTL Nand function with an extended node out. This gate is by a semicircular block with an arrow with a small one Circle shown at its exit. A suitable NAND gate of this type is one of the two gates from the Signetics Corporation SP616A series.

It has been found that either the two-input or the four-input NAND gate as an inverter works if all entrances but one float, d. This means that there is only a signal at one input.

209 637/356

33 34

A third gate is one and 174 at the inputs of the lower Nand circles

Two-input expansion gate, which is generated by a 172, 163, 164 and 166 of the associated FÜp-Flop-

semicircular block is shown. A suitable circuit switched on.

This type of gate is one of the quadruple. It is assumed that the normal

Expansion gates of the SP631 series of the Signetics Cor- 5 button 59, the slow motion 1 button 51, the slow motion 2-

poration. A fourth key 57 used in the circuits and the slow motion 3 key 56 in their normal

The element is a DC-triggered half-sideline stand, so it is on the flip-flop circles

/.K-Flip-Flop. A suitable flip-flop of this type is 162, 167, 168 and 169 given a binary signal 1, so

the Type SP 620 A from Signetics Corporation. that the output signals of the lower Nand circles

The flip-flop circuit can asynchronously with P _r and io 172, 163, 164 and 166 a binary signal 1 and the

/ ^ - input signals can be set or reset output signals of the upper Nand circles 161, 171,

the; on the other hand, it can be a binary signal 0 synchronously using 173 and 174. Will be one of the

When / and K input signals are pressed together with buttons, the signal on theirs changes

be switched with a clock signal. If the asyn signal line is changed from a binary signal 1 to a binary

chronologically switched, the flip-flop behaves like 15 signal 0. Since this signal is applied to the lower Nand

a /? 5 flip-flop. If it is switched synchronously, then circles of the other three flip-flop circles are given

the circle behaves like a / iC flip-flop. is, it follows that the output signals

In the following, the individual circles of the lower NAND circles of the flip-flop circles, which are for the blocks of the control loop 117, are described. The signals associated with the other three keys, becoming 0, are represented as they are in the recording mode, which means that each of the other three flip-flop circuits are present. The circle for the speed to be reset, which was previously set, speed control device 144 is shown in FIG. The zero signal on the signal line of the pressed This circle contains the normal key FS9, the time key is still on the upper Nand circle of the lupe-1 key 58, the slow-motion 2 key 57 and the associated flip-flop Circle given, whereby the slow motion 3 button 56, it being with these buttons 25 output signal of this upper Nand circle to 1 to short-term contact pushbuttons. Each button will. This binary signal 1, which is connected to the lower Nand is connected to a logic circuit, which is output in such a way that the output signal is formed that, when the key is pressed, an associated lower Nand circuit is supplied to a binary zero control signal , an associated signal signal becomes. The output signal of each of the lower lamp is energized and the logic circuits of the other 30 Nand circuits 172, 163, 164 and 166 are brought into their de-energized state via a key. The associated inverter circuit 176 is switched to a switching circuit. In this context, each key has transistor 177 , which has a normal position for the keys, in which it excites a signal lamp 178 belonging to the direct current signal,
on its associated line, and a second position, which is pressed, the output signal of the upper Nand circuit 161 , in which it applies the signal line to 35 of the normal flip-flop circuit 162 to the Lei ground. The signal line of the normal key 59 is given to directionP _t . Therefore, this signal P _{1 is} a binary signal 0 at an input of an upper NAND circuit 161 when the arrangement is not in the normal of a normal key flip-flop circuit 162 and an operation. On the other hand, this signal is an input from the lower Nand circle 163, 164 and 166 binary signal 1 when the normal key 59 is pressed. turned on, which in a slow motion 1 flip-flop 40 The signal from slow motion 1 flip-flop circuit 167 is circuit 167, a slow motion 2 flip-flop circuit 168 at the output of the lower Nand circuit 163 or a slow motion 3 flip-flop circle 169 and appears at Q ₆ , where Q _{6 are} when the time is printed. Correspondingly, the signal line of the slow-motion 1 key 58 = 0 and at other times = 1. Magnifying-1 key 58 to an input of an upper. Correspondingly, the output signal from the lower Nand circle 171 of the slow-motion 1 flip Flop circle 45 Nand circle 164 of the slow-motion 2 flip-flop circle 168 and received at one input each of the lower Nand circles at Q ₇ , with Q _{7 connected} with the slow motion 2- 172, 164 and 166 pressed, which in normal key 57 = 0, and at other times = 1. from flip-flop circuit 162, in slow-2 flip-flop circuit output signal of the slow-3-flip-flop circuit 169 168 or in slow motion 3 flip-flop circle 169 ent is removed from the lower Nand circle 166 , are held. The signal line of the slow motion key 58 50 given via an inverter 179 and appears at 0 _H. is to an input of an upper Nand circuit 173 Therefore, when the slow-motion 3 button 56 is pressed, Q _s = 1 of the slow-motion 2 flip-flop circuit 168 and at each and at other times = 0. A second, at Q _{0 to} an input of the lower Nand circles 172, 163 and the stepping output signal is switched on by the output of the 166 , which in the normal flip-flop circle upper Nand circle 174 in slow motion 3 flip flop 162, in slow motion 1 -Flip-flop circle 167 or in 55 circle 169 decreased. Q ₉ is therefore equal to 0, unless slow motion 3 flip-flop circuit 169 are included. Ent- when the slow motion 3 button 56 is pressed.
The signal line of the slow motion 3 key is speaking so that the arrangement is always in normal operation when switched on 56 at an input of an upper Nand circuit 174 , a delay of the slow motion 3 flip-flop circuit 169 and each approximate circuit 181 is for Delay in feeding one input of the lower NAND circles 172, 163 60 binary signal 1 into the normally closed and 164 connected, which are provided in the normal flip-flop contacts of the normal key 59. To secure circuit 162, and determine in slow-1-flip-flop circuit 167, that the keys in the playback Richtungsim Zeitjupe-2-Flip'Fiop circuit 168 are included. loop 127 are ineffective if they are kept in-gedrück The outputs of the lower NAND circuits 172, 163, system state, the four signal 164 and 166 are connected to the other inputs of the obe- 65 lines of the normal, slow motion -1-, ZeiUupe-2-ren Nand circles 171, 161, 173 or 174 of the pull and slow motion 3 key 59, 58, 57 or 56 are switched on to the belonging flip-flop circles. Correspondingly, inputs of a NAND gate 182 are routed. The output of the upper circles 161, 171, 173 output of this gate 182 is via an inverter 183

to Q ₁₃ , where Q _{13 is} equal to 1, except during the time when one of the four keys is held down.

The rest of the circuit according to FIG. 15 acts it is a control circuit which is used to display a specific position on the disc will. A cycle motor 184 (Fig. 20) provided, which has a (not shown) pointer that according to a selected speed and rotates clockwise or counterclockwise direction on a scale (not shown) and indicates the position of the heads within the system's record. Another, as a director's marker used pointer (not shown) is magnetically connected to a clock indicator, see above that it normally rotates with this clock generator. If a director key 512 is pressed, so the director's marker stops rotating and remains in a fixed position on the scale, whereby the location of a specific recorded event is displayed. If the director key 512 is used for pressed the second time, the direction marker is released, which is due to the magnetic Attraction immediately seeks out the tact indicator and rotates with it. The marker is then held the next time the direction button is pressed.

As shown in Figure 1.5, the push button 512 has two Positions. In its normal position, the control button 512 connects a binary signal 1 with its signal line; When pressed, the button connects a binary signal 0 with the signal line. The signal line the director's button is about an integration circle

186 to the key input of a / - ^ - binary element

187 is switched on, which is switched as a 5 /? - flip-flop to switch states for each pulse at its key input. The K input of binary element 187 is connected to a binary 1, while the / input is connected to QVL, which is a binary 1 unless the record button 52 is pressed. The signal Q 12 is also applied to the P _r input of the binary element 187 _{via an inverter 185, the P A} , input of the binary element 187 being connected to ground. If the record button is pressed, the binary element 187 is thus reset.

The output of the binary element 187 is connected to a circuit 189 via an inverter 188, which operates a director's brake 191. The director brake 191 stops the movement when excited the director's needle. If the direction key 512 is pressed, then the input of the integration circuit is now to ground, as a result of which the capacitance is discharged and the state of the binary element 187 is changed, see above that the state of the director's brake 191 also changes. The output of binary element 187 is further connected via an inverter 193 to a switching transistor circuit 194, which the excitation a signal lamp 196 belonging to the director's button.

Fig. 16 shows the circuit of the playback direction control loop 127. This circle contains four operating buttons: the receptacle 52, the Reverse button 53, still picture button 54 and forward button 55. Each button sets an associated flip-flop circuit, which is related to the speed control circuit 144 corresponds to the circle described. In this context, the buttons have 52, 53, 54 and 55 a normal position in which a binary signal 1 occurs the associated signal line is given, and a depressed position in which a binary signal 0 to the associated signal line is given. The signal lines of the record button 52 and the reverse button 53 are connected to upper NAND circles 197 and 198 of associated flip-flop circles 199 and 201, respectively. The signal line of the record button 5 2

ίο is one at lower Nand-circles 202, 203 and 204 Reverse flip-flop circuit 201, a still picture flip-flop circuit 206 and a forward flip-flop circuit 207 turned on. The signal line the reverse button 53 is coupled to the lower Nand circles 208, 203 and 204.

The signal line of the forward key 55 is routed via a NAND circuit 209 and an inverter 210 to an upper NAND circuit 211 and the lower NAND circuits 208, 202 and 203 of the other three flip-open circuits 199, 201 and 206. The other input of the Nand circuit 209 receives the signal O ₁₃ , which is supplied by the speed control circuit 144 via a manual direction switch 5101. As mentioned above, the signal Q _{13 is} equal to 1, except when one of the four keys in the speed control loop is pressed. Furthermore, a binary signal 1 comes from the Q ₁₀ to the normally closed cycle of the key 55, which is a delayed binary signal 1 which is supplied by the delay circuit 181; therefore, the arrangement automatically switches to forward operation when it is switched on.

The signal line of the freeze frame key 54 is routed to one input of a NAND gate 211, the other input of which is from the signal F ₁ . + F _R , which is normally equal to 1, except when the fast forward button or the fast forward button is pressed. The output of the NAND gate 211 is passed via an inverter 212 to the lower NAND gate 208, the lower NAND gate 202, the upper NAND gate 213 and the lower NAND gate 204. Therefore, the arrangement enters the still picture mode when the still picture key 54 is depressed. If the fast forward or fast backward button is pressed, the arrangement goes into operation with still images when the buttons are released.

The outputs of the lower NAND circles 208, 202 and 204 are fed via an inverter 214 to a transistor switch 215, which thus controls the indicator lamp 216 belonging to the respective key. The output of the lower NAND circuit 203 of the flip-flop circuit 206 is coupled to a NAND circuit 217, the other input of which _{receives the signal Q 11} from the control logic circuit. The signal Q _u is equal to 1, except when the operation with still images is selected by a variable speed control, as will be explained in the following. The output of the lower NAND gate 208 of the recording flip-flop circuit is at Q ₁ . Q ₁ is equal to 1, except when the arrangement is operating in the recording mode ( Q _{1 is shown} equal to 0 since it is assumed that the arrangement is in the recording mode). The output of the upper NAND gate 198 in the reverse flip-flop circuit 201 is fed to Q ₂ , so that Q _{2 is} equal to 0, except when the arrangement is in reverse operation. The output of the lower NAND gate 203 in the flip-flop circuit for still images 206 is led to Q ₃ , so that Q _{3 is} equal to 1,

except when the arrangement is in operation for still images. For the forward flip-flop no exit is required as the. Arrangement goes into forward operation when the the other three flip-flop circles are not set.

A logic circuit which can be used as the search frame feed control circuit 159 is shown in FIG. In this circle 159 there are three pushbuttons, namely the fast forward button 511,

229 switches. One of the transistor circuits 234, 235 belongs to one of the slow motion keys 58, 57 and 56 , respectively. The resistor 232 belonging to the slow motion 2 key 57 and the resistor 233 belonging to the slow motion 1 key 58 are set so that a reset resistance value is formed, whereby a predetermined time reference of the clock pulses is achieved by the double base trigger 227 when the slow motion 2 key or slow motion 1 key is pressed. A to

the fast reverse button 510 and the resistor 236 belonging to the frame forward slow motion 3 button is shown with push button 51 . Each button has a normally manually operated lever (not shown), usually closed, in which a binary is connected in the control panel, whereby the time reference of the signal 0 on the associated signal line can be manually regulated. The resistor 231 , which is in series with the resistor 236 and a normally open position, is used when the switch is closed by pressing a binary 15, the signal 1 determined by the resistor 236 on the associated signal line is used in this way put that it is slightly above. The signal lines of the fast forward key 5 11, one of the fast reverse key 510 corresponding to the normal speed and the image forward value is located.

The push button 51 is supplied by the slow motion 3 logic circuit 169 via corresponding switching transitions

sistorkkreis 218 to associated indicator lamps 219 20 signal Q- ₈ is normally switched the same, whereby these lamps when the 0 is pressed, except when the slow-motion 3 button 56 is pressed. Keys are energized. When Q ₈ equals 1, the resistors are 231

The fast forward and fast reverse and 236 connected in series to capacity 229 . The signal lines are connected via corresponding inverter signal Q ₁ from line magnifier 3 logic circuit 168, which circuits 220 and integration circuits 221 to the corresponding 25 is normally equal to 1, except when the slow motion speaking outputs F _R and F _t - switched on. Since the 2 key 57 is pressed, an inverter 237 fast forward key 511 and the fast reverse to the associated circuit 234, 235 , key 510 under normal conditions in a binary, whereby the slow motion 2 resistor 234 are normal-zero , the signals S _R and F _{r are} switched off in ways by the capacitance. All operating modes equal 1, except if the fast resistance is connected in series to the capacity, the forward or fast reverse button is pressed. when Q ₁ becomes equal to 0, that is, when the slow-motion output of the fast-forward inverter 220 and the 2 key 57 is pressed. The signal Q _1. , Which is a high-speed reverse inverter 220 , is normally equal to 1, except when the slow motion inputs of a NAND circuit 222 is pressed 1 key 5 8 is switched via an inverter, the output of which is via an inverter 223 to the 35 238 to the associated transistor circuit 234, F ₁ : + / - "^ - output is switched on. Therefore, the 235 , in order to switch off the resistor 233 , has the Ff + Ffl output the binary value 1, except if not except if Q ₆ becomes 0. This happens if neither the fast forward or fast reverse slow motion 1 button 58 is pressed,
button is pressed. Therefore, the sequence of the slow motion rule

The image feed key 51 is designed so that 40 signals A- from the frequency of the clock pulses, A _{n is} normally equal to 0 and the binary value 1, the frequency of the clock pulses in turn assumes when the key 51 is pressed. Which depends on which slow-motion button was pressed. The signal line of the image feed key 51 is an inter- Frequency assumes a predetermined value when the network circuit 224 is turned on. If the front, slow motion 1 or slow motion 2 key is released, the signal A _{2 is set} to 45. If the slow motion 3 key is pressed, the

slight delay through the integration circuit 224 to 0.

The logic circuit for the slow motion control oscillator 154 is shown in FIG. The illustrated oscillator 154 includes a 7 / C binary element 226 that is triggered by clock pulses. As shown, the /,. Inputs are connected to a positive voltage, while the P ₁ and / ',. Inputs are connected to ground. The complementary output of binary element 226 is at A-. The clock pulses that trigger the / -tf binary element 226 are generated by a double base clock circuit 227 , the output of which is connected to the clock input of the / -K binary element 226 via an inverter 228 .

Adjustable frequency.

19 shows a circuit for the control logic circuit 129. The reverse signal Q- ₂ according to FIG. 16 is applied to the line P ₂ via an inverter 239 and an integration circuit 241 . The reverse signal Q- ₂ is normally 1; therefore, P _{2 is} equal to 1 during the forward mode, the recording mode or the still image mode, and it is equal to 0 in the reverse mode.

The recording signal Q ₁ is applied to the output P ₄ via an inverter 242 and an integration circuit 243 . The recording signal AQ _x is normally equal to 0 during recording operation and in reverse operation, in operation with standing pictures

The double base clock circuit 227 contains a capacitance 6.degree. Or equal to 1. Therefore, 229, which is in series with parallel connected resistors, the signal P _{4 is} only during the recording levels 231, 232 and 233 . Through these resistances, the discharge of the capacitance is increased to 229

a predetermined voltage determined, whereby the

operation equal to I. The output signal of the inverter 242, ie the signal P ₄ , is ignited via an inverter 234 to the lower input of a NAND gate 246. The contradictions 231, 232 and 233 65 give. The upper input of the NAND gate 246 is in series with a transistor 234, which holds the normal signal P ₁ , which in normal operation is more likely to be connected to the associated resistor
a second transistor 235 in series with the capacitance

equals 1. The output of the NAND gate 246 is at the upper input of a second NAND gate

39 40

247 led. An output signal of the first NAND ^{1 is received by} a third NAND gate 261 . The signal

Gate 246, which is equal to 1, is returned if A- _t + A ₂ is equal to 1, except when operating with standing

the arrangement in the marking mode or in the picture (O ₃ = 1), if the picture feed button

not in normal playback mode. The (A- ₂ = l) is pressed. The output of this

other input signal · of the second NAND gate 247 5 Nand <iatters 259 is via an inverter 262 and

is received by a third NANDR gate 248 ^ an integration circuit 263 is sent to the output A.

whose one entrance; the reception signal P ₄ and give its logical equation
the other input of which is the alternating field signal A _r

received via an inverter 249 . The alternating field- A (P- ₄ · K! · A ₁ + Α '), · (Α ₂ + AJ
signal Λ /. · is normally equal to 1 and is single-io. .
Loaned to 0 when the arrangement is alternating. A device is also provided for image operation. Therefore, the second Nand- the arrangement in the operation with still pictures gate 247 an output signal 1, if the arrangement to bring, if the voltage belonging to the resistor 231 reaches the lower end of its field in the playback mode or in the normal lever. In operation and not in alternating field recording 15 in this regard, the lever actuates a switch operation is located. The signal from the second NAND gate 5102, which gives an output signal R ₂ to a NAND 247 , is applied to an input of a fourth NAND gate 264 , the other input signals of which are given by the gates 251. The other input of the fourth signal is K ', Q- ₉ and G- ₄ . The output signal of the NAND gate 251 is at the output of a fifth gate is given to the output Q _u , which NAND gate 252, which actuates the signals P- ₄ , K 'and _{y4 1} 20 an indicator lamp 216 for still images, is inverted. The signal A _x is equal to 0, except when the This output signal is normally equal to 1, arrangement in operation with still images or except when the switch is operated, and is operated in the fade-in mode (ß _s = 0). The signal K 'is also applied to a NAND gate 266 , which is equal to 1 if the arrangement is in the forward mode other input signal is the signal Q ₃ from the flip-flop, and 0 if the arrangement in the back circuit 217 for still pictures is. Hence the away operation is working. The signal P- ₄ is the complete output signal of this NAND gate 266, normally a mental signal of the recording signal. Therefore this is equal to 1, except when the freeze frame button is pressed, output signal of the fifth Nand gate 252, which results in Q _{3 being} equal to 0, or when it is equal to 1, unless the arrangement in the playback lever operated switch 5102 is in slow motion. 3-Wiederj operation (ie P ₄ = 0) or in forward operation 30 output operation is operated. This causes the (K- 1) to work and when A ₁ equals 1. The off signal A ₁ becomes 1, so that the image feed circuit output signal of the fourth NAND gate 251 is blocked via the NAND circuit 261 and can unblock an integration circuit 250 to the output W.

give, where the logical equation F i g. 20 shows a logic circuit which is called ψ __ p_. j ^ '. ^ 4. ρ · λ (_ 4- p_ .p_ 35 clock motor control loop 267 can be used. In this. 4.1414 circuit, the clock motor 184 is running at a speed. Therefore, W is 1 when P ₄ is 0 (ie the one operated, which corresponds to the speed of the head; arrangement works in playback mode), K ' switching corresponds to and is rectified to this equal to 1 (ie the arrangement works in forward mode. In this regard, the signal E _DG controls from operation) and A _{1 is} equal to 1 (ie, the arrangement works 4 ° head return control logic circuit 136 the clock motor 184. tet in operation with still images) or if specifically, the signal E _DG via an inverter 261 P ₁ does not equal 1 and P ₄ equals 0 (that is, the arrangement on the clock input of a / -Ä binary element 269 works in normal playback mode), which is switched as /-.K- flip-flop. | i) if the arrangement is in alternating picture recording The main output signal and the complementary operation works (P ₄ · A- _P = 1). 45 output of the /-.K-Binärelementes be 2.69 The alternating field signal _F A from inverter 249 to the inputs of corresponding Nahd gates is applied via a further inverter 253 to an input 271 and 272nd The other input signals are given to a NAND gate 254 , the other NAND gate 271 and 272 of which receives _{the recording signal P 4} via an input. The output inverter 273 from the output of a monostable chalky NAND gate 254 is received via an inverter 50 ses 274 . This monostable circuit 274 256 and an integration circuit 257 at the output is given by the pulse E _D0 at the output of the inverter P ₃ , the logic equation 268 being triggered, which is buffered by an emitter follower 276 P = PA- and diffused by a differentiating circuit 277 ^{34 is} denoted. This ensures that the Ausist. Therefore, P, is equal to 1 if P ₄ and A- _F equal 1 55 output pulses of the NAND gates 271 and 272 are unabsind, which happens when the arrangement is dependent on the width of the pulse E _DÜ a beselhalbbild -betrieb and im Recording mode is working. have the right pulse width.

The slow motion control signal A- ' is applied to an input. The output signals of the NAND gates 271 and 272

The output of a NAND gate 258 is given, the others of which are generated via corresponding inverters 278 and 279

Input the signal 60 given an inverse circle, which four Nand-

P 4. #_ '4. Contains λ_ gates 281, 282, 283 and 284 . The Nand

⁴ * gates 281 and 283 are connected to inverters 278 and

from NAND gate 252 . Hence, the signal goes through NAND gates 282 and 284 to inverter 279

A- locked when the arrangement is coupled to the recording. The other input signals of the Nand

operation, in forward operation, and in operation with 65 gates 281 and 282 come from the main output

standing pictures works. The output of a / -K binary element 286, while the Nand-

NAND gate 258 is fed to a second NAND gate 283 and 284 input signals from the complete

259 given, which also received the signal A- _x + A ₂ from the mental output of the element 286 . The

Reversal signal K from reverse logic circuit 138 (FIG. 22) causes the switching state of binary element 286 to be changed. The signal K is applied to the P _r input via an inverter 287. The clock pulse for this ./-/C binary element is received by inverter 273. The output signals of the four NAND gates 281 to 284 are applied to transistor circuits 294, 296, 297 and 298 via corresponding inverters 289, 291, 292 and 293 in order to regulate the DC voltage applied to the windings of the clock motor 184. Therefore, the direction of rotation of the clock motor 184 is changed when K is changed. However, the direction of rotation of the drive motor is not changed until the signal E _ÜG arrives.

The signal K at the output of the inverter 288 is given to the output K- via a normal reversing step switch 5103. If this switch is open, so. it is possible to switch images in the reverse direction if the control switch for variable speeds is in the position for still images.

21 shows a logic circuit which can be used as carrier logic circuit 137. In this circuit, the signal E- _AG from the head logic circuit 134 (Fig. 36) is combined with the signal E _Ba from the head logic circuit to form the signal F- _ÜG (Fig. 12b). Furthermore, the signals E- _BG and E- _{CG are combined} by the head logic circuit to form the signal F- _CG . In addition, the signals E- _Cü and Ei) _{G are combined} by the head logic circuit to form the signal F- _BG . Finally, the signals E- _U q and E _AG are also combined by the head logic circuit to form the signal F _AG. Specifically, the signals E- _{A (}} , E- _Bü , E-QQ and E- _Dü from the head logic circuit 134 (Fig. 36) are given to corresponding inverters 299, 301, 302 and 303 to generate the signals E _AG , E _BÜ , E _ca and E _00. The signals E _CG , E _BG and E _A0 are given to associated outputs. The signals E _AU , E _BG , E _C q and E ₀ Q are still transmitted via corresponding inverters 304, 305, 307 and 308 are given to the upper inputs of NAND gates 309, 311, 312 and 313. The signal E- _AG at the output of the inverter 304 is also given to the other input of the _NAND gate 313 belonging to the signal E-0G, whereby the signal F _{CG is} formed which has the logic equation

Fcc, - Edg + Ecg

owns. The signal F _CG via an inverter 314 is applied to the output of the signal F- _CG . The signal E _BG at the output of the inverter 306 is still given to the NAND gate 309 belonging to the signal E _AG , whereby the signal F _{DG is} formed at the output of this gate, which the logic function F _ÜG equals E _AG + E _ßG owns. The signal FDa is given to the output F _DG . The signal E- _CG is also applied to the NAND gate 311 belonging to the signal E _BG , whereby the signal is at its output

'AG

is formed. This signal F _AG is given to the output F- _A0 via an inverter 316. The signal EJ) ₀ at the inverter 308 is still given to the NAND gate 312 belonging to the signal E ₀₀ , whereby the signal at the output

+ ^E üa ⁼ F

BG

is formed. This signal F _BG is given to the output F _BG .

Circuitry for the reverse logic circuit 138 is shown in FIG. 22 shown. As stated above, this circuit is used to swap the signals E _AG and Eq ₀ at the outputs E _AK and E _CK and the signals F _AG and F _CG at the outputs F _AK and F _CK in order to initiate the reverse run of the arrangement .

ίο The signal P _{2 s} , which is received by the quick search logic circuit 131 (Fig. 30), is 1 for forward operation and 0 for reverse operation. This signal is via an integration circuit 317 and an inverter circuit 318 to the P ^ input a first / -K binary element 319, which is connected as a / -F flip-flop, and given via a further inverter 321 to the P _r Einarig of the first binary element. The prepulse G from the clock generator 132 (FIG. 31) and the signal E- _liG from the carrier logic circuit 137 (FIG. 21) are applied to the clock input of the first binary element 319 via a NAND gate 322. If the arrangement works in forward mode, the main output signal of the first binary element has the binary value 1. If the arrangement is brought into reverse operation, P., _s becomes 0, whereby a binary signal 1 is sent to the P ^ input of the first binary element 319 and a binary signal 0 is applied to the P; input. However, the first element does not switch until the next prepulse G is received. The C pulses are blocked by NAND gate 322 during pulse E _BG. This ensures that the arrangement does not start running backwards if the backwards / up button 53 is pressed during the entire pulse E _BG.

The main and complementary output signal of the first binary element 319 is applied to the P, - or P ₁ , - input of a second / AT binary element 323, which is connected as a / -it flip-flop. This second flip-flop 323 does not switch until it receives a pulse E _BG from the carrier logic circuit (FIG. 21) and a pre-pulse G. Furthermore, this flip-flop does not switch if there is no .Sf + Y signal, ie if one of the photocell devices 51 and 52 is excited. The logic circuit which performs this function contains a NAND gate 324 which receives the X + Y signal from the carrier reversal logic circuit 143 (FIG. 25) and the prepulse G at its inputs. The output signal of this NAND gate 324 is applied to an input of a second NAND gate 327 via an inverter 326. The other input to the second NAND gate 327 is the signal E _BG ; therefore, the output signal of this second NAND gate 227, which is applied to the clock input of the second flip-flop 323, in the absence of the signal E _BG and the pre-pulse G and in the absence of the X + Y signal is equal to 1. The output signal is only then 0 if the pulse E _BG and the pre-pulse G are received and if the signal X + Y is equal to 1. Since the pre-pulse G is clocked in such a way that it lies approximately in the rise time of the pulse E _BG , the flip-flop 322 switches over in its states at the beginning of an E ^ g pulse.

The complementary output signal of the second flip-flop 322 is given as signal K to the output K via an inverter 328. The signal K is still given to an inverter 329, whose

Output signal is equal to the complementary signal K- . This signal K- is given to the output K- .

The exchange of the signals E _M} and E _CG is carried out in two exclusive-OR gates 331 and 332. The OR gate 331 contains an upper NAND gate 333 which receives the signals K and E _AG as input signals, and a lower NAND gate 334 which receives the signals K and E _{CG as input signals.} The other exclusive-OR gate 332 contains an upper NAND gate 336, which receives the signals K and E _CG as input signals, and a lower NAND gate 337 which receives the signals K- and E _{AÜ as input signals.} The output signals of the NAND gates 333, 334 and 336, 337 are given to Nor gates 338 and 339, respectively. The output signal of the upper exclusive-OR gate 331 is given to the output E _{AK via an inverter 341.} The output signal of the lower exclusive-OR gate 332 is given via an inverter 342 to the output E _CK . Therefore, the signal E _{AK is} equal to the signal E- _Aa and the signal E _{CK is} equal to the signal E _CG , if K = 1. However , if the signal K ' is 0, the signal E _AI ^ is equal to E _CG and that Signal E ' _CK equals E _A0 . '■

The signals F _CG and F _AU are exchanged in the same way, that is, two exclusive-or gates 343 and 344 are provided to which the signals F- _AG , F- _{(: a} , K and K- are given The output signal of the upper exclusive-or gate 343 is applied to the output '/ ^; and the output signal of the lower gate is applied to the output F _CK . Therefore the signal F _{AK is} equal to F _Aa and the signal F _{CK is} equal to F _{(: u} , if K is equal to 1. If K is equal to 0, then F _{AK is} equal to F _{C (}} and F _{CK is} equal to F _AÜ .

Reverse logic circuit 138 also includes means for generating a 20 microsecond pulse labeled M each time K changes from 0 to 1 or vice versa. This device comprises a monostable multivibrator 346 which is formed by two NAND gates and a capacitance, the capacitance determining the length of each pulse. The signals K and K- are applied to the inputs of the monostable multivibrator 346 via corresponding differentiation circuits 347 and 348. Since the monostable multivibrator 346 responsive to only positive pulses, the pulse K is provided a pulse for each increase, with each increase in the pulse K 'is present. The output signal of the monostable multivibrator 346 is given to the output N via an inverter 349.

A circuit for the carrier control logic circuit 139 is shown in FIG. This is a circuit for correcting errors that can occur when the heads are switched. In this regard, the circuit only allows the carriers to move away from the photocell devices 51 and 52 in the correct order, that is, B follows A and then C and D, since it disables the pulse F ' which would normally be movement of a carrier cause that is not supposed to move. In the forward mode, only the carrier D can move incorrectly; this carrier can move away from the photocell devices 51 and 52 at the same time as the "carrier". Therefore, the logic circuit prevents the pulse F'D from becoming 1 while either the photocell device 51rf or 52rf on the channel D is in operation when F _AC equals 1 (ie Λ ',, or Y _n = I ).

In reverse operation, this circuit performs two functions in the same way. First, the circle allows the carriers to move away from the end stop switch in the correct order (ie, C follows D and then B and A). Second, immediately prior to moving away from the end stop switches, each carrier does not receive either of its two carrier pulses so that the carriers travel in the correct tracks.

In the circuit according to FIG. 23, the to the carrier A and the carrier belonging to reverse logic circuit 143 signals coming X _A and Y _A to a first NAND gate, where the 351st Belonging to the carrier signals B X _B and Y _B are applied to a second NAND gate 352nd The signals X- _c and Y- _c belonging to the carrier C are applied to the inputs of a third NAND gate 353, while the signals X- _D and Y-it belonging to the carrier D are applied to a fourth NAND gate 354. The output of the NAND gate 351 to the Λ-carrier signals is applied to one input of a fifth NAND gate 356, the other inputs of which are the reverse signal K- and the signal Fug from the reverse logic circuit 138 (FIG. 22). The output signal of this fifth NAND gate 356 corresponds to the signal F _HG as long as the arrangement is in reverse operation (K- - 1) and one of the signals X _A and Y _{A is} interrupted; on the other hand, the output signal is equal to 1. The output signal of the fifth NAND gate 356 is applied to an input of a sixth NAND gate 357, the second input of which receives the signal F _AK from the reverse logic circuit 138. The output signal is sent to output F- _A .

Therefore, the signal F _'A corresponds to the signal F _AK in forward operation, as FIG. 12B shows, with the last half is the pulse F _AK by the pulse F _GB locked when the assembly is in reverse operation and either the signal X _A or signal Y _{4 is} present (ie, carrier A is at one of its endpoints), thereby preventing head A from starting before head B. . '

The output of the second NAND gate 352, which belongs to the X _fl - and K _ß photo cell carrier, is connected to an input of a seventh NAND gate 358, the other input signals of which are the signals K ' and Feg . The output of this seventh NAND gate 358 is on. an input of an eighth NAND gate 359 is switched, which continues to receive the signal F _GB . The output is connected to output F ' _{! S.} This logic circuit operates in the same way as the F ' ₄ circuit described above.

The output of the third NAND gate 353, which belongs to the X-q and V-c signals, is connected to an input of a ninth gate 361, which also receives the reverse signal K ' and the signal F _{l) G.} The output of this ninth NAND gate 361 is connected to an input of a tenth NAND gate 362, which receives the signal FCK at its second input. The output of this NAND gate is led to the output F _c . This logic circuit also works in the same way as the F '^ circuit described above.

The output of the fourth NAND gate 354, which

45, 46

It belongs to the X-jr and £> _y signals is on (see Fig. 12B). The output signal of the NAND gate to an input of an eleventh NAND gate 263 is switched to the output 369 via an inverter 372, the other inputs of which are given the reversing signal KF _AC.

and record the signal F _AK. The output of this A circuit which is used for the carrier reversal

The eleventh NAND gate 363 can be used with a twelfth NAND logic circuit 143, the gate 364 is switched on in FIG. 25 and continues to provide the signal. When the carrier takes up one of its end F _00. The output of this NAND gate are 364 points, the circle determines when the Prove to the output F _'D turned on. Hence the movement of the carrier is to be reversed. Furthermore, the pulse F ' _D delivers blocked during the pulse F _AK when the circuit ΛΉ-Y signal for the reverse logic, the arrangement is operating in the forward mode (K = 1) in circuit 138 (Fig. 36). In this respect, and one of the photocell signals X are ₀ barren Y ₀ upstream signals X _A, X _B, X _c, X _0, Y _A, Y _B, Y _c and Y ₀ ie of the hands is (, the carrier D is located on a photocell via corresponding inverters 373, 374, its end points). Therefore, the carrier D. 376, 377, 378, 379, 381 and 382 cannot move with the carrier A on the corresponding ones. Given the complementary outputs of the circuit, reverse run mode (K = 0), the first carrier is 15 with the corresponding output signals in the carrier pulse Fdc (Fig. 12B) through the carrier error control logic circuit (Fig. 23) and in the carrier error correction logic circuit 142 (Fig. 26) locked. This correction logic circuit 142 (Fig. 26) can be used. happens because the carriers are not in the reverse The output signals of the X _A and Z _ß inverters 373 go upward running until the second carrier and 374 are on the inputs of a 2-input pulse to channel A has caused that Signal 20 of extension gate 383 is given. Correspondingly, X _A or Y _A becomes 0, whereby the first pulse of the X _c and A ^ inverters 376 and 377 on the A-carrier D is blocked. fermented of a second extension gate 384, the Y _A -

A circuit for the carrier return control logic and Y _ß inverters 378 and 379 to the inputs of a circuit 141 is shown in FIG. This circuit is used by the third expansion gate 386 and the Y _c - and Y ₀ - to clock back the signals F ' _A , F' _B , F ' _c and F' _o , 25 inverters 381 and 382 to the inputs of a fourth which have zero crossings at G. ; the resulting expansion gate 387 is switched. The outputs - the counterclocked pulses are used to fade in four gates 383, 384, 386 and 387 are on the Einder pulses / _c . In the circuit according to FIG. 24 are connected to a NAND gate 388, while there are four similar logic circuits. In the fol- output of this NAND gate 388 via an inverter, only the F '^ - logic circuit is described, 30 389 is led to the X + Y output. If one of the signals X or Y becomes 1 (ie the photocell components are provided with the same reference numerals), the signal X + Y will be closed. In the circuit of Fig. 24, the signal becomes zero.

F ' _A to the P _fc input of a / -X binary element 366. The signals X and Y are still coupled to what is connected as a / - / C flip-flop. 35 uses to generate a signal M that is in the carrier. This signal is reversed via an inverter 367 error correction logic circuit 142, the direction of _{movement of the carrier motors coupled to the P r} input of a / -K flip-flop 366. In this regard, pelt. The clock input signals of the flip-flop 366, the signals X _A and X _B on two inputs of one are the clock pulses C given by the clock generator 132 of the fifth expansion gate 391, the output of which (FIG. 31), which come via an inverter 368. 40 output to the P ^ input of a / -Ä binary element The flip-flop 366 is normally located in 392, which is in a switching state during normal operation in which the main output is switched as an ÄS flip-flop ( that is, there are no signals equal to 0, since the signal F- ' _{A is} coupled to it - reversals exist). The signal X ₀ is pelt. If the signal F- _{A is} equal to 0, which corresponds to the switching pulse F- _A via a sixth expansion gate 393 at the Pj position, an input is given. The Af _{c input is given to the P r} input with a single positive input signal. The flip-flop 366 does not switch the one whose output is led to the Py input, however, as long as the output of a seventh expansion gate 394 is connected. until a clock pulse C is received. The other input signal of the seventh gate 394 corresponds to the time reference of the main output signal which is formed by a signal which is equal to / _c · E _BG . Coincidence of a C-impulse with an F - ^ - impulse. In this connection, the pulse J- _c from the main output signal is applied to an input of slow motion logic circuit 133 (FIG. 32) via an input of a NAND gate 369. The other inverter 396 to an input of a NAND gate 397 output signal of this NAND gate is a / _C pulse, the other input signal of which is the pulse which is sent via a NAND gate 371 from the slow motion E _BÜ from the carrier logic circuit 137 (Fig . 21) is. The logic circuit 133 (Fig. 32) is received. A capacitance 370 is connected to the input of the seventh expansion switch between the output of the NAND gate 397 via an Inverden input and ground, in order to connect the pulse J _c to gate 394 by 2 microseconds. Therefore, the P _r input delay before it is faded in by the clocked pulse signal equal to 1 when all ^ signals are equal to 1 F ' _A is faded in so that the negative zero (ie, all carriers are at an end point) crossings of the F '^ pulses do not coincide. The 60 and when the signal E _BG and the signal J _c to 1 other input of the NAND gate 371 is received. In the other case, the Py signal is equal to 0. Q signal, which is combined and received by the disk servo. Correspondingly, the Y signals are combined. This signal has the binary value 1, given to the P ^ input of the binary element 392 as long as the disks are rotating. In this context, the Y _n signal via the output signal of the NAND gate 369 is then 65 an eighth expansion gate 399 to the P _ft equal to 0, while a / _(: pulse during a decrease, the signals Y _B and Y _a clocked to the two inputs F '^ -. lmpulses is received for each of a ninth extension gate 401 whose AusImpuls F' _a are supplied, two pulses J _C Power input is switched to the P ^, and

47 48

y _c signal on an input of a tenth expansion movement is prevented. Given the 402 movement direction gate. The signal Y _c · E _BÜ is used to reverse the carrier, four NAND gates are provided on the other input of the tenth gate 402, 408, 409, 411 and 412, one of which is input, the output of which is at the P _ft input angekop- gang receives the signal M , which becomes 1 around the pelt. Therefore, the P _ft input is equal to 1.5 to reverse the direction of movement of the carriers. This is when all F signals are equal to 1 (ie, all carrier first NAND gates 408 receive an F _AC signal and a are located at the other end point) and when a Λ '- ,, - signal as input signals; the second gate pulse E _BG and a pulse J _c are present. When 409 receives a signal F _BC and a signal X- _B as an input to the carriers actuating the photocell devices; the third gate 411 receives a signal (ie, the signals Y _A , Y _B , Y _c and Y ₀ are equal to 1), io F _cc and a signal X- _c as inputs, which thus becomes the P ^ signal 1 when the next pulse fourth gate 412 receives a F _oc signal and an X - ₀ -E _B and the pulse J _{c are} received. Hence signal as input signals. The output of the first is switched to the /-.K binary element 392, so that the NAND gate 408 is led to the output F- _AC0 ; its main output M becomes 0. If the output of the second NAND gate is actuated by the associated Z photocells on the carrier, the output F- _{Bco is} led. The output of the third binary element 392 is switched accordingly, whereby gate 411 is led to the output F- _Cco ; which the M output signal becomes 1 when the next output of the fourth NAND gate 412 is received at the pulses E _BG and J _c . As _indicated by output F-DC0. Therefore, as can be seen from the above, the carrier is advanced to the outside until the corresponding switching of the binary element 392 is generated by the Im- 20 photocell signals. A puls / _{c is} clocked with it. The reason for this is that the further outward movement of the associated carrier resulting pulse M with the clock pulse C is prevented.

is clocked. The output pulses of the carrier error correction binary element 392 are further switched by a logic circuit 142 to the motor drive pulse N , which gives the reverse run ¹ - 25 stronger 129, which supplies corresponding pulses in logic circuit 138 (FIG. 22) and on supply the clock to drive the stepper motors. The input of element 392 is given. This in-motor drive amplifier can unpulse a circuit. N is a 20 microsecond pulse, which is spoken as it is generated above in connection with the display when the arrangement of the reverse drive of the clock motor has been described. Preferential operation in the forward mode or from the forward mode is in the motor drive amplifier a non-drift mode changes to the reverse mode. Provided means for minimizing the over-The main output signal of the binary element 392 control of each step is provided so that it is given to the output M, while the setting time is minimized. Such a complementary output signal can be given to the output M device in the form of a clock circuit. A circuit implementation for the carrier error of the motor provides pulses to the acceleration correction logic circuit is shown in FIG. This reverses the motor for the period of time, which circuit is used to switch the direction of movement is required to reduce the motor speed in the time the motors (ie the inward or outward movement point to 0 when the motor is moving on the discs) and to Correction of error 40 step completed.

learn which in the switching of the carrier to- A circuit design for the synchronous separation

can kick. Assuming that the carrier circle 121 is shown in Figs. 27A and 27B,

Χ move inward (ie M = 0), the signal becomes where Fig. 27A is the upper half and Fig. 27B

Ι ;! ^{1 represents} F _AC from carrier return control logic circuit (Fig. 24) to the lower half of the circle. The synchronous

j an input of a first NAND gate 403, a 45 separating circuit is used to generate S ^, F and T

\ SignalM-from carrier reversal logic circuitl43 (Fig. 25) (Fig. 12A) from the composite reference

j to the second input of this gate and the Si sync signal. The signals generated in this way become the

gnal Y- ^ from carrier reversal logic circuit 143 (Fig. 25) Control of the time reference of the various opera-

given to the third input of this gate, where functions of the electronic circuit 118 are used. The

the output of this NAND gate to the output 50 incoming composite sync signal, the

F- _AC , is coupled. Therefore, for each pulse from a suitable source, such as a

F _AC a pulse is delivered at the output F- _ACI , except for the station synchronous generator, is delivered via

when the Γ ^ signal becomes 1 (ie, the carrier A is given a coupling capacitance 413 and through a

is found at its one end point). Therefore, diode 414 is rectified. Then it is blocked on one of the second pulse F _AC. Correspondingly, 55 input of a NAND gate 416 are given, which

! the pulse F _EC , the pulse M- and the pulse Y- _B the first sawtooth of the vertical sync pulse

! coupled to a second NAND gate 404, which gates, which is equal to the signal S _R (servo reference

ί output is led to output F- _BC ; the impulse). The signal for keying the NAND gate

pulse F _cc , the pulse M- and the pulse Y- _B are 416 generated by three monostable circuits 417, 418 and to the inputs of a third NAND gate 406 as well as an integration and clamping circuit 420

couples, the output of which is generated at the output F- _CCI. This signal has a duration of about

] leads is; the pulse F _DC , the pulse M- and the Im- 17 microseconds. In particular, the clamped

S puls Y-ß are applied to the inputs of a fourth Nand- composite sync signal via three inverters

} Gate 407 coupled, the output of which is led to the output 421, 422 and 423 on the integration and clamping S output F ₀ Ci . The carriers are coupled once for 65 circuit 420, which by a capacitance

. | each pulse F _AC , F _BC , F _cc and F _ln: proceeding inwards, one at a voltage source

switched until the associated X signal becomes 1, resistor 426 and one the capacitance to one

Γ at which time a further inward voltage source coupling diode 427 is formed.

209637/356

49 50

The input signal is above the capacity. 45 microseconds duration, which is used to block

The line sync pulse and the compensation pulses alternating compensation and vertical sawtooth pulses

is only used due to its short duration. The output signal of the first mono

a low voltage across the capacitance 424, which is stable circuit 438 via an inverter 443

is not sufficient to'die clamping voltage of the diode 5 and a differentiation circuit 444 on the input

427 to overcome. Given the first part of the vertical of the second monostable circle 439,

impulses lasts long enough to load the capac- 'rather from two NAND gates and one capacitance

to charge high enough so that it stands, which triggers this circle. the

Clamping voltage is overcome. As a result, the second monostable circuit 439 delivers a train of pulses

via a differentiation circuit 428 a trigger io with pulses of 5 microseconds duration, which

pulse generated for the first monostable circuit 417. form the line synchronization signal S _Y. This signal

The first monostable circuit 417 contains two NAND- is given to the NAND-gate 4.37. Since that

Gate and a capacitance and provides a pulse line sync signal S _Y and the signal L _R only

of 5 microseconds in duration. coincide for odd fields (Fig. 12A),

The output signal of the first monostable 15 is generated only for odd fields, an output circuit 417 via an inverter 430 and a signal is generated. The output signal of the NAND gate differentiation circuit 429, a trigger pulse for the 437, is passed through an inverter 446 to the output F of the second monostable circuit 418, which is made up of two.

Nand gates and a capacitance. The pulse T is a positive RZ pulse, the second monostable circuit 418 provides an output »o at the end of the last line sync pulse at the pulse of 600 microseconds duration, which starts during the equalization and vertical syn-generation of pulses through the rest of the saw-chronograph signal lasts and before the start of the tooth vertical pulse of 100, so that such a first line sync pulse ends. In order to generate additional trigger pulses not on the subsequent leading edge of the pulse T, the line monostable circle will arrive. The output signal of the synchronous pulse S _Y via a pair of inverters 447 second monostable circuit 418 is given via a and 448 Fig is formed from two Nand multivibrators. This multivibrator is gates and consists of a pair of capacitances, of transistors with associated resistors and whereby this circuit 419 is triggered by the leading edge of the 30 capacitances and a pulse consisting of three inverters. This monostable circuit built the self-starting circuit 451. The swing 419 delivers an L-pulse with a duration of radkreis 449 is pre-triggered by the incoming line-17 microseconds, which is greater than a synchronous signal S _Y. If one or less than two sawtooth-shaped vertical pulses were to fail several line synchronizing signals, they would oscillate. This L-pulse is fed to the NAND gate 416 35 of the oscillating wheel circuit 449 at its natural frequency, whereby the first sawtooth vertical pulse which is 5% below the normal horizontal lines is sampled, which is after inversion by frequency.

an inverter 432 to the heat reference pulse S _R

(see Fig. 12A). is via a pair of inverters 452 and 453, one

The output signal of the monostable circuit 418 40 differentiation circuit 454 and a third inverter is also given via a differentiation circuit 433 456 to the clock input of a binary divider 436 in order to give a monostable circuit 434, which triggers ten as a wave counter (ripple 47 microseconds, which from two through counter) switched / -X binary elements NAND gates and parallel capacitances. This contains. In this counter 436 a switch 457 pulse of 47 microsecond duration is provided as L ' , which indicates the use of the arrangement and has a duration which is equal to one in connection with the SECAM system (625 line period of two sawtooth-shaped vertical pulses synchronous pulses) or with the NTSC system. The two signals L and L- form reset (525 line sync pulses). The sound pulse for a binary divider 436 (FIG. 27B), which selects L 'as the reset pulse for the NTSC-cher, which is explained in more detail below. The 50 system and the reset pulse L for the SECAM-F pulse is a field identification pulse (ie, system, this measure for the difference it identifies odd and even fields). between the number of line and balancing-this pulse is required by blanking the line-pulses in the two systems. Synchronous pulse, which coincides with the first sawtooth The reset pulse L or L ' is generated via a vertical pulse, 55 inverters 458 on the / inputs of the binary elements including a NAND gate 437 and the so-called in counter 436 and a second inverter 459 L-pulse is used as a blanking pulse. Those given on the / ", inputs.

Line sync pulses S _Y are mono- The counter 436 counts the same number of

stable circles 438 and 439 are generated, the to- line sync pulses for odd and even

composite sync signal as trigger signal for 60 fields: therefore the circle is designed so that the

the first monostable circuit 438 is used. Counter 436 counts exactly 258 line sync pulses,

In this context, this is combined when switch 457 is in its NTSC position

set synchronizing signal is at the output of the inverter; if the switch is in its SECAM-

421 via a second inverter 441 and a Dif position, 309 line sync pulses are generated

Ferentiationskreis 442 counts on the first monostable 65. To meet these requirements,

Circle 438 is given, which consists of two NAND gates, the pulse L 'is given to the counter 436 to this

and a connection capacity. This circle 438 , which is monostable after the second sawtooth-shaped vertical pulse, supplies a pulse to be reset for NTSC. Furthermore, the

51 52

Pulse L is given to the counter 436, in order to reset it. After the first sawtooth-shaped vertical pulse reference pulse S _K , the incoming servo is again reset by the transistor for SECAM. When the last line circuit 469 is inverted and counted for a voltage-dependent synchronous pulse by the counter 436, the delay circuit 478 is given, which consists of an output signal via an inverter 461 and two differentiation circuit 462 coupled to a monostable circuit on a NAND transistor , whereby a collector span gate flip-flop 463 is given, whereby its voltage changes with the slowly changing equal error switching state and the leading edge of the voltage generated by the horizontal synchronous time base Kor pulse T at its output changes rectification circuit. The DC voltage input (Fig. 12 A). ίο signal from the horizontal synchronous time base correction-In addition to generating the leading edge of the. circle is buffered by an emitter follower 479 and a pulse T, the differentiated output signal in the emitter circuit operated transistor circuit 481 of the counter 436 via an inverter 464 to the. The output signal of the _{transistor circuit 481 operated in emitter switch P fc} inputs of a chain of binary elements feeds a signal which forms a second counter 466. 15 differential amplifier 482, the output signal of which is furthermore this differentiated output signal is buffered by the emitter follower 483 and applied as a KoI via a second inverter 467 to the K inputs lektorpdtential for the monostable circuit 478. The counter 466 counts twelve when it is turned. The one-shot circuit 478 with variable switch 457 is in its NTSC position, and delay delivers pulses with a pulse width of ten when the switch is in its SECAM position - 20 in the range of 0.5 to 8 microseconds.
is located. The output signal of the monostable circuit 478 given to the second counter 467 clock input signal is generated by blanking the sync signal, which is composed of an inverter 484 to a NAND gate, starting with '486, the other input of which is the record of the first vertical sawtooth pulse . The opening command _{signal P 4} (P ₄ = 0 during playback) via the output signal is received by the monostable circuit 25 from an inverter 487. The output signal of the 418 with a switching time of 600 microseconds (FIG. 27 A) Nand gate 486 is generated via the emitter follower 477 and applied to a NAND gate 468. This is applied to the output R ₀ .

Sync signal is received by inverter 422. A circuit for the slow motion converter is shown in FIG. 29. The output of NAND gate 468 is shown in FIG. This circuit generates the signal the clock input of the second counter 466 (Fig. 27B) 30 Z ₀ , which enables the arrangement to be given. The counting continues until the end of the decelerations from normal speed over the same period, the counter 466 supplying an output signal which can reproduce the still images at every slow-motion speed up to the point in time. The slow motion nand gate flip-flop 463 resets, whereby the control signal A- _s from the field alternating logic circuit 156 is generated 35 on the trailing edge of the pulse T (FIG. 12A) via an integrator 488 and an inverter. 489 to the P input of a first / -K binary circuit 122, which can be used as a servo reference delay element 491, which is connected as a / -K flip-flop, is shown in FIG. and set to P _k -E \ n via a further inverter 492. Given the purpose of the servo reference delay transition of the flip-flop. The pre-pulse G from the circle 122 is to delay the phase of the disk at the clock generator 132 (FIG. 31) to the clock mark and given the first flip-flop 491 during playback. To let this flip rush. The resulting time advance of the flop delays the zero crossings A _s when the reproduced signal compensates for signal delays occurring simultaneously with the pre-pulse G, so that Avoid the 45 shown. As shown in Fig. 14, the flip-flop video signal does not switch the same timing reference to the reference 491 its output signal until G becomes 0 when it has synchronous signal as the video input signal. the pre-pulse G at a zero crossing A _s am

To delay the servo reference pulse S ₁ . Clock input is available.

when reaching recording, this pulse is taken from the complementary output of the first

Synchronous separation circuit (F i g. 27) received and over 5 ° flip-flops 491 is through a differentiation circuit

a differentiation circuit 470 and two inverting 493 differentiated. The differentiated signal S ₁ becomes

Amplifier 469 and 471 to a shortened delay on the P input of a second JK binary

line 472, which is given via a super-element 494, which is configured as an ftS flip-flop.

input delay and a reflected delay is tet. This second flip-flop 494 is through each

of a total of 15 microseconds. The reflective 55 G-pulse provided if it was previously triggered by the signal S ₁

tated pulse, which is negative, triggers one of the first flip-flop 491 was reset. the

Diode transistor gate circuit 473. The delay pulse G from clock generator 132 (Fig. 31) is

Line 472 is delayed approximately 2 volts above ground, for example by 7 microseconds

hold to ensure that gate circuit 473 has ambiguous outputs from the second flip-flop

is not triggered by noise. Avoid the exit 60 494. In this regard, will

signal of the diode transistor gate circuit 473 is the pre-pulse G via a differentiation circuit 496,

inverted by a transistor circuit 474 and to a buffer circuit 497, an inverter 498 and a

given an input of a NAND gate 476, second differentiation circuit 499 on the P ^ input

The other input signal is given the recording signal P _{4 of} the second flip-flop 494.

(P ₄ = 1 when recording) from control logic circuit 428 65 The main output signal Z ₁ (Fig. 14) of the second

(Fig. 19). The output signal is sent via a flip-flop 494 to the clock input of a third

Emitter follower given to the output R _d, given / - / f binary element 501, which as

the signal R _D controls the disk servo. KS flip-flop is connected and as parts with a

53 .. 54

Divider ratio 2: 1 is effective. In this combined input of a NAND gate 509 given, the appendix of which the third flip-flop 501 changes its switch input the signal F _F - F _R from the inverter 503 state for each negative-going zero crossing. The output signal of the NAND gate 509 output of the main output signal Z _{1 of} the second flip-flop is passed through an inverter 510 to the output W _s flops 494. The complementary output signal of FIG. Therefore W is blocked (W _s becomes 0), the third flip-flop 501 is sent to the output Z ₀ if either the fast forward key 510 or the press. Fast reverse button 511 is pressed because F _F

The zero crossings of the output signal Z are ₀ or F _R becomes 0. If W becomes 1, the time is therefore delayed with respect to the leading edge of the pulse G lupen logic circuit 133 by the signal Z ₀ , that is 7 microseconds. If the input rate io dem is controlled by the signal B ₀ , so that the signal of the slow motion signal doubles the field rate, then B _{0 in turn generates a signal Z 0} by the fast search logic circuit of the slow motion converter, which is determined in signal T _s supplied in 131. . its rate is equal to that of D ₀ (i.e. normal movement- In every operating mode, except in fast-

supply). search mode, the signal T _s corresponds to the signal Γ,

A circuit which can be used as a quick search logic circuit 131 is shown in FIGS. 30A and 30B. gen will. The signal T is, as described above, and this circuit controls the operation of the arrangement shown in FIG. 12A, during the vertical inter-rapid search mode and generates an inner clock interval equal to 1. As FIG. 30A shows, the signal T signal, which has about four and a half times the rate of the normal from the synchronous isolation circuit 121 over a pair of Inmalimpulses T , whereby the arrangement advances about 20 vertcrn 511 and 512 on an input of a first four and a half times faster than normal. Nand-Gatters 513 given. As in the following

Specifically, the commands for the arrangement will be explained in, the other input signal of the quick search mode is generated in the lower part of the circuit of the first NAND gate except in the quick search mode (Fig. 30B). In quick search mode, the value is equal to 1. The output signal of the first Nand gate arrangement is brought into purely electronic mode by suitable devices (not shown 513 is fed to an input of a second Nand gate), since gate 514 gives its other input signal no information comes from the panes. Especially except in the quick search mode it is equal to 1. The output both in the recording mode and in the high-speed signal of the second Nand gate 514 is sent via search mode the output signal of the recording buffer 516 to the expansion node circuit 123 to the input of the playback circuit 30 of a Nand circuit 517, which is used for the 147 given, but in the fast search mode, the output signal T _s acts as an additional buffer. is not given on the heads. Since the field corresponds to the signal T _s , apart from the changeover logic circuit 156 (FIG. 34) is _{actuated by the control of the fast search or the fast reverse signal (P 4} = 0), it is activated by a running mode, the Signal T. A blocking gate 518 is provided at the output of the signal F _F · F _R gate from the fast search logic circuit 134, which gate switches when it switches over. The command signal F _F · F _R from the field circuit from playback to recording the Si changeover logic circuit 156 is generated in that the signal T _s blocks for a short time after P ₄ to 1 signals F _R and F _F from the search frame feed -Rule- will.

circle 159 (Fig. 17) to the inputs of a Nand fast forward and fast reverse

Gates 502 are given, the output signal 40 operation, the signal T is replaced by the pulse from an inverter 503 to the output F _F ■ F _R 600 microsecond duration, which is reproduced. This signal is equal to 1, except when the recovery rate of about 3.7 milliseconds or the fast forward button 510 or the fast reverse four and a half times the repetition rate of the pulse T , buttonSll are pressed. In this case the signal is possessed. However, certain conditions must equal 0. The signal P _{2 s} will be met by coupling the 45 to ensure accurate operation of the incremental signal F _F · F _R from the output of the inverter 305 in systems, which controls _{the r s pulses} . The input of a NAND gate 504 is generated, it is to be noted that the carrier and step of _{other inputs receive the signal P 2} via an inverter switching motor arrangement having an inherent inertia 506. Since P ₂ in the forward mode and in the backward mode, which is the maximum number of increments forward mode, is 0, the output signal 50 is limited, which without errors in a given time unit of the NAND gate 504 equals 1, except when the connections can be carried out. This requires that the order operate in reverse operation and not in switching from normal operation to Schnellaufbe quick search operation. This output signal drove or from high-speed operation to normal operation is given to a second NAND gate 506, during the pulse cycle T its other input signal must be quantized by a third 55 that the time interval between the Nor-Nand gate 507 is obtained. The input signals malimpuls T and the quick search pulse P less of the third NAND gate 507 are the quick forward than the interval that is an error in the progression signal F ₁ . and would produce the signal F- _R + F- _{F from.} Therefore, in the illustrated NAND gate 502. The output signal from the second circuit switching from normal pulses T NAND gate 506 is given via an inverter 508 to 60 to fast search pulses T or vice versa at output P ₂₅ . Therefore, P _{2S is} in fast-setting that it takes place in a time interval, the forward search mode is equal to 1, in the forward mode equal to or greater than the interval between two 1, in the reverse quick search mode is 0 and fast search pulses T. Furthermore, the Umin reverse operation should not be equal to 0 during the presence of a

The slow motion signal W will take place by the fast 65 normal pulse T in order to lock the shape of the Imsuch logic circuit when the arrangement is in the pulses T and the simultaneous on-fast search operation is working. In particular, the occurrence of a normal pulse T and a high-speed signal W from the control logic circuit 128 (FIG. 19) on a search pulse T is to be avoided.

When switching from normal operation to fast search operation, the normal pulse T is sent from the inverter 512 (Fig. 30A) via a differentiation circuit 519 to a first monostable circuit 521, which contains two NAND gates and a capacitance and a pulse of 100 on the trailing edge of the pulse T Microsecond duration generated. This output pulse is transmitted via a differentiation circuit 522 and a second monostable circuit 533

search pulses T corresponds. A negative output pulse occurring at the output of the output NAND gate 537 is given via an inverter 539 to a differentiation circuit 541, the negative part of the differentiated pulse forming a monostable circuit 542, which is composed of two NAND gates and a capacitance, triggers. At the output of the monostable circuit 542, negative outputs occur for each quick search trigger pulse C, since the output gate 537 of the multivibrator 528 is now blocked by the output signal of the flip-flop 527. The signal α continues

given which two Nan'd gates and a Kapa- 10 pulses of about 600 microseconds duration

containing the second monostable circuit 523. The quick search trigger pulse occurs about all

due to the trailing edge of the first pulse with 100 3.7 milliseconds, whereby this rate is 4.5 times greater.

Microsecurid duration is triggered. The outlier than the rate of normal pulses Γ is. the

The output signal of the second monostable circuit 523 is the output pulses of the monostable circuit are the

also a pulse of 100 microseconds duration, 15 quick search pulses T _s , which are transmitted via the Nand gate

which with respect to the trailing edge of the pulse T ter 514, the buffer 516 and the NAND gate buffer

is delayed by 100 microseconds. This output 517 can be given to output T _s . The producers

The output pulse is sent to a first NAND gate 524. The fast search pulse T _s continues until the

give whose other input a signal α of signal α of the input NAND gate 524 its value

an inverter 525. As in 20, the signal α changes from 0 to 1 (i.e. from quick search to normal

described below, to 0, if the fast, time or slow motion operation).

search button is pressed and the photocell device is For switching from quick search to normal

gen X _AA and Y _{VY are} not energized. Therefore, when painting is done, the circle is designed in such a way that this

Output signal of the first NAND gate 524 for 100 circuit neither in the presence of a pulse microseconds to 0 after the first pulse J 25 T _s nor in the presence of a normal pulse Γ

occurs after the signal α has become zero. The- can take place. The signal α is via the inverter

This output signal is sent to the fast input of a 525 to the reset input of the multivibrator 527

first flip-flop circuit 526 given which a given, which resets this flip-flop and

Pair of cross-connected NAND gates to re-trigger the quick search trigger pulse

holds. The output of this first flip-flop generator 528 is prevented. On the monostable

Circle 526, which is given to the NAND gate 513 len circle 542 cannot receive further trigger pulses, therefore changes its value from 1 to 0 and
blocks the normal pulse T.

The pulse lasting 100 microseconds on

Output of the first NAND gate 524 will continue 35 ^au f ^e 'n NAND gate 543 and an input Nandhin to the control input of a second flip-flop gate 544 given for a flip-flop circuit 546th The signal α switches the input gate 544 through, is composed of two crossed NAND gates. This triggers the monostable circuit 541, controls the output signal of this flip-flop circuit 527, which contains a pair of NAND gates in a capacitance to excite a freely oscillating multivibrator 40. The output of this monostable 528 which generates the T high-speed search pulses. The circle 546 is a negative pulse of 8 milliseconds, freely oscillating multivibrator 528 contains three seconds duration, which is used to delay the on-Nand gate 529, 531 and 532, a capacitance 533 occurs for the normal pulse T for 8 milliseconds and a frequency control resistor 534. The multivibrator used to block the quick search pulses vibrator 528 is a modified monostable circuit, 45 will. When the one-shot 544 retriggers its own input in its own. When the rest position returns, the NAND gate 543 lets the monostable output signal through at the output of the signal α, which resets the monostable circuit NAND gate 532, which a negative going 546 resets. The signal α is given an inverse pulse of about 3.7 milliseconds duration, its ter 547 to a NAND gate 548. After the quiescent value assumes, so it causes a Rücktrigge- 50 occurrence of the next gate signal through the NAND genus len from monostabirung the multivibrator means transfer circuit 523, the signal α to the rear Stellter 529. However, should the capacity of the RC input of the flip- Flop circuit 526 given which time part 533, 534 discharged before the triggering of the gate 513 switches through in order to let the pulse T input have an effect on the NAND gate 531. Since the one-shot circuit 523 can run 100 times. The capacitance 533 discharges 55 microseconds after a normal pulse T an inner diode of the NAND gate 531 generates between the pulse, it prevents the occurrence of a nor-extension node and the input and causes it
after a short time delay, a new triggering of the monostable circuit 528. This leads to a positive pulse of short duration on the multi-60
vibrator output of the NAND gate 532 occurs, which via a control diode 536 to an input
of a NAND gate 537, which is given by the
Output of the second flip-flop 527 is turned on. This activation is used by the four input signals. It is capacitance 538 so delayed that the first output is the signals F _Ri F _t -, X _YA and Y _AA . The Siimpuls after switching only after a time on signals F ,. and F ^ are provided by the search frame advance which is approximately the time interval between fast loop 159 (FIG. 17). The signal F ,. is

209637/356

malimpulses T at a Γ time, which would lead to a gating of a partial pulse T with resulting errors in switching.

The signal α, which is generated regardless of whether the system is working in quick search mode or not, is equal to 1 in normal mode and equal to 0 in quick search mode. As FIG. 30 B shows, are used to generate the signal λ

57 58

equals 0 when the fast forward button is pressed. and to avoid transition delays in the logical EI-

Accordingly, the signal F _{K is} equal to 0 when the ments allow.

Fast rewind button is pressed. The carriers can. The system clock pulse C is not derived from the trailing edge at fast search incremental speed and from the pulse T _s. This impulse C is used for the switching impulses, which take effect and are used in the vicinity of these end stops, in alternation with their end stop switches. can be used on the one hand to switch from head to head and from carrier stop switch as a normal stepping speed wedge to carrier. Specifically, the signal is slowed down. The pre-warning photocells X _AA or Υ _ΛΛ T- _s from the first inverter 558 via a second In are always actuated when the carrier verter 564 and a differentiation circuit 566 on six tracks approximated to the photocells io a monostable circuit 567 given, which one have. For the advance warning on the outer limit containing a pair of NAND gates and a capacitance, X _{AA is} equal to 1, while for the pre-warning on the inner limit Y _{AA is} equal to 1 since the input signal is the differentiated signal T _s. If X _AA or the monostable circuit 567 delivers a pulse of Y _AA equal to 1 and the system is in fast 30 microsecond duration on the trailing edge of the search mode, then for the period of time in which there are i ₅ pulses T ₅ . This pulse of 20 microseconds the carrier is in the pre-warning zone, a duration is called via an inverter 568 to switch off to normal progression speed C- and via two inverters 569 and 571 to the. Therefore, the signal α is given to outputs C only.

equals 0 if X _AA and Y _AA as well as F ₁ , or F _R equals The pulse B ₀ is a version divided by two

0 are. The Boole equation for λ is: 20 of the pre-clock pulse G and is given by the half

■ _Λ - / χ _ | _ γ \ _ | _ f_ ,. / r_ image identification pulse F _s from the quick search Lo-

gikkreis 131 determined in the phase. The in-phase

The signals X _AA and Y _AA are brought about by the corresponding signals B ₀ and F _s that currently ting inverters 549 and 551 are given to the inputs of a field through the heads / 1 and C and odd NAND gates 552. The output of the 25 fields recorded by the heads B and D Nand gate 552 will be via an inverter 553 on. To form the signal B ₀ , the pre-input of a second NAND gate 554 is counter-pulse G from inverter 563 to the clock input of a ben. The other input signal of this NAND gate / -tf binary element 572 is given, the JK flip 554 is the signal F- _R + F- ,. is switched at the output of the nand flop. Via a pair of inverters 573 of gate 502, the output of NAND 30 and 574 being the signal F _s from the quick search logic gate 554 being the signal α. circle 138 to the P ^ input of the flip-flop 572

The field identification pulses F are given at. Therefore, the signal F _s sets the flip-flop 572

Quick search mode blocked because the quick search is before. The trailing edge of the prepulse G causes

speed is not directly related to the fact that the flip-flop is set every time

the incoming sync signal. The pulse F _s after the previous G pulse applies

F = F _s , if the arrangement was not in quick search equal to 1, and is reset if the im-

operation works. However, F _s is equal to zero if the _pu ls F _{s was} equal to 0 after the last prepulse G.

Quick search arrangement works. As the complementary output signal of the flip-flop

The Boole equation therefore applies: is given to the output ß- _G . The main

p , _ ρ. p_ .. p_ 40 output signal is given to output B ₀ . There

^{s h R} ' a signal F _{s is} present for every even field

A NAND gate 556 contains the pulses F vom ist, B ₀ for every even field is 1 and for

Synchronous transistor circuit 121 (Fig. 27) and the Si every odd field equal to 0. One for the time

gnal F _h - ■ F _R from inverter 503. The output signal lupen logic circuit 133 usable circuit is in

of the NAND gate is represented by an inverter 557 in FIG. 32. This circle provides the fundamental

verted, the output signal of which is the signal F _s . mental movement signal D ₀ and the carrier tract

_{A pulse / c} circuit which can be used as a clock generator 132 . The slow motion control signal W _s , which is shown in FIG. This circuit receives the Si from the quick search logic circuit 131 (FIG. 30) received T _s and F _s from the quick search logic circuit 131 , is via an integration circuit 576 and (FIG. 30) and generates three basic principle clocks Inverter 575 to the P ^ input of a JK-Bi pulses, which are given to synchronize the switching närelementes 577, which are used as / - / ^ - flip-flop of the system logic. This clock is switched. The Si pulses applied to the P _ft input are the pre-clock pulse G, the clock pulse C signal W- _s is still on via an inverter 578 and the clock pulse B ₀ (see FIG. 12A). Specifically given the f, input. The clock signal for the is the pulse T _s from the quick search logic circuit 137 55 / -K binary element is the pre-pulse G- from the clock via an inverter 558 and a differentiation generator 132 (FIG. 31). If a change in time circuit 559 is given to a monostable circuit 561, magnifying glass control signal W _{s is} present, then the flip-softener changes two NAND gates and a capacitance ent-flop 577 its switching state until the next lead. Therefore, the one-shot circuit 561 does not provide a pulse G- in order to avoid a change during the output signal on the leading edge of each pulse clock pulse, which can lead to system errors ses T _s . The output pulse is a pulse from could lead.

The main and complementary output signal of the ter 562 to an output G and a two flip-flops 577 are given to an exclusive-OR gate inverter 563 to the output G, which lasts 20 microseconds. Given 579, having a pair of NAND gates, the logic circuits in the system are activated by the 65-581 and 582, whose outputs are reset to a pre-pulse Norr G, which are turned on before the clock gate 583rd The main output pulse C occurs to ensure that the switching signal of the flip-flop 577 will go along with the gears before the system is switched on, signal Z ₀ from the slow-motion converter (FIG. 29) to the

59 60

lower NAND gate 282 given. The complement. In its normal position, the signal K from the tary output signal of the flip-flop 577 is coupled with the reverse logic circuit 138 (FIG. 22) to the off signal B ₀ from the clock generator 132 to the upper gear K- . The signal R 'is given by the half-row NAND gate 581 . Delay logic circuit 158 (FIG. 35) is applied to the

The output signal of the exclusive-or gate, 5 output R '+ B ₀ coupled. The output A _F is

which either grounds depending on the signal W _s. In alternating field mode, the output K 'is

the signal B ₀ or the signal Z ₀ is grounded to the, the output R ' + B ₀ to the signal B ₀ from

P _{/ r} input of a second binary element 594 against clock generator 132 and the output A- _r to a binary

ben, which is also connected as JKF \\ p-flop coupled to närsignal 1.

is. Furthermore, this output signal is applied to the G _r input via a circuit for the field inverter 586. The clock change logic circuit 156. This circuit replaces the pulse for the second flip-flop 584 is that of the slow motion signal A through the signal B ₀ when the clock pulse generator 132 received clock pulse C-. Da- order works in alternating field operation, and the second flip-flop 584 is given a signal B ' by the clock, which is pulsed in alternating field operation, whereby either D ₀ or Z ₀ 15 the signal. B ₀ corresponds and is clocked back in normal operation (this is B ₀ , if W _{s is} equal to 0, equal to 1).

or Z ₀ when W _s is 1). This prevents in the circuit according to Fi g. 34 shows the slow motion that switching transitions cause logical errors - control signal A from control logic circuit 128 (FIG. 19). The main output signal of the second flip is given to an input of a NAND circuit 599 , flop 584 is given to the P, input of a third JK 20 whose other input is the 128 binary elements 587 from the control logic circuit, which is called / - / C flip- Flop (Fig. 19) supplied signal P- _{3 is switched} via an inverter. The complementary output signal 501 is received from input P- ₃ . The output signal of the second flip-flop 584 is applied to the P _ft input 'Nand gate 599 is applied to the output A- _{A of the} third flip-flop 587 . This third ben so that A- _A equals A when P ₃ equals O. The flip-flop is switched by the pre-pulse G-switched on its clock input. The signal B ₀ from the clock generator 132 (FIG. 31) is switched. Therefore, one is made via two inverters 602 and 602. 603 given to an input back-clocking of the signal Z ₀ or B ₀ by the third of a NAND gate 604 , the other one of which is flip-flop as a function of the pre-pulse G, so the output signal is _{the signal P 3.} The output of the that these signals can be used for the head logic. Nand gate 604 is applied to the output A _A , the main output signal of the third flip-flop 587 ₃₀ where the signal A _{A is} equal to B ₀ when P ₃ becomes equal to 1 via an inverter 588 to the output D ₀ (ie, the arrangement works alternately. The complementary output signal of the image operation).

third flip-flops 587 is generated via an inverter 589. The signal B ' is formed in that the

given to the output D- _o . The signal D ₀ ent- signal B ₀ at the output of the inverter 603 to a

speaks to the signal B ₀ when a normal or fast 35 input of a NAND gate 606 is given. the

search operation and the signal Z ₀ at slow motion or other input of this NAND gate receives the signal

Alternating field operation. P ₃ through a pair of inverters 607 and 608. That

The carrier clock pulse / is generated by the output signal of the NAND gate being sent to the output

the signal D ₀ and the signal D- _{G given} via corresponding output B- . Therefore the signal B 'is equal to 1,

corresponding differentiation circuits 591 and 592 to a 40 when P _{3 is} equal to 0, and equal to B ₀ when P _{3 is} equal to i

monostable circuit 593 , which is a (the arrangement works in alternating half-image

Contains pair of nand gates and a capacitance. drove).

Therefore, this monostable circuit 593 provides an im- The signal R used to control the half-line delay pulse of, for example, 100 microseconds duration circuit 149 is thereby g at the beginning and end of each pulse D ₀ . The result is that the signal T _s from the clock generator 132 is sent to the output signal of the monostable circuit 593 with an input of a NAND gate 609 , the clock pulse C from the clock generator 132 is sent to the second input, the signal F _e F _{K given} by NAND gate 594, given its output fast search logic circuit; the third input via a differentiation circuit 596 to a two- receives the signal P ₄ from the control logic circuit 128; given to the tenth monostable circuit 597 . which 50 fourth input is given the signal R '+ B ₀ from a pair of NAND gates and a capacitance image changeover switch 153 (FIG. 33). That endures. This monostable circuit 597 delivers to its output signal of the NAND gate 607 , a pulse of 100 microseconds output Λ is given to the output output. Therefore the signal R is equal to 1, duration. Therefore, for each zero crossing of the Si if either T _{s is} equal to 1 (in the compensation time _{B G} or Z ₀ a period of time determined by the clock pulse C) or if the arrangement in the fast search mode works with a pulse of 100 microseconds (F ,, · F _R = 0). The signal R is equal to 1, formed duration. This pulse is given to the output J- _c via an input when the arrangement is in the recording mode arverter 598. Therefore it is worked (P ₄ = 1). During normal playback, the carrier clock pulse J _{c is} equal to the clock pulse C, signal R with the exception of the equalization period when D _{0 is} equal to B ₀ . If, however, D _{0 is} equal to Z ₀ , then 60 is equal to the signal R ', while it is equal to B ₀ when the pulse J _{c occurs} with the next clock pulse C following the field changeover switch 153 in its half-zero crossing Z ₀ is located
(see Fig. 14). F i g. 35 shows a half-line delay

One as a field-changing switch 154 verwend- logic circle 149 usable circuit. This switchable circuit is shown in FIG. 33 shown. This circuit compares the states of the signals D ₀ and B ₀ , which are required to switch the arrangement in the to determine when a half-line delay alternate field exception mode is used. If the signal B _{0 is} equal to 1, this is a manually operable three-pole double-switch video output signal and should be an even field. is

on the other hand , if the signal B _{G is} equal to 0, the video output signal should be an odd field. In normal recording and D ₀ = B ₀ , even fields are recorded on areas A and C , while odd fields are recorded on areas B and D. In normal playback, D _{0 is} either B ₀ or B- _G . If D _{0 is} equal to B ₀ , the half-line delay is not required. However, if Dq is equal to B- _c , the half-line delay is

is placed on the third and fourth NAND gates 618 and 619; while the complementary output signal L- is applied to the first and second NAND gates 616 and 617. The output signal of the first NAND gate is given to the output E- _AG . Therefore E _{AG has} a logical function, which

E- _AG equal to D ₀ L- B- '

tion required for all video information. io directs. The output signal of the second NAND gate in slow motion playback, however, D _{0 is} equal to Z ₀ . Da- 617 is given to the output E- _BG . Hence

at D ₀ - usually has a longer period than B ₀ . The in F i g. 35, which is an exclusive-or gate, is used to compare the logic states of B ₀ , B- _G , D ₀ and D- _o . The conditions for this comparison are: (1) if D ₀ equals B ₀ or D- _o equals B- _o , the video signal coming from the disc is the correct field required at the output; the half-line delay is blocked; (2) _{if D 0} equals BQ or D- _o equals B ₀ , the video signal coming from the slice is a false field, the half-line delay being required to produce a correct field at the output.

In the circuit shown, the signal D ₀ from the slow motion logic circuit 133 and the signal B ₀ from the clock generator 132 are passed to a NAND gate 612, the output signal of which is passed to a NOR gate 613. The signal D- _o from the slow motion logic

the logical function E _BG reads:

E- _R r. - D-η · L- · B-.

"BG

The starting material of the third NAND gate 618 is fed to the output E- _co whose logical function

E ~ dg ^{= d} ~ g -LB-

reads. The output signal of the fourth NAND gate 619 is given to the output E- _D0 , with the logical function

^e ~ cg = D ₀ -LB-

reads.

F i g. 37 shows a circuit which acts as a chroma inverter logic circuit 152 can be used. This circuit determines whether the chroma inverter circuit 151 to

Circle 133 and the signal B- _o from the clock generator Ϊ32 30 correction of the phase of the chroma information in series are given to a second NAND gate 614 to be switched to the video output signal. As above

. explained, the chroma inverter should turn the phase by 180 ° each time a new field is displayed in reverse operation (K ' = 0) ^{(Cc =} 1); i ^m slow motion operation of the chroma inverter to be switched every time when the half-line delay is effective (R = 1).

In the circuit arrangement according to FIG. 37, the signal C bi jd Wid ii used to switch the chrominverter

the output signal of which is given to the NOR gate 613. The output signal of the NOR gate 613 is the signal R ', its logical function

R '= B ₀ -D ₀ + BoDQ

reads.

F i g. 36 shows a circuit which can be used as head logic circuit 134. This circuit generates the individual head pulses E _AG , E _BG , E _co and 4 ° C _n each time a new field is reproduced in E _D0 (see Fig. 12B). These head pulses are positive reverse operation generated by inputting the signal J _c RZ signals with a binary ratio of 1: 3 from slow motion logic circuit 133 (FIG. 32) via normal recording or playback and an inverter 622 a NAND gate binary ratio of 1: 7 for alternating field 633 is given. The other input signal of the drawing. 45 NAND gates 623 are used to generate the head pulses, signal K ' from field two signals. This is a changeover switch 153 (FIG. 33) which is sent to this input via an inverter 624. The output of the NAND gate 623, which is equal to J _c + K ' , is applied to an input of a second

equal to the signal B ₀ . The signal D ₀ 50 Nand gate 626 is given for slow motion. The other input signal, however, is the same as the signal Z ₀ . With normal recording this NAND gate 626 is for the reverse run

determined as will be described below. At the output of this gate an output signal is generated for each pulse J _c if the signal K '

Like F i g. 36 shows, four NAND gates 616, 55 are equal to 1 (ie, in reverse operation). These 617, 618 and 619 are provided. The signal D- _o from the output pulse of the NAND gate 626 is applied to the slow motion logic circuit 133 and is applied to the second and clock input of a / - / i binary element 627 NAND gates 617 and 619 which are quartered. The signal ben, which is connected as an ÄS flip-flop. Therefore, D ₀ from the slow motion logic circuit 133 changes to the first of the flip-flops 627 for each pulse J _c its switching and. third NAND gates 616 and 618 given. The 60 state, whereby the value of its main output signal B- from the field change logic circuit 156 signal C ₁₁ for each new field from 0 to 1 changed (Fig. 34) to the input of all NAND gates 616,
617, 618 and 619 given. The signal D- _o continues to be applied to the clock input of a JK binary element 621 , which is switched 65 as a KS flip-flop
and acts as a binary divisor (i.e., this element
switches more negative zero crossings from D- <7).
The main output signal L of this flip-flop 621

signal D ₀ from slow motion logic circuit 133 (FIG. 32) and signal B- from field alternation logic circuit 156 (FIG. 34). The signal D ₀ is for normal running

The signal B- is equal to 1 for normal playback and normal playback. However, in the case of alternating field recording, the signal B- ' is equal to G _B.

is changed. Therefore, the chroma inverter becomes for each new field played back in reverse mode switched in its switching state.

When running forward, the signal K ' and therefore always also the signal J _c + K' = 1, the switching of the flip-flop by a second / -K binary element 628 connected as a JK flip-flop

63 64

is controlled. The main output signal of the flip is to the P _fc input of the first flip-flop 634 Flops 628 is via an inverter 629 and an and via an inverter 641 to the P _; -Entrance ge-differentiation circuit 631 to the input of the Nand- give. The signal E _{CK is given} by the reverse logic gate 626 . The Signa / R '+ B ₀ of the semicircle is set to the P _fe input of the third flip-flop is image reversal logic circuit 153 (Fig. 33) on the 5 637 and through an inverter 642 _r on the P input P, -Input of a flip-flop 627 and given via an In-. The signal E- _BG from the head logic circuit 134 verter 632 given to the P _fc input. The clock (Fig. 36) is sent to the P _r input of the second flip pulse for the flip-flop 628 , the key signals C, flops 636 and via an inverter 643 to the P _k which are given via an inverter 633 from the clock generator input . The flip-flops 634, 636, 637 and 132 (Fig. 31) are received. Therefore, changes of the io 638 628 its switching state whenever R 'supplied clock pulses C clocked by the (F ig. 31) by the clock generator 132. Flip-flop. The complementary or B ₀ changes from 0 to 1 or vice versa, the word output signals of these binary elements are clocked accordingly to the outputs E _AC , E _BC , E _cc and tet during the switchover by the clock pulse C. The switching of the flip-flop 627 causes E _DC given, these output signals for switching the first flip-flop, whereby the 15th of the heads are used. The signal E _{00 is changed} at the binary value of C _H , which in turn changes the output of the inverter 639 via a further state of the chroma inverter 151 . Given inverter 644 to the output E _DG, wherein A as Kopfriicksteuer logic circuit 136 verwend- this signal to control the speed of the clockable circuit is in F i g. 38 shown. This switching motor is used.

device, which the head switching signals E _Aa , E _Ba , E _co ao From the above it can be seen that according to and E ₀₀ clocked back with the clock pulse C, the invention contains a method and an arrangement four / -K binary elements switched as / -K binary elements -Flip- for reproducing black-and-white and color remote flops 634, 636, 637 and 638. The signal E- _D0 from the visual signals with every slow motion speed up to head logic circuit 134 (FIG. 36) is switched to the Py-On. . is indicated down to the pictures below. Dargang the fourth flip-flop 638 and an In- »5 beyond, the arrangement in the reverse run verter 637 given to the P _ft input. The signal or E _AK operated at above normal speed from the reverse logic circuit 138 (FIG. 22) can be used.

In addition 13 sheets of drawings

Claims (14)

Claims:. 1. Arrangement for a system for reproducing a television signal in a mode with variable speed, in still pictures or in reverse with a first recording. medium zone on which odd fields "of the television signal are recorded by a first transducer head, with a second recording medium zone on which even fields are recorded by a second transducer head, each of the heads being adapted to have the recorded fields through them opposite the Record are reproduced in a different sequence, and the arrangement ensures that the outgoing reproduced signal has a correct interleaving of the fields, with a first subcircuit responsive to the fields reproduced by the first head and defining each reproduced odd field, with a second Sub-circuit which responds to the fields reproduced by the second head and defines each reproduced even field, and with a third sub-circuit for converting even fields into odd fields or from odd fields into even fields, marked calibrated by a fourth, to the first and second subcircuits (132, 575, 576, 577, 578, 581, 582, 583, 584, 586, 587, 588; 132, 575, 576, 577, 578, 581, 582, 583, 584, 586, 587, 589) responsive subcircuit (132, 158) for exciting a correction signal (R '= 0) in the absence of the normal sequence of odd and even Fields and by coupling the third subcircuit (132, 156, 148, 149) to the fourth subcircuit (132, 158) for receiving the correction signal. 2. Arrangement according to claim 1, characterized in that the fourth subcircuit (132, 158) receives a synchronization signal (F ₈ ) which "defines the desired odd-even grid of the outgoing reproduced signal and an odd-even signal corresponding to the grid (B _G ) supplies, and that the fourth subcircuit compares the odd-even signal with the signals generated by the first and second subcircuit (D ₀ , ZJ ₀ ) and always supplies the correction signal (R '= 0) when the Signals are not matched. 3. Arrangement according to claim 1 and 2, characterized in that the third subcircuit (132, 156, 148, 149) for converting odd fields into even fields or from fade fields into odd fields contains a delay circuit (149) which at Actuation by the correction signal delayed an entire reproduced field with the recording of the vertical blanking period by a time which corresponds to the duration of half a line of the reproduced field. 4. Arrangement according to one of claims 1 to 3, characterized in that the third Teilschaitung (132, 156, 148, 149) for Umforinung of odd fields in even fields or from even fields in odd fields further a locking circle (132) for Receiving the synchronous _{signal (F 5} ) and generating a blocking signal (T _s ) for the duration of the vertical blanking period and a circuit for coupling the blocking signal to the delay circuit, the delay circuit (149) being switched off during the vertical blanking period. ,:, '; ί "'; ■ ■ ■ ii 5. Arrangement according to one of claims 1 to 4, characterized in that four recording medium zones (a, b, c, d) are provided for recording the fields, which rotate about corresponding axes at a speed that corresponds to a rotation of 360 ° each Recording medium zone for each field interval of the television signal is equivalent that each recording medium zone is assigned a transducer head (A, B, C, D) , that the odd fields on the recording medium zones (a, c) and the even fields on the recording medium zones (b, d ) and the even fields are recorded and that the first sub-circuit (132, 575, 576, 577, 578, 581, 582, 583, 584, 586, 587, 588) on fields reproduced from the recording medium zones (α, c) and the second sub-circuit (132, 575, 576, 577, 578, 581, 582, 583, 584, 586, 587, 589) is responsive to fields reproduced from the recording medium zones (b, d). 6 .. Arrangement for a system for reproducing a television signal with variable speed effects with two recording media on which odd and even fields of the television signal are recorded by a plurality of transducer heads, the transducer heads being designed so that one of the recorded fields is reproduced a predetermined number of times wherein the arrangement ensures that the outgoing reproduced signal has a correct interlocking of the fields, according to claim 1, characterized by a first sub-circuit (123, 125, 126, 121, 131, 132, 136, 130) for receiving the television signal, identify alternating fields of the television signal as odd and even fields and to define the fields as odd and even fields during recording, so that each of the recorded odd fields is displayed as an odd field and each of the recorded even fields is displayed as an even H Albbild is determined, and by a coupled to the first subcircuit and during playback to the transducer heads second subcircuit (133, 158, 153, 156, 148, 149) for changing the line raster of each reproduced field, so that then always the field of the opposite Type is generated in the outgoing reproduced television signal when the odd-even designation of the reproduced field differs from the odd-even designation of the existing field of the television signal. 7. Arrangement according to claim 6, wherein the television signal contains a composite video sync signal, characterized in that the first subcircuit for receiving the television signal has a fourth circuit (121, 132) for receiving the "composite video sync Chronsignals and for generating a between a state for odd fields and another state for even fields changing binary signal (B _G ) and a third circle (132, 136, 130, 124) for receiving the binary signal, which causes that by the Binary signal fixed odd fields are recorded by first predetermined heads (A, C) and even fields by second predetermined heads (B, D) , it being determined that in the reproducing mode, odd fields are reproduced by the first heads and even fields are reproduced by the second heads . 8. Arrangement according to claim 6 and / or 7, characterized in that the second sub-circuit for changing the line raster of the reproduced fields has a fifth circle (132, 156, 148, 149) which covers an entire reproduced field with the exception of the. Vertical blanking period delayed by a time which is equal to the duration of half a line of the reproduced field, namely whenever its determination differs from the identification by the first subcircuit receiving the television signal. 9. Arrangement according to one of claims 6 to 8, characterized by a sixth circuit (157, 133, 134) effective in playback mode for generating a head selection signal (D ₀ , E) which causes a recorded field to be played back zero times by each head, the head operation sequence being either the same as for recording or reversed with respect to it, and by a seventh circle (131, 132, 133, 158, 153, 156, 148, 149, 136, 130) for receiving the binary signal (B _G ) and the head selection signal (D ₀ , E) such as to operate the fifth half-line delay circuit (149) when the binary signal identifies an odd field while the head selection signal activates one of the second heads, and when the binary signal identifies an even field while the head selection signal puts one of the first heads into operation. 10. Arrangement according to one of claims 6 to 9, characterized in that the fourth circuit for receiving the composite video synchronization signal and for generating the binary signal (B ₀ ) comprises the following circles: an eighth circuit (121, 132) for receiving the composite video synchronization signal and for generating a continuous horizontal line sync signal (Sy) which coincides in time with the horizontal sync pulses of the composite video sync signal and extends at the same frequency over the vertical sync periods of the composite video sync signal, a ninth circle (121) for receiving the composite video sync signal and the continuous horizontal line sync signal a predetermined vertical sawtooth pulse (S _K ) in each vertical sync part of the composite video sync signal, for counting the pulses of the continuous line sync signal and for generating a signal (T ₈ ) m With a vertical interval pulse that begins between the last horizontal sync pulse and the first equalization pulse of each vertical sync part of the composite video sync signal and ends between the first horizontal sync pulse and the last equalization pulse of the vertical sync part of the composite video sync signal, a tenth circle (132) for generating a vertical sync signal (G) with a short continuous pulse which coincides with the leading edge of each vertical interval pulse, and an eleventh circle (132) for receiving the head-time signal and for generating the binary signal in the form of the short-time pulse signal divided by two, so that the binary signal at every short-term impulse changes from its one to its other state. 11. Arrangement according to one of claims 6 to 10, characterized in that the ninth circuit (121) for receiving the composite video synchronization signal and for generating the binary signal contains the following circles: a twelfth circuit (121) for receiving the composite video synchronization signal and the continuous horizontal wedge synchronization signal and for generating an identification signal pulse (F) for odd fields when one of the continuous horizontal line synchronizing pulses laterally coincides with the first sawtooth pulse of a vertical synchronizing part of the composite video synchronizing signal, and a thirteenth, part of the circle (132) for recording the circle (132) forming part of the circle (132) receiving the identification signal odd fields and for phase adjustment of the binary signal (Bq) in such a way that it assumes a predetermined state during the odd fields and the other predetermined state during even fields. 12. Arrangement according to one of claims 6 to 11, characterized in that the seventh circle (131, 132, 133, 158, 153, 156, 148, 149, 136, 130) is designed to receive the binary signal (B ₀ ) that it generates a main half-line delay signal (R ') which changes between a first state corresponding to the actuation of the half-line delay circuit and a second state corresponding to the deactivation of the half-line delay circuit, and that the fifth circuit (132, 156, 148, 149) a circuit (156) for receiving the main half-line delay signal (/? ') and the vertical interval signal and for generating a secondary half-line delay signal (R) corresponding to the main half-line delay signal with the inclusion that it is during each vertical interval signal pulse assumes the second state, whereby the vertical sync pulses of the reproduced output signal never delayed and only the horizontal line parts of the output signal to r achievement of the desired intermeshing of lines can be delayed. 13. Arrangement according to one of claims 6 'to 12, characterized by a chroma inverter circuit (151) to achieve a phase shift by 180 ° of the chroma-synchronous part of the reproduced fields and by an 5 6 the composite television signal coupled to the half-line delay circuit in today's long-distance circuit (152) for operating the chroma inverter seTisystemen a continuous sequence of the same circle, if the half-line delay circuit represents time periods, which are called pictures, where it is effective .. with each picture in two equal time periods, Which 14. Arrangement according to one of claims 6 5 fields are called, is divided. Fields to 13, identified by a circle (133) , mesh with one another, these fields containing signals for generating an inverted display which correspond to a full scan of a television of the recorded fields with respect to the screen. Sequence during recording to reverse a The fields are synchronized by vertical running effect of the recorded process to erio impulse identified. The video signal is held in each and separated for actuation by a circle (152) coupled to the heads and the field with horizontal sync pulses to produce an inverse remixing which would give adjacent lines of the television picture. The television receiver contains internal syndes of chrominverter circuits (151) and additional chronization circuits, which, depending on the introduction of the phase change when a 15 vertical and horizontal sync pulses work, new head playback in the reverse playback sequence by one correct scan of the television screen begins. to be supplied. Is when playing opposite the Record a different relative speed between the magnetic head and the magnetic medium . 20 present, this leads to considerable time differences in the sync pulses, which lead to a loss of synchronization in the receiver. To the The present invention relates to achieving a changed time-base effect should the arrangement for a system for reproducing a television signal not changed in the time reference of the sync pulses in a variable-speed mode. speed, in still images or in reverse There are different methods of recording running backwards with a first recording medium zone, and reproducing video signals with a time-base effect changed to the odd fields of the television signal. In a method recorded by a first transducer head, the television signal is recorded by a recording device with a second recording medium zone 30 with a spiral scan on the even fields by a second magnetic tape so that a complete transducer head is recorded, each The last picture or field on each deep track heads is designed in such a way that the recorded half-recorded and that the horizontal synchronized pictures are reproduced by them in a pulse in adjacent tracks in a different sequence from the recording, and the 35 are directed . A suitable selection of the tape speed arrangement ensures that the outgoing playback during playback can be achieved in slow motion, time-lapse signals, a correct interlocking of the effects, or idle picture effects. Has in these fields, with a first sub-circuit method, it is difficult to the recording device for which the by the first head each selected speed of slow motion reproduced einzu- fields responsive uhd each reproduced un- 40 filters, so that the reproduced image noisy even field defines, with a second part of the shell and tends to disintegrate. Also, since the length of track processing, which is re-changed by the second head with a different tape speed responsive given fields and each re the reproduced signal does not satisfy the given round even field specifies and radio standards with a. Third sub-circuit for converting even 45. In a second method, the television field is converted into odd fields or from unsignal to a spiral track on a surface of even fields into even fields. recorded on a magnetic disk and from Normally broadband signals are reproduced (ie the recording and signals with a frequency range of about 1 MHz, playback head moves radially over the rotating disk, for example television and instrument (analog)). On the lower surface of the disc signals from tape devices with transverse scanning, such as a second head in a fixed radial position, for example the device VR 2000 (video) or the. Such a disk recorder FR 700 (instrument data) and tape recorder is not very versatile, is not able to record a color television with spiral scanning, such as the programs and has a relatively device VR 660, recorded. The devices mentioned 55 small playback capacity. are produced by the applicant and are It is still from the magazine »radio mentor drove. Small segments of television signals Wurelectronic, 1967, No. 7, pp. 526 and 527, which has already become known through devices with disk-shaped arrangements, in which circles recorded drawing carriers. In order to provide for those that respond to a changed time-base effect on playback heads devices (in the case of 6 ° reproduced television signals and the first of television signals, for example slow motion, slow and second (or even and odd) fields ruffled and still images) to achieve that must determine. Another circle transfers the first total length of time of the recorded event and second (or even and odd) fields without changing the individual frequencies and vice versa. The entire process is controlled by the. If the relative speed were to be regulated between recording a reference signal, the creation of which in the recording head and the magnetic medium is left open during the abovementioned printed text.
Playback changed, so all frequencies would be in The present invention is now the task Signal changed. In this context, it is based on a special, simple way of regulating