DE1905659C - Method and circuit arrangement for monitoring connections in stored-program telecommunications switching systems for binary, coded messages - Google Patents

Description

The invention relates to a method and a structure and internal units. Of the circuit arrangement for monitoring connection external units, Fig. I shows only the line connections in memory-programmed telecommunication connection unit LC for connecting the subscriber interface systems for binary, coded messages, and trunk connection lines L to the system, in which the lines are connected to a line connection - 5 receives the polarity coming from the lines L for receiving and transmitting the polarity swings and identifies the respective transfer device changes within the binary messages, otherwise by determining the internal connection numbers and the connections between the or addresses of the transfer device dials Hand of the feeders and buyers with the help of a pro-addresses of the buyers the respective Abnehmergrammsteuerüng are set up or dismantled, and with xo lines out and sends polarity change to which the named units with one to the lines L. Via the channel A 1, the in F i g. 1 as a solution to the switching tasks, simple connecting line is shown, but consists of agile data and programs containing a plurality of parallel cores, the Lei storage unit is running, in which each feeder connection unit LE with the storage unit SE is a storage area for receiving a memory - 15 connected. This is permanently assigned from the main memory KS, word that during a connection, for example, a core memory that contains the internal connection number required for the respective customer identification of the switching-related tasks and information about data and programs, the memory via the Direction of the last change of polarity so- Operation control SOW for the execution of the how about the status of one of each incoming ao different memory operations, the memory request polarity change to zero contains change control SAFS for the allocation of the memory and that from the program control in bc- chercycles to the requesting Controls and the correct time interval are read and checked. Program request control PAFS for request, the counter reading being built up in one of the two directions of the last polarity change a ₅ and PSt possible by programs through the control units LE .

is increased by "1" and the triggering of the In the address-addressed work memory KS , a memory area is permanently assigned to each connection when a specified counter feeder is reached. This is initiated. ■ _This memory area, hereinafter referred to as feeder cell in tele-switching connection for binary surnames, takes, among other things, the assignment between directives, which are briefly referred to in the following as data exchange, feeder and customer, as well as the directional systems, must? 1 participant and the last change of polarity. The trunk connection lines for permanent potentials, with storage operation control SOPS include, for example, for permanent start polarity, as triggering criteria, among other things, are monitored from the data processing rium. Thus, connecting lines are known to test the input and output to single current subscribers to 300 ms start polarity register of the memory and the safety sequence control and lines to remote subscribers as well as office with the clock supply and the area protection connecting lines to 600 ms start polarity. Check S / I FS at the memory request control. The existing, independent of one another. Such time-dependent criteria were set up in working controls to meet their requirements for electromechanical switching systems by allocating memory cycles that are recognized and evaluated in dependencies or relay circuits based on their priority class. The tasks of which the tightening and unfolding lines have been dimensioned in accordance with their SAFS saliva requirement control. The tasks of the known data processing system is also a fully electronic remote systems, the usual priority control for the work writing switching system according to the time division multiplex memory (electronic computing systems, 1961, H. 2. principle, in which a calling subscriber receives one of p. 54 to 60 ). Finally, each controller can, through several central links, be assigned a program in itself or in other processes, which an electronic device can request to terminate another controller. Contains such sign recognition. Requests are directed to the central program request in the centrally controlled , memory-programmed change control PAFS, and there with the communication systems, efforts are now made to note data identifying them as far as possible, from all of them switching-related tasks for the purpose of processing units PSt continuously or with the help of suitable ones to reduce effort The central points in time are checked and finally solved by the processing unit responsible for the control and a stored program. The upper s $ is one of these tasks. From the processing units for monitoring connections, In the German patent processing of the programs, Fi g. 1 only the registration PLS 12490.0 did already, a program control PSi process, which is suggested via the channel Λ 2 to the memory unit SE for the detection of permanent potentials. that can be used in centrally controlled, memory-programmed while the connection is being set up from the switching systems, which "0 dial characters determine the address of the recipient, still work according to the so-called code multiple principle. This is inserted into the named feeder cell that writes a memory-programmed connection". When everyone arrives on line L * Monitoring is made possible without decentralized effort. the change in polarity is required by the line connection-the switching system in which this method unit LE is used in the memory request control is shown in principle in FIG. e $ SAFS initiates a storage cycle via channel / 41. The system is, as in the German patent · The registration P IS 37 354.3 assigned to the respective feeder line, but with an appropriate address, is proposed via channel A 1 on request, parallel rm designations, from uter- into the address register the storage operation control

Transfer SOPS. At the same time the information greets thereby the load on the memory and the

via the direction of the polarity change in a word program control,

register, by means of an additional signal, the invention is therefore based on the object

which is transmitted in parallel to the address, divides the cyclical query of the feeder cells

Take line connection unit LE of the memory operations 5 and thereby overwriting poluritiities

control SOPS also with that the content of the change through the program control to ver '

addressed memory cell is to be read. Avoid that as well as the burden of the program control

read memory gets into the word register, and the memory through the connection

without keeping the information about the surveillance stored there as low as possible,

To delete the direction of the new polarity change,> ° This task is achieved according to the invention

because this is, for example, held statically. The solves that one knows the feeder to be monitored

Receiver address and the direction of the polarity marking information to each feeder Changes are then written to the line connection unit in each case with a permanently assigned memory space. LE passed, which will ben the polarity change to the first that each memory location

The relevant line sends during the reading 15 and only when the information stored there

The subsequent writing process within this tion requires monitoring, which is specified in the

The memory word with the information memory word is contained in the count bit combination in the read cycle

tion is checked and changed via the direction of the new polarity change program control, and

written back to the feeder cell. that the changed counts during one

For the purpose of checking for permanent polarity, ao single storage cycle is carried out by a within the meaning of Now in the German patent application mentioned, logical "OR" operation on the memory P 15 12 490.0 has already been proposed, in which additional bits for the memory η-th memory area are written even in the tributary cells assigned to the relevant tributary, provision of a meter reading. The program- In this way it is achieved that only such Control asks all feeder cells in a »5 feeder cells are checked, which are also monitored periodically coordinated the time interval that should be of the. With the help of d'jse's method Duration of the potential to be monitored and therefore save working memory cycles. Beyond that When monitoring a 300 ms long final, the checked is performed by ORing the character is 120 ms. During a query, the memory word with the newly read memory, the content of the relevant tributary cell in the word in the word register of the main memory becomes an incorrect one already mentioned word registers transferred and avoided from overwriting the tributary cell. Program control checked. If the counter reading has this, it can also be achieved that each a certain limit has not yet been reached and two cells are assigned from which tributaries result the examination of the direction of the last polarity - the one the direction of the last polarity feature alternately indicating bits that the 35 to be monitored and the other contains the counting bits; If the program polarity is present, the counter reading is likely to change by "1" then controlling the cell in which the direction elevated. Then the memory word with the last change in polarity is noted, read only. Bndertem counter reading again in the relevant This solution, however, would have compared to the invention Enrolled feeder cell. An occurring disadvantage is that two cells per feeder before the polarity change sets, however, the counting bits would have to be seen again to 40 and that to check the Zero, so that the counter reading follows the specified direction of the last polarity change as well as the Vann only reach the limit when the potential meter reading two cells have to be read remains unchanged on the line for a certain minimum and accordingly two memory cycles. Recognizes that the program is required.

• control when a query is made that the highest counter 45 In a preferred embodiment of the invention

level is reached, the triggering of the load will divide all feeder cells into several

appropriate connection initiated. divided into groups of equal size. The groups will

As already queried in you German patent application at a time interval that is the same as the P 15 37 354.3 was proposed, the quotients of the query interval and the number of the line connection unit requested memory 50 of the groups (step-by-step query). The additional cycles are assigned to these with the highest priority. However, they become bringer cells within a group Interrogation of the feeder cells and interrogation in order to change them immediately one after the other (intermittent countdown requires the program control or ft age). This method has advantages over the monitoring program running in it also an intermittent query of all feeder cells if several working memory cycles, they with 55 of a srjßweise load of the working memory low priority. It can therefore occur in front of and the program control. To ver come that the line connection unit prevents other controls or the, line Working memory cycle is allocated and a connection unit with a new polarity change to be processed quickly arrives in the feeder cell for too long on the allocation of memory cycles writes, before the program control has to wait for a βο, the query of the feeder query would have to take place in the memory cells with low priority read from this feeder point, word with possibly changed counter reading The fluctuations in the query interval of the in writes back to the Zufoinger cell. The feeder cell to be last interrogated in each interrogation cycle could contain the position of the feeder cell, which would thereby make the new device uncontrollable, on-polarity reversal by the program control system erroneously overwritten. In addition, a step-by-step query of all feeder cells with Even the test does not claim that the ν is excessively stressed on the central units of the watchful transferring memory cycles and the advantage that the part of the organization «^

1905 669 5 6

program * integrates with the load on the central units. The program * less is this communicated from the data processing control, which then initiates the triggering, lechnik well-known Organwatiomprogramm air Steue- Compared to this solution has another feature

rurti the simultaneous processing of several profile forms the advantage that the group size gramme runs with step-by-step interrogation with every s, i.e. can be determined by the programmer In the preferred method, on the other hand, step abi is only sent to uitlerdalin, and therefore without any circuit changes, when the interrogation of a group begins. different office sizes is adaptable. At this

trn to prevent such feeders from also being used that should not be monitored. Group \ on tributary cells in a first register can transfer the information for identifying such io to the program control and the number Feeder together with the address of the feeder in a group within the rVr group take, entered the direction of the last polarity sweclmls second register of the program control and the counter reading in the respective feeder zcMe. The content of the first register is then for each stored «earth. Step of the query command and the content of the

Less memory cells require cmc, especially 15 second registers reduced. '

advantageous embodiment of the invention, in the case of an advantageous circuit arrangement for

In each case only the feeder cells to be monitored. Carrying out the aforementioned interrogation procedure with j

be queried. This solution consists in that An / eigenfcld becomes the address of the first memory *

the cell of the display field that characterizes the feeder to be monitored at the beginning of the query of a Information in a so-called display field to group of feeder cells in a first * register is stored within the spoke. in which everyone is transferred to program control. The feeder cell to which the operation is to be queried is assigned a fixed bit. Control receives the content of this register in each case is. This display field is made up of a block »on after processing the addressed display cell and immediately successive memory cells controls the transmission of the in this display cell forms. In each case one memory cell of this display as contained memory word in a shift register field is taken over by the program control within the program control. The content of the < and checked. Only those feeder shift registers are queried until a test cell whose bit is in the named memory cell is set to a monitoring request «1 · is set. characteristic binary state of the output

In a further exemplary embodiment of the invention, the display frame appearing in the shift register is known before the feeder cell to be queried and the further counting of the counting or the Checking of the count in a complete shifting of the shift register prevented. the Memory cycle read. Only then is the address of the to-memory operation assigned to the display bit »or the changed counter reading is brought into being with the help of the first registers and placed in the feeder cell. Any increase in the 35 of the count is formed.

Counting reading basically requires two. In this embodiment, it is possible to

Memory cycles. This will be done in the program control in any case when it is used again Fühningsform of the invention avoided that existing switching elements the effort for the First of all, basically lower the number of the connection monitoring purposes to be carried out requesting feeder cell with the storage operation 40 So a general purpose register def program control "Or" is used as the first register at a certain minimum level: the usual battery position is then checked, whether the counter modulator is used as a shift register and that too With another storage operation "Or", the accumulator's shift counter was known as increased again or the connection triggered counter used.

must be or whether the next feeder cell from- «Further details and advantages of the invention asked to throw. Since connections are seldom explained on the basis of the drawings. It fits are to be triggered and also an increase in the counter F i r. 2 a schematic representation of the cross-sectional

standes with another storage operation "Or" system with the most important ones to carry out is rarely required, this method of address counting register method requires significantly fewer memory cycles. 5 ° borrowed registers,

The formation and provision of the addresses of the F i g. 3 the structure of the address counting register, Feeder cells happens with a simple fig. 4 the most important registers of the program

Implementation of the invention with the help of an address control for carrying out the method with Counting register within the program control, the variable group size,

via an address register of the program control with 55 F i g. 5 the most important registers of the program control the address register of the memory operation control for carrying out the method connected is. At the beginning of each query cycle is the display field.

Start address of F i g receiving the feeder cell. 6 the formation of the address during the procedure Memory area stored in this register. The ones with display field,

Operation control for the query command increases 60 Fig. 7 the arrangement of the display cells in the the memory and at each step of the polling cycle

Address counting register to the distance of the addresses Fig.8 the flowchart of the special command for

of the feeder cells to be queried and triggers the connection monitoring with display field. Reading of the addressed feeder cell from the in FIG. 2. 4 and 5 are all lines to the par-

Memory off. Since this embodiment only has a 65 aHelen transfer of memory words with thick Requires relatively little circuit complexity, lines are suitable, all control lines, on the other hand, with thin ones they also signed up for a decentralized arrangement of the lines. The drawings contain only Connection monitoring in the line connection - which is absolutely necessary for understanding the invention

MMiLk fi! d, it SSL «/ n ^{if u} . ^H fi ^sartschlu f requests Spekher cycles on Speiehef,

rCEwiSs · Ρ% "^ sssssssas

control ™% ST Sl? ^Pro « ^{ram connection monitoring is} required. the

The Ar! the fLäinl ⁸ μ ^ written tion »00« corresponds to the counter reading · ()., the Kom- ^ ÄiriSSÄS the SÄ ^e ' ^Cher - ^{binalion 8lne dcm ZähI} ^ "d * U and the κίΚ-settable by the controls SZp ^ ί ReI ^. TT '-'I * ^d T ^ ¹¹ Jf "' ³ " ¹¹ ' ² ' · ^This Z «"'er-OP _Ä for the memory operal ^ codfd'cöd ^ Fte * ΆΆ?% £ ^ ^ ^ * * ™ ™ "Speicherabiaufsteuerung sst met in a hi '^ ^u" f ngerzeiie reached

As is well known, the tasks of the clock w "l""H" J ^ u *? ^ T, ° ™ ^P B ^{e VOn Zubri} "gellen

Area protection test ^{8 of} the sJdcheS de? Kv S ί "VS Tf ^kt J * *" · ¹⁰¹ P ¹¹ ^ ^{31111 Of} testing and I-wire selection The 'ΑήΖικίΤT ' ^{75 mS with the help of the program} requirement control ARS or the word input rule WER are TeS "*« "" ^ TT " ⁰ ^ P ^ ³ " ¹ " ¹ » " ^fo ^ on occurs both from the LeitunlsanschlusseinheiVLE al? Tch? S? 7« ίΤ '" ^αεΓ , ί ^{ει1ΐ5ί: Ιιεη} patent application from the address register ARP resp. vomι wörtrenSr WR ρ · f Il _c r ⁰¹ "?" ¹¹¹ ""^{"1" 1} method. I _n the program controlling ™. PSt VrrZhulr ^g £ \ u ^Flg · ^{2 '4 and 5 is this''} ROGRAM s TART by the control ⁸ access to Sfesef RJSSSfShI? ^ f ^^ ^^ tri TG, which after every 3.75 ms separates the sfeSeSdeiSSSueiii ⁸ dl ^"4 ° ,, ^{the Elnschrelben} Staitadresse ^the ADR of the control überleweils £ HHSS? 1SS £ the ^Wa _I ^ch _R ^un ß ^s P ^r ° g ^{r3mms in the} instruction counter to assign the lowest memory cycle and via dkStener '■ ·? ^{3S Obe} ™ ^achm pP ™ Z ™ "™ consists of the

line L1 or L2 the transfer «.,« »!« t essentially consists of a hardwired process,

a wired sequence to Ahfräa ^ · 7 κ ^{5 em Befenlsre} g ' ^{ster 5Ä of} the program control P5i

zellen dargesSote * ί ££ Oc] Zn ^ Sn '^ / ^ T' "f" T 'Γ - ^ ί ""? * ^{Γ Vcr} 'the feeder cell is in a R! If ⁸ binding monitoring be. Start of querying a

Content according to various VSÄ ί "'"^"GrUPPC ° ^{of the" def Bearbeilun ach} g ^cin it can Auslöseden (Fi -Fi d Λ AZR 4% RC ^& oT I P ^ro g ^ramming is needed over the Bcfehlsdecodie- RB) The addr "<: _P ",» ■ " ^g '," i " ^h ' g- ^{5: Λ / 1} '55 rer becomes the operation control VUE for the

S of di ^^ SATSSn ^ ¹¹ ? ^{118 S} P ^{CZialbcfdl1 aüs} ^ ^vähIt ' ^{dic in a} "« «h known"

solution program into another Reg Z'aPR ^ T ™ ™ ^ ^ '^^ f ^a "% ^ch ··!« · -in can

Transfer program control TO ^{§ dCr} Speiser D, g «alc Rcchcnanlagcn, Springer-Ve.rlng.

In the following it is preceded by ^ ,,, ^ n , ",". ' ^ L \ ll ^l ) "Ρ. ^Κ .P» * " ¹¹ " !! » ¹ ™ "· ™ ¹ « 'W controls

,) plcuerung

^ SnSig ^ cSSclSmS? ^J """i" Dependency on the system clock dfe AusmlmS

η ^ nM ^^ T ^^ ™ ™ - ™ <· «Query.bcfoh.s. The Bcfeh. is «ended when

Oiarila. of 3 (Ki ms monitored Sd D e 7 Znacr "™ , Γ" · """^"'T ^ ί ^ ™ *** « "<·

,, <Ι | .. _η ... "_ ,.",. . . . · ^{> Jl {} - '- »" nnger- what by one of the Pn-: ifomk / 7. Überu-n-hr. ··,

'a cnlanrnS,; "™ .Ts mS"'" ^Λ ^ German counting YYY. RB fes.gestell, wird, Der .ηΐ,". ',.

SSl ή ,, '- "' vorgesdi - R ₅ Hcld.ls/iihk-rs is now from 'Icr iViitlc ^ ik PI ₀ '.,"

i P / Z See "? 'ι ,, Il .!"" ^abllC ^ ¹ , ^Si "·'.'"^ ™,! -" n «l, .on, Register ARP ii.v.gdVn. · IX - _r ^

i? ^g """ ^l ™ P ^m PP ^c " - addressed ik-iic Hcfehl pcl.-incl ÜIkt. dns W '

"Zubi ge, Ie, l ', ogr _: " nn, se.e, ung in .I; i, Ik-relUsie

1 906 659

the next polarity change which initiates the initial state for the query of the start polarity

next group of tributary cells is established, the counting bits back to "0" so that no

the monitoring program is also ended. Error arises.

If the test logic PL has checked the bits / V, with every incoming polarity change, P ₁ X, Y at the word register of the program control S the counting bits in the relevant feeder cell are recognized as a connection to be released, the "0" is set. For this purpose, the line * content of the command counter UZ increases the corresponding bits in the Wtm <by the test logic connection unit LE , and the address of the relevant feeder input register WER to zero. Through the memory cell in the register APR of the program control operation »read-change« is then transferred in addition to the one to which the following program for the new polarity change also has access to this counter reading from the triggering of the connection. Given the word input register in the feeder cell, those for querying other feeders are written.

cells in this group necessary data in The various embodiments de; Invention registers ensured that the tripping program training differ essentially in that they are not accessible. With the next command, 15 type of address formation for the address to be measured, the operation control VVE by the requesting feeder cell. In the control program increasing the program counter is established, the process is according to Fig. 2 is a Adressenzählregister AZR vorgramm initiated for triggering the compound AP, seen, the contents of which will be explained in any more detail here by the operation control its expiration. VVEl after each execution of the last opera The program request runs in the same way from 40 tion when the last requested request is requested.

as when the monitoring program is started by the bringer cell, it is increased by »2«, if as above

the clock generator TG. The last command LB of the tripping was assumed - each line two on one-

program then resets the command counter to other memory cells that are assigned and the

the start address of the monitoring program or. Direction of the last polarity change as well as the

if the counting bits for querying the other feeder cells * s are in the first of these two feeder

data required within the group that are stored in the bringer cells. The address count

Address of the next to be queried feeder cell register according to Fig. 3 consists of a basic

and the number of feeder registers still to be queried that can be plugged in and

cells during the processing of the triggering program the start address of the block to be queried dei

gramms were determined, on a command to the 30 feeder cell, a group counter G2

Load the registers for each cell to be queried to count the queried groups Newfinger cell. 'counter ZZZ for counting those within a group

The memory cycles for reading the tributary cells already scanned one-bit tributary cells are each requested by the operation control VVE at memory E to determine an overflow of the memory request control S / IFS. 35 cell counter and a further one-bit memory F. The operation control also controls the setting of the register OPR for the memory operation code, however, after the increment of the contents Word register WR is stored, so that the content of the content of a feeder cell, interpreted as a decimal number, is determined by the test logic PL prepared by the address counting register, which is always an even number. Y = "00" in 512 feeder cells in 32 groups of 16 feeders each · X, Y = "10" or from X, Y = "10" m X, Y - "11" feeder cells, the line counter must be changed to four digits must be (P = "1", N = "0"), then and the group counter will have five digits The address of bit X or bit Y in the word register to "1" of a feeder cell is set from the content of the base; none of them Bits to be changed are cleared t. 45 registers, the group counter and the number of lines The operation control now requests a memory as well as the one-bit memory formed by the bit «cycle and loads the register OPR with one of these registers parallel to the memory or the memory operation corresponding to the» or « Combined program control are transferred. According to nation. The content of the word register is processed into a group of 16 feeder cell word input registers WER and the address of the relevant feeder cell is reached in the address register ARS Overflow memory £ is set and transferred to the groups. The word counter advances the memory word by »1«. The check logic PL passed output register WAR , with the help of which checks the overflow bit and informs the operation / operation device OE with the contents of the word control KtVEl, if necessary, that the abcing output register WER is linked and terminated with a change request command. The over tem counter reading is then written back to the memory. lauibit E returned by the test logic PL . It can happen that the line sets.

connection unit LE the counting bits and the P-bit of the query can also be different Zubrin

resets the relevant tributary cell to zero, if either the

before the new counter reading with the memory group size, ie the counter ZZZ ode <- the count

tion "Or" was entered in the feeder cell. end, ie the memory E, designed to be pluggable

In this case, they are created in the feeder supply.

the memory operation "or" the count bit combinations

tion »10« «tier» 01 «. However, since this also offers the possibility of the number and the

Feeder / rush assigned line that is not ω S ₅ size of the groups of tributary cells differed

Monitoring polarity, in this example stop to match borrowed feeder numbers, is shown in FIG

Polarity is present and the counter reading therefore not shown there contains cir

is changed, the stops the monitoring of the RC registers to receive the address of the

11 ^υ 12

(protruding feeder cells in a counter RB, the 16 feeder cells, so for example the Öit 18 with the shift counter of the accumulator idert · each display cell is set to "f",
The sehaltungstechnisehe realization of an Ab 'queried feeder cells within a group question with display field shows PI g. 5. Öie there * indicates. At the beginning of the interrogation of a group, the program control set is differentiated from the register RC with the start address of the group as shown in FIG. The arrangements shown in 2 and 4 are only loaded, then the query command is passed through the registers for address setting and the read and operation control Vl) El * Operation control VÜEi, which selects in through the sequence. The number of feeders to be queried * of the query command-related details from the AuN cells is contained in the address part of the command and if the construction of the VUEX and KfE 2 controls differs, it is transferred to the counter RB from the command register BR . In order to interrogate a group of feeder cells, this transmission is already controlled by the operation unit, first of all the relevant display cell in the pro controller VUE1. The start address is available for program control. Notated with the \ u in an auxiliary cell of the memory. The contents of this example 1-digit address of this feeder to the register RC are loaded at each step of the interrogation cell, the 1-digit multipurpose register is loaded from the operation control VUE1 to the RA. The content of this memory cell is incremented by "2" so that the address of the next bit to be stored in the accumulator AK, the bit from the accumulator which identifies the end of the group, is stored in the register RC. The content of the register RB , on the other hand, is transmitted in one-bit memory E in each case. The content of the is decreased by "1" at each step of the command. ao accumulator is - controlled by the Opera - When the group is processed, the control VVE 3 is therefore - with each clock pulse to register RB to zero. This is shifted one place to the left by the test logic PL until the test device detects it and reports a "1" to the operation control VUEl device P at the output of the accumulator, which then detects the address increased by "2" and the supply of the clock pulses to the last feeder cell as the start address that blocks the accumulator and the counter RB. With every next group in the auxiliary cells, the clock pulse T writes back the shift counter RB des and the command counter BZ advances. Accumulator with one of the number of display bits

If the test logic has recognized a line to be triggered in a display cell corresponding to the counting capacity and reported this to the operations control, increased by "1". Both the shift counter RB and the address of the relevant tributary cell 30 as well as the one-bit memory E are monitored by the test logic from the register RC into the general-purpose register APR PL . A group of feeder cells is transferred within the program control, which is then processed when the shift counter is accessible for the subsequent trigger program and the one-bit memory is set to "1". is. The triggering program is already used in the The formation of the addresses is shown in Fig. 6. Requested and processed in a written manner. If 35 memories for 32768 = 2 ^IS words have ended the addresses of this program, the status of the is a length of 15 bits. The addresses of the registers RC to be interrogated, which existed before the requesting of the triggering tributary cells are made up of three parts on the program, thus restored, built, each of which in this example consists of 5 bits, the address of the relevant tributary cell. The first part is the fixed basic combination, which can be plugged in and therefore can be changed from the multipurpose register APR to the register RC 40, and which is transmitted. Then the query from the start address of the dry feeder command is read again and the operation control depends on cells; this part has the highest value selected. speed. The task of the group voter in selecting

In the above-described embodiments, the embodiment according to FIG. 2 also takes over from the invention tributary cells of such 45 last 5 bits (11 to 15) of the address of the display cell stored in the register ΛΛ ge lines that are not monitored. Dien applies to should. These are lines that have no connection. The feeder cells are divided into 32 groups. .. are involved, and in the reverse direction through- If 64 groups are formed, self-switched trunk lines; this includes the last 6 bits of the register RA for the majority of all lines. For this reason 50 address formation is used. Since it is advantageous to use lines to be interrogated to identify the last bits for counting the groups and to read only those tributary cells that are to be, the last 5 bits in the lines that are initially monitored must be assigned. All adresses of the display field have the binary value "0", therefore bringers that are to be monitored are. The starting address is an integer number during the connection establishment in as much as 55 times 32. The display field called for counting the feeder cells is noted in the memory. This display field shown in a group in Fig. 7 is made up of a size of 16 (2 ") tributary cells, the last four blocks of consecutive memory cells are used on (/ 1) bits of the counter RB . This counter RB is built, for example each storing 24 bits is, of which increases with each step of the accumulator AK order for display purposes, respectively the first 60 "1" If the Zähier expired., this 16 bits will be exploited. each feeder cell is detected by the checking logic PL and the Opcrationsjeweils This bit is reported to the control VUE3 , which then increases the content by "1" during the connection setup by entering the register RA . Set to "1" at the positions of the display command. The end of a counter RB is a Another bit is added, which is always group G of tributary cells with ei; ·, «;» 1 «65 and has the value» 0. In this way, one of the for tributary cells is reached n not used that only every second tributary cell is read. Positions of the display cell marked. Existence The address is composed as follows of the reasons, as assumed above, in each case from men: B, RA (11 to 15) RB (3 to 6), "0".

Cj

13 U

The sequence of connection monitoring indicates that the accumulator should also contain "0" in the display field Htm'on the basis of the bit shown in FIG. 8 (II /?), So the test logic PL represents the flow chart. Determines whether the bit at the output of the accumulator before this diagram is the usual notation has the value "1" (Π I), if this case is used. A register designation with after- 5 not before '(UIn) ₁ then the test logic gives the way for the number placed χ denotes the .v-th bit of the register. the clock pulses T free; the shift counter RB If the symbol AK for the accumulator is increased by "1" and the accumulator AK is indicated by an arrow, a subsequent one means shifted one place to the left (UI). The test number, if the contents of the accumulator by the "AKI - 1?" Is then repeated. If the number of steps specified in io supply AKl = 1 is met (UI /), the status of the arrow direction is to be shifted. The counter RB in brackets increased by "1" and the name of a register provided with the accumulator AK, e.g. B. (RA), Moved one place to the left (V). The after identifies the content of the memory cell, the address formed by the rule given above, the content of the register is addressed. If there is one, the address register ARP is followed by a number with the program symbol (RA). 15 Transfer control (V). The operation control so designates this the corresponding bit of the ViO now requests a memory / cycle. The one in memory cell. For a positive decision, the processes shown in block VI run within the diagram in each case the letter "/", for a negative a single memory cycle. The test logic PL tive l-ntscheidunp the letter "" used first sets the first of the two counted bits, ao bits (bits 17 and 18 of the memory word) to "1" and the process is started by a clock, clears the others Bits of the word register WR. Which the loading of the instruction counter BZ with the address contents of the word register WR is now the Uberwachungsprogramms comparable cingabercgister WHO and the contents of the addressed anlaßt in the Wortdes first command. Initially, register with the RA Zubringerzclle in the word output register WAR is the address of the transfer to be processed display parts loaded 25 Speicheroperationsstcuerung SOPS and then linked to the content of this display cell in by the memory operation "Or". That transfer the accumulator AK . The result is then transferred to the relevant feeder cell. The shift counter RB is initially written back to "0". The feeder cell is set and bit 18 of the accumulator, which now contains the counting combination "10" or "11". Group endc identifies, in the one-bit memory E 30 The program control now takes over the transfer. Bits 17 to 24 of the accumulator in the word output register WAR are then deleted (I). By a parallel changed memory word in the word register WR. When the bits of the accumulator are checked, the test logic determines whether the polarity bit P stored in bit 16 of the word operation control VUE 3 with the help of the test register has the value "1" logic PL. whether all bits of the accumulator AK have "0" 35 or "0". If this bit has the value "0" (VlXn), are set. If this is the case (II /), then the lei group of feeder cells assigned to the feeder cell is not fed to stop polarity. The expiry will then have to deal with the more. The next parallel test of the accumulator AK will therefore continue to be queried for the display cell; the content of the RA register (II). If, however, the condition WR \ 6 - 1 is met, the value is increased by "1" and the content of the new request continues to check whether the condition show cell is also transferred to the accumulator (XIV). WR 17 0 is fulfilled (VIII). In the event of a negative decision, the one-bit memory E is set to "1" (XII /), then the sequence (VIII ") is again followed by the test logic that reports that the group has been tested in parallel with the previous parallel test of the accumulator (U) continued, processed feeder was terminated, and the A positive decision (VIII /) leads to the operation control VVEi increases the command 45 Check of the condition WR IR -1 (IX). If this counterBZ is "1"; the query command is now not fulfilled (IX «), so the second count bit ends in the. Stored in the register RA address of the word register WR - like next to enhance the earliest count bit to be processed display parts in a described - the memory set by the check logic PL to "1" auxiliary parts transferred and available for and after the Operationssteuemng VG3 a processing of the next The group is back to the memory cycle and the OPR register is set. Before the monitoring program f; i. which - with a second "OR" storage operation, has finally ended the group that has just been processed, has entered it into the feeder cell, so that the program control PSt must now still contain the combination "I" (XI). Following this specific question as to whether the address A 1 of this display section is cheroperalion, the parallel test of the smaller or larger than the address S5 accumulator AK increased by "I" follows.

Al the last cell of the display is. OiII that meets now on that of the relevant feeder cell Relation A 1- ^ A1, the line assigned to the program processes a polarity change in and out

control also "the cell with the address AX in the sets the Lciischlusscinlici« LIi da * tf-oil and

usual way. Ui, however, the address Ai greater the taiilbhs in the feeder cell on * tfo before the

as the address A 2, then a processing cycle is filled in the mentioned auxiliary operation control VUEi

cell, the start address of the display fcldcs, the operation Xl is received, so after filing

written and ficim nilctiMen clock pulse the transfer of the operation Xl die Zlililr) ilk «mliinnlion» 01 «

monitoring started with this display / hurry to be stored in the metering clock. This combination

lsi the l'Jif'IJil'Hpeicfier not on "I". instead, in the case of Ülierftaiig, ntitiitn is set to the tilleriitif "0" (XII / ι), so bcginnl tier Ablmif 6 "Wiiihciulen SlarlpiilarHiil back to" 0 "gwet / l.

again with tlem Nullsel / en ties Verscliiebc / iiltlers l-intii tripping «uiisili recognizes the l'fiiflojük / 7

MIM /). (tiiriin. ilnli ilk · lk <(li (iuitti | < WH IN I (IX) i-rfltlll js |

• llniu · tlie l'testing the Akkuinulaiiiiinhiill (ll) tr- Dei liiliiill ik-s accumulator AK is wiihftucl ilci

Processing has been shifted to the left step by step, the processed bits being deleted and re-inserted into the accumulator on the right. The shift counter Äß indicates the number of steps. The operation control WE 3 now to the accumulator AK its contents to the right-shifting clock pulses T and the VcrschiebczählerÄB its contents each step to "1" degrading clock pulses T to. If the shift counter RB is reset to "0", the accumulator AK is also back in its initial state; the zero position of the shift counter is recognized by the pilot logic PL . The operational control VUE3 then interrupts the supply of the clock pulses and sets the bit stored in the one-bit player E back to position 18 of the word stored in the accumulator. The operation control ΙΊΙΕ3 then opens on a signal from the test logic, the transmission paths between the shift counter RR, the register RA and the base and the Mehrzweckrcgislcr Apr and transmits the address of the associated one of the compound to be triggered Zubringcrzellc in this register. Before the draw is initiated, however, the data required to query the other feeder cells, the contents of the accumulator and the address of the display cells stored in register RA are ensured so that they are available for further processing of the display cells after the trigger program has requested. The contents of the register RA and the accumulator AK are therefore each transferred to a memory cell. Once the program request has been completed, these data are again transferred to the register RA or to the accumulator AK . With the help of the query box to be read again, the group of feeder charges is now processed further.

In the context of the invention, it is possible for you to monitor the lines for permanent stop polarity in an analogous manner. With an additional statement in the query command, which Bcfehlsdecodicrcr D is decoded and causes a corresponding setting of the operation control VVEi , one can achieve that the counter reading is increased with start polarity or with stop polarity or with both polarities. After each reading of the feeder code (VI in Fig. 8), a decision is then necessary on the basis of the information mentioned as to which path to set the feeder code to “1” (e.g. 17 for start polarity. 19 at Stop polarity). This is followed by tests analogous to decisions VII and VIII according to FIG. 8. The process is continued with decision IX.

In the context of the invention, it is also possible to monitor connections with / wci at the same time with different trigger times (.1 (K) or 000 ms). In the feeder cells are then told which exchange the lines in question are responding to are silent, In this case the query is twofold: In the first query, all Feeder / rush processed in / while cycle on the other hand only the feeders of the loamy ones with 300 ms AtislMsezelt queried.

Gs is possible, however, further monitoring after the detection of .100 ms Slitrtpolti * rllUl from the PrflimmslctrefMiig wiilirend der Hoitrbdfting des AuslMsenrngrnmms / ti leave. The program control sctzl dnnn the count bits in the relevant feed block on "0" ^u "d stores information about the first time the counter has been reached. If the triggering program is started a second time after 300 ms

requests, the program control finally releases the connection.

However, after a delay time of 300 ms, the program control can also activate the relevant Query feeder clock and check the counter level.

ίο If this is unchanged (»11«), the connection is released.

Claims (1)

Patent claims: 1. Procedure for monitoring connections in spcicherprogrammicrlcn Fcrnmcldcvcrmitl- systems for binary, coded messages, in which the lines to a line connection unit for receiving and sending the polarity cycle within the binary messages so connected and the connections / wipe the feeders and consumers with the help a program control on b / w. are dismantled, and in which the said line connection unit and the program control with one of the data and programs necessary to solve the communication tasks Containing Spcichcrcinhcil circulate, in each feeder a storage area / ur recording of a memory word is permanently assigned, the w: ih- At the end of a connection, an internal connection number identifying the respective customer and information about the direction of the last polarity switch and the status of one of every incoming polarity change to zero contains reset counter and that of the program control in certain / urgent Distance is read and checked, the counter reading in one of the two possible directions of the last polarity change by "1" cr- i-o is increased and the connection is released at Reaching a specified counter status is initiated, thereby marked / eic Ii net, that information identifying the feeders to be monitored is sent to each feeder ger in each case permanently assigned 'Ipcichcrplat / is written that in each case this first Storage space and only when the information stored there requires monitoring, the information contained in the specified storage word Count picture combination is checked and changed in the program control and the changed Counting bits during a single memory cycle by means of a logical »Or · effective operation on the memory itself in the the memory area assigned to the relevant feeder can be written. 2, method according to claim 1, characterized in that indicates that the query procedure is over a query cycle during which each Feeding tfcllc Im containing the counter reading Memory is queried once, can be distributed glcfchmilUlg (incremental query). .1. Process according to claim I, characterized in that / ti Hcglnn anvs Abts friige / .ykln * ulk Ziihrinper / ellvn tinmtlU'lbiir tindl · dnntidei iihpcfrnpf (MoHwcIse query). 4. Verfuhren iiin.1t claim I ₁ thereby fit '* h dall siinnlitw ZtibrlngerA'tliit in I 905 659 // several equally straight groups are divided and that the tributary cells within a group are interrogated, but the groups are interrogated step by step, 5. The method according to any one of claims I. to 4, characterized in that one! The feeder cell to be queried is read in a first memory cycle and its content is buffered in the program control so that the The counter reading is checked and, if the polarity to be monitored is present, is increased in a second storage cycle with the storage operation "OR". 6. The method according to any one of claims i |> is 5, characterized in that the at one certain counter reading the binary value "1" having counting bits of a feeder cell to be queried independently of the stored one The polarity in a first memory cycle with the memory operation "Or" is set to "1" so that the unmodified memory word temporarily stored in the program control is in the Program control is checked and depending on the stored polarity and the Counter reading of the unchanged memory word, the counter reading of the feeder cell in a second Memory cycle with the memory operation "Or" increased or the connection released or the next jubilee cell is queried. 7. The method according to any one of claims 1 to 6, characterized in that for monitoring connections with the monitoring periods T or 2 T (single current or double current subscriber) in a first Abfragetyklus all feeder cells are initially interrogated and processed and only in the subsequent interrogation cycle the feeder cells assigned to the feeders with the monitoring period T are processed. 8. The method according to any one of claims 1 to 6, characterized in that for monitoring connections with the monitoring duration T or 2 T, the counter reading in those feed cells that are assigned to feeders involved in a connection with the monitoring duration 27, after reaching the maximum value corresponding to the monitoring period T it is reset to zero, that information about the first reaching of the maximum counter value is written in an intermediate memory and that these feed cells are queried again during the following monitoring period T and that after reaching the counter maximum value again the connection is released SS '). Method according to one of Claims 1 to 7, characterized in that, in order to monitor connections with the monitoring parameters T or 2 T after reaching the counter value in feeders, the feeders involved in a connection with the monitoring value 2 T are assigned , the connections in question are delayed by the major difference 7 'and only triggered immediately. «S. II). Seduce me to one of the claims I to Ί, diidiirih nvktmt / cidimi, diili rik · den / ti hiiiik'ii feeder kunii / vitlincmk · information together with the address of the respective Ame «. Λ * ^mmn f ^d . ^eS ™ » ^m « ^{Ilse | s} and the counter reading is stored in the respective feeder cell. π method according to one of claims J up to 9 characterized in that the information identifying the feeder to be monitored is in a so-called display field is stored within the memory, in which "the feeder cell to be queried is fixed a bit It is assigned that in each case one memory cell of this display field is taken over by the program control and only those tributary cells are queried whose bit is set to "1" in the named memory cell 12 circuit arrangement for carrying out the method according to one of claims 1 to 11, characterized in that the Speicheroperat'ionsstcuerung (.WPS) a word input register (WER) for receiving the respective word to be entered into the memory and a word output register {WAR) for receiving the respective A word read from a memory cell contains that the outputs of these registers are connected to a logic device (OE) connected in front of the memory input, with which the contents of said registers can be connected depending on a control signal which determines the type of logic operation and which is generated in a control device (SST) from the data stored in a SpiMcheroperationsrcgister (OPR) of the program control or the line terminal unit this register (OPR) is formed übergebencn information. Circuit arrangement according to Claim 12, characterized in that each memory word actually read out from an interrogation is transferred from the word output register (WAR) to a word register (WR) of the interrogating program control and for checking the bits provided for connection monitoring purposes within this memory word a test logic (PL) is provided, which is controlled by an operation control (VVE) , which opens the transmission paths between the registers of the program control and between the memory and the program control, for the sequence causing the interrogation of all feeder cells in each case in the operating state when the word register (WR) contains a memory word to be tested, that the test logic (PL) changes the counter reading stored in the word register and, when the counter has expired, sends a control signal to the operation control (VVE) , whereupon this initiates the initiation of the trip, and uaß when the counter has not expired The counter stored in the word register (WH) is transferred to the word input register (WER) with the possibly changed counter reading for the purpose of changing the counter with the word of the same address in the memory. 14. Schiiliunjtsiinordnuitg nneli one of the claims 12 or M for the implementation of the method according to claim W, thereby pel «escapes, because the address is in each case with an address register (AXK) iitiit-rliiilb« kr l'roi < ritniimtctit, 'MiMg (/'.V/) niiiom tins is connected via an address register of the program control with the address register of a storage opening control (SOPS) so that at the beginning of each scan cycle the start address of the memory area receiving the feeder cells is stored in this register and the operation control (VUEl) has the address counting register (AZR ) each step of the interrogation cycle is increased by the distance between the addresses of the tributary cells to be interrogated and the reading of the addressed tributary cell from the memory is triggered. 15. Circuit arrangement according to claim 11 for performing the method according to one of claims 1 to 9, characterized in that the address counting register (AZR) in a first register (B) for receiving a fixed base address, a second register for counting the groups of feeder cells ( CZ) and a DIE ao »em upstream third register is divided for counting the feeder cells (ZZZ) within a group, that the extensions switching pulses of the operation control (VUEl) are supplied to the cell counter (ZZZ), which after processing a group of the highest level and a one-bit memory is set to "1", and that the test logic (PL) recognizes this state and sends a control signal to the operation control (VUE1) , which causes the address of the next command to be transferred to the command counter (BZ) . 16. Circuit arrangement according to one of claims 12 or 13 for performing the method according to claim 10, characterized in that the start address of a group of feeder cells is transmitted to a first register (RC) of the program control (PSt) and the number of feeder cells in the Group is entered into a second register (RB) of the program control, that the register (RC) containing the start address is connected to the address register (ARP) of the program control and that the operation control (VUEl) in each step of the query sequence in each case the content of the first register 2.0 (RC) around one of the Distun /. the feeder / rush in the memory increases the corresponding number and the content of the / wide register (RB) decreases by "I", and because "the counter reading" 0 "of the second register (RlI) can be determined by the test logic (PI-) and this thereupon emits a control signal to the operation control (VUE1). 17. Circuit arrangement according to one of claims 12 or 13 for performing the method according to claim ti, characterized in that a first register (RA) is provided within the program control, into which the address of the first memory cell of the at the beginning of each query of a group of feeder cells Display field is transferred so that the operation control (VUE3) changes the content of this register by "1"t; * <ü after processing the addressed display parts and effects the at least partial transfer of the memory word contained in this display cell into a shift register within the program control, that the content of the shift register is shifted, with a counter (RB) counting each of the shift register steps at the same time until a test device (P) recognizes the binary status of the display bit appearing at the output of the shift register and the counter (RB) continues to count or the advancement This prevents the shift register and the address of the feeder cell assigned to the display bit being formed with the aid of the first register (RA) and the counter (RB) . 18. Circuit arrangement according to claim 17, characterized in that the accumulator (AK) of the program control is used as a shift register and the shift counter (RB) of the accumulator is used as a counter. 19. Circuit arrangement according to claim 17 or 18, characterized in that the address of the feeder cell from the fixed content of a base register (B), the last digits of the address of the respective display cell stored in said first register (RA) and the content of said counter ( RB) is formed. For this purpose 2 sheets of drawings