DE1900166C3 - Control element for an electronic data processing system - Google Patents

Description

6. Control element according to claim 4, characterized in that the fixed decoder (36) is the linking device (24) is arranged downstream, through which the bits of the first group (22) of bits the output register (21) can be transferred to the group control register (26).

7. Control element according to claim 1, characterized in that the group control register (26) said first group (22) of bits during a plurality of consecutive memory cycles stores and thereby the part (22) of the output register (21) with which the group control register (26) is connected during these memory cycles for generating further micro-operations permitted to use.

8. Control element according to claim 7, characterized in that that the bits of the first group (22) of bits in the output register (21) are under control can be used as branch addresses by the linking device (24).

9. Control element according to one of claims 1 to 8, characterized in that with the output register (21) are coupled via a linking device (25) downstream of the fixed decoder (36) to branch address registers (51 to 55), in which branch commands can be saved.

The invention relates to a control element for the generation of micro-operations with a Read-only memory in which a multiplicity of microinstruction words are stored, each of which consists of a plurality of bits from which the micro-operations are derived, with control means to generate prescribed micro-operations depending on the micro-instruction words, with an output register in which the microinstruction words read from the read-only memory be temporarily cached, and with access facilities for such access too

the read-only memory that micro-operations to meet operational requirements in a prescribed Sequence are generated.

It is already a microprogram controller one

program-controlled calculating machine known (DT-

switched amplifier (71, 76) included and 60 PS 1195 074), in which the in an n-digit Bedaß each AND gate (70, 75) with its one error register predetermined commands in a sequence and

Combination of several elementary operations can be resolved with the help of 2 "incremental chains, whose active outputs control the individual elementary operations. They consist of a memory words output from a command part and from an address part. The command part becomes after storage in a separate register

Input for receiving a bit of the second group (31) of bits and with its other Input for receiving a group control decoding signal is used.

4, control element according to one of claims 1 to 3, characterized in that an additional to a third group (35) of in the dispensing

used to control various decoders with the help of hard-wired micro-programs can be controlled. The disadvantage here, however, is that a change in the respective microprogram is not easily possible.

It is already known (see "The Best Way to Design an Automatic Calculating Machine", by M. V. Wilke, Manchester University Inaugural Conference, July 1951, pp. 16-18), a calculator that works with a variable command group. Usually the programmer is responsible fixed set of commands available. Each command consists of a sequence of elementary operations or so-called "micro-operations". The practical application of these micro-operations forms the basis the execution of most of the respective machine. For each instruction is the micro-operation sequence normally specified in the respective machine. In connection with the above known computer has now been given a device with the help of a programmer can assemble executable micro-operations into any instruction. In this way it is possible to change the command repertoire of the respective data processing machine according to the respective To be able to change applications.

As a device for the practical implementation of the measures considered above is a memory required to store micro-operation sequences. The device used as such a memory is currently usually referred to as read-only memory or non-destructively readable read-only memory. In each case, a memory is assumed, the memory content of which has been handled by a programmer, but usually cannot be changed by the machine. In the following this memory can also be designated by the abbreviation "ROM".

In the simplest utilization of one working with a memory of the type mentioned above Control element, each bit of a word is used to define a micro-operation. With consideration on the fact that up to several hundred micro-operations are often used in a computer, thus, a large and expensive memory is required.

It is already known to reduce the storage capacity required in the context considered above. In this way, the micro-operations can be divided into groups, and the memory bits can also be determined which represent the elements of each group in coded form. Accordingly, for a group of M micro-operations, B bits are sufficient for M <> 2 ^B - 1. However, this is associated with a limitation in that only one micro-operation of a group can occur in a given word. This restriction thus stipulates that the minimum number of groups must be at least equal to the number of micro-operations in the respective word which comprises the highest number of micro-operations. Using this scheme, the memory bit requirement can normally be reduced so that two to three micro-operations per bit can be obtained.

The disadvantage of group formation in the manner considered above is the requirement that the micro-operations of a group are mutually exclusive on a word basis. Through this the possibility of being able to change the respective microprogram as desired without the having to rewire the decoder provided in each case.

The invention is based on the object of showing a way of how a control element of the initially is to be trained in order to make better use of the storage capacity of the existing To be able to put together memory micro-operation control signals in each desired sequence.

The above-mentioned object is achieved with a control element of the type mentioned at the beginning according to the invention in that to expand the interpretation of the microinstruction words said Control devices contain a Gfuppensteuerregister, which via a link arrangement is connected to a first register area of the output register in such a way that it is clear of this register area receives a group of bits forming a first part of the respective microinstruction word, that the linking arrangement is controlled by a command the relevant first part of the respective Introducing the microinstruction word into the group control register allows a first decoder to the group of bits stored in the group control register to produce a plurality of Control signals responds and that a second decoder with a variety of circuit arrangements a second register area of the output register is connected in such a way that these circuit arrangements take a large number of bits from this register area of the output register that form a second part of the same or another microinstruction temporarily stored in this output register represent, and with these bits selectively one by the output from the first decoder Control signals generate specified micro-operations from a plurality of micro-operations. Through this there is the advantage that, in a relatively simple manner, one much larger bit can be obtained from each of the occurring bits Number of micro-operation control signals can be put together than has previously been possible was. It is also advantageous that the composition of the micro-operation control signals emitted in each case changed in a relatively simple manner according to the respective requirements can be.

In the following an embodiment of the invention is described with reference to the drawings.

1 shows a simplified overall block diagram an electronic data processing system;

Fig. 2 shows a block diagram of a ROM control element according to an embodiment of the invention;

F i g. FIG. 3 schematically shows an adaptive coding circuit according to an exemplary embodiment of FIG Invention.

Fig. 1 shows the main parts in a block diagram of an electronic data processing system, showing the use of a ROM control element. All operations in the arithmetic and logic element 10 take place under Control of the ROM control element 11. For memory operations are in the arithmetic and logic element 10 addresses and data formed in port registers, and then one Memory control device 12 from the memory

element 11 signals to a memory operation start. The memory 14 can have various assemblies that can be put into operation independently of one another

15 included. Is the one addressed module from the input / output processing device

16 is not used, the memory operation is under the control of the memory controller 12 continued. At some fixed points in time before data is output, the control element II rated in terms of the availability of data. At the appropriate time, the control gives Data into the computing and linking element 10.

Input-output commands are obtained from the memory 14 with the aid of the arithmetic and logic element 10 under the control of the control element 11 brought out and processed at the point in time at which the peripheral devices 13 can be switched on to initiate the transmission of data or other necessary information. At this point in time, the control element 11 outputs to the input-output processing device 16 Signals from, whereupon the processing device 16 begins to record the information that it is required by the computing link element 10. The data path for this transfer runs via the memory control circuit 12. Since both the input-output processing means 16 ate the computing and linking element 10 also requires such a data path, such a path stands for their data traffic available. This data traffic takes place asynchronously; he may, if necessary, too also be blocked at any time, e.g. B. when the input-output processing device 16 requires memory access for some already advanced peripheral operations. When the traffic has ended, the input-output operation can continue, namely under the control of the input-output processor 16.

A special embodiment of a ROM control unit is described in more detail below will. A block diagram of this control element is shown in FIG. A in Fig. 2 ROM memory 20 shown may contain bistable devices arranged in a rectangle; it is connected to an output register 21. The ROM memory 20 is a quick access memory with a storage capacity of e.g. B. 2000 words of 120 bits each. Register 21 is a one-word memory register, the cyclic with the ROM period duration as output register for addressed in the memory 20 Words works. Register 21 has 120 bits which are divided into four "fields". The first field 22 is connected to a group control register via gates 24 and 25 26 or connected to Zwcig address register 51 to 55. The group control register 26 is on Auxiliary memory register.

The field 22 is either via the gate 24 or via the gate 25 with the in the outputs of this Gutter connected registers. Some of the words contained in the ROM memory 20 assign a field 22 of identification bits for the group control register 26, while other words have bits for other control signals. These others Control signals are referred to as Zwciguclrcsscn, which are entered in the intermediate pressure register 51 to 55. You can also send signals for be additional micro-operations; they can moreover in a certain way or as a function are decoded by the identification bits in the register 26. In the illustrated embodiment

the first field 22 contains twelve bits which are generated by a micro-operation controlling the gates 24 and 25 in suitable storage facilities are introduced. The gates 24 and 25 are for purposes of illustration as single-connection clcmcntc shown. It should, however

ι «can be seen that the memory content of field 22 of the output register 21 in parallel via GaUcrcircuits or other conventional circuits for such purposes is delivered.

The second field 29 comprises 26 bits; it is with one Test connection or test logic circuit 30 connected. Depending on the micro-operations to be performed, the bits in field 29 control the Checking of selected states in the central processing device. The results of this

Verification will be used to determine the microprogram interconnection used.

The third Fclü 31 comprises 52 bits; it is to one Group decoder 32 connected, which acts as the switch mentioned above, and these bits from one Group of micro-operations to another group

convicted. In this embodiment, the output of the group decoder 32 controls signaling devices 34 and thus 234 micro-operations.

The fourth field 35 comprises 30 bits; its output is connected to a fixed decoder 36 which an output device 37 controls and thus 48 micro-operations.

The bits in the group control register 26 are determined by the decoder or group control decoder 38

contained logic circuits are decoded. The output of the input control unit 38 is to the Group decoder 32 connected to in this a transition of the bits of the field 31 from a Group of microprograms on top of another

Effect group.

The ROM memory 20 is adrcssicri by a ROM address register 40; controlled. A starting address is normally transferred from the main memory to the via an input terminal 41

Address register 40 entered. Further addresses are obtained by the content of the address register is increased with the aid of a stepping device 42. The branch addresses are also common necessary; they are stored in the aforementioned five branch registers 51 to 5Ji.

From your field 29 a command »Branch in Memory test «issued in order to operate the intermediate control 45. A priority or priority combination circuit 47 connects line flip

Flops 46 with die 45. One Connection training 30 is to be given to the management Flip-flops 46 connected; it is used in the line flip-flops 46 contained bistable Einrich Depending on the test results,

Oo put. When a command "Branch in memory test" is given, the bistable devices of the conduction Flip-flops 46 scanned. The first set bistable " Establishment in the priority order causes the submission of the output signal of the corresponding

f'5 branch address register to the ROM address register sler 40 down. Will none of the bistable Einrichlungci is set, there is no real branching, and clii The address for the next ROM cycle is given by di <

raised address formed. Is one of the bistable devices is set, the corresponding branch address is entered directly into the ROM address register 40, and the stepping device 42 is disabled.

The operation of the one shown in FIG ROM control begins with one of the Main memory ah the terminal 41 for input of the address delivered to the ROM address register 40. This start address represents the result of the instructions programmed into main memory. The address in register 40 selects a word in ROM which in turn will be in the output register 21 is directed.

In most microprogram sequences, the first word in each case has the group control identification bits field 22. This fact is indicated by bits appearing in field 35, and one of the Micro-operations that can be triggered by the device 37 are used to determine the content of the field 22 ao to the group control register 26 to be transmitted. The group control register 26 effects short-term storage of the bits supplied to it until another word containing group control identification bits in register 21 has been entered. as

In the embodiment described, only twelve groups are required. Since with help 16 different code combinations can be represented by four bits, the four bits are sufficient completely. In the embodiment described, however, a 12-bit Fcld is used because this Field for the branch addresses is required. By storing the identification bits in register 26 and through Use of these bits for a sequence is the field 22 for the inclusion of branch addresses in the other words in the sequence freely. With the help of a 12-bit field, only one bit needs to go through a binary "1" can be formed to denote the groups effect control decoding. This simplifies the logic circuit.

The content of the group tracking register 26 is decoded by the group control coder 38. at In the embodiment described, the decoder 38 has a total of <> 7 decode outputs. This 97 outputs are activated in different combinations, depending on the "1" bits in the field 22. The Stcucrdccodertcilc the decoder 38 are connected to a network of gate circuits connected in the (iruppendecoder 32, which Input signal from the field 31 of the output register 21 are supplied. If there is one Identifier bits in the word contained in field 22 can also be formed in field 31 using binary characters "0" Bits included. In the specific embodiment assumed to explain an example represent all the micro-operations encompassed by a single word to be performed simultaneously Operations. In the event that »this is not required, the circuit and Assemblies. As a result, those for the sequence control are then designated by a single word Operations required clock control circuits are no longer required.

Most microprogram successions begin with preliminary microoperations to pick up addresses and transferring words from the main memory to registers of a computing unit. With this one considered embodiment, these preliminary micro-operations are all in field 35 of the ROM word denotes Da normally not to carry out any further micro-operations at the same time are, there are none in field 31 Commands.

Although in the above consideration all Problems related to the delay in transferring identification bits to register 26 and the following class combinations have not been taken into account, it has been shown that such Problems do not limit the applicability of the invention. at of the embodiment considered for the purpose of explaining the invention stands at a ROM cycle of 125 nano-seconds sufficient time is available to be used by the signaling devices 34 to trigger microprograms during the cycle in which the register 26 identification bits can be supplied. To prevent ambiguity from occurring, it is necessary to either to delay the micro-operations 34 until the contents of the register 26 are changed or clear the register 26 by a micro-operation of the previous word.

In the embodiment of the invention considered here, at the end of the ROM cycle, in to which the first word of the microprogram sequence was read, the following states exist: a first Group of preliminary micro-operations has been carried out by the fixed decoder 36; Are identification bits entered into register 26 and decoded by decoder 38; the content of the address register 40 has been increased. At the beginning of the next ROM cycle, due to the increased address, there is a new ROM word in the output register 21 available.

This new word generally triggers additional micro-operations specified by field 35 as well Micro-operations that are triggered by the combination of field 31 and the state of group decoder 32 are determined. The field 22 of the new word may contain a ROM address. This address denotes a branch to a new microprogram sequence that still has a service may require. The gate 25 transfers the branch address from the IcIcI 22 to one of the five Zwcigadrcsscnrcgistcr. After the occurrence of the second word starts processing. The results that arise produce results that Audit operations to determine whether a branch sequence of microoperations is required is. This is how it is in binary computing /. B. sometimes required different operations to be carried out when carry-overs occur, as opposed to operations in which no Carryover occurs.

The bits contained in the field 29 actuate the test logic circuits 30 in order to determine properties such as the presence or absence of transmissions. The test results are used to set the line flip-flops 46. Certain words in a microprogram sequence are often followed by a branch. These words contain a branch instruction which causes the status of the conduction flip-flops 46 to be checked. In the embodiment of the invention explained here, the bistable elements of the line flip-flops 46 are checked in their order of priority, ie 1-2-3 etc. The branch

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control device 45 transmits the memory contents of the Branch registers 51 to 55 in the ROM address register corresponding to the longest "set" bistable Element. This: two-way address creates a word in a branching microprogram sequence. The new microprogram sequence is executed as long as until another branch instruction occurs or the end of the microprogram is reached.

The adaptive decoding system is shown in more detail in FIG. As far as possible, they are the same in FIG. 3 Reference symbols used as in Fig. 2. That Output register 21 and group control register 26 are shown in block form, with individual lines illustrate the respective bit readout process. The twelve bits of field 22 are through the first twelve letters of the alphabet in the register 26 designated. As already stated above, these twelve bits are used because they are available. This means that the field 22 at many, but not all, of the words needed to provide twelve bits for branch addresses will. With execution of a computer program in the plant put the words in which it is desired is to provide group control flags, words in which branch addresses are unnecessary. With many of these readily available twelve bits, four bits would be an enormous amount for the present embodiment used adaptive decoding system to provide 16 different output signals.

The group control decoder 38 effects a grouping of the outputs of the via OR circuits Registers 26 in 85 groups. This is required because there are many micro-operations in many different Microprogram sequences occur together. Although the 85 starting groups are not all possible Represent OR groupings, this number of groupings is sufficient to open the door to achieve the required versatility in each application. In this system it was not necessary combine more than five identification bits using OR circuits. Dn the actual link validation is too complex to represent in the present context, this is shown in the drawing only indicated by link symbols.

The outputs A and Ii of the register 26 are combined via a gate 60 which acts as an ODHR-Ciattei and which is followed by an amplifier 61, at the output of which the group control decoding signal / 1 / ί occurs. The outputs J and / are correspondingly. of the register 26 via an OR gate 63 / u:,; inimuiget'asst, to which an amplifier 64 is niichgcordncl. At the output of this amplifier appears ilns Gruppunstcuur-Dccodicrsignul JL . A ODI'R-Outlcr 67 summarizes the / l / i-Dccodcrsignal and one y /.- DcciKliersigiuil together with the output on I) of the register 26 signal occurring together at the output of the OR Gatler 67 nacligesclialleten amplifier 68 thus enters the 5 -Bit decoding signal AIiI) JL on.

The field 31 of the output register 21 supplies 52 non-decoding output signals which are fed directly to the group decoder 32. The mentioned 52 output signals are each fed directly to AND gate tern in the group decoder 32. Every exit

The output signal of the field 31 is fed to a plurality of AND gates, each of which triggers a Mikroppe ration. The respective other input of the AND gate receives a signal from register 26 either directly or in decoded form.

In the embodiment under consideration, there are 234 AND gates, each with an amplifier connected downstream intended. These AND gates provide the control signals for 234 micro-operations. Two of these Gates are shown in your link diagram.

ίο Displaying a number of gates beyond this would be impractical for the present purpose. The AND gate 70 with the downstream amplifier 71 is connected with one input to the output line of the group control decoder 38 carrying the group control decoding signal AB and with its other input via a line 73 to the output of the output register 21 associated with the bit position 39 in the field 31 . The sub-command occurs at the output of amplifier 71

If the bit position 39 of register. 21 contains a binary character “1” and either A or B in register 26 is formed by a binary character “1”, the Λ register is received It should be understood that several outputs of the group control decoder 38 are connected to more than one gate of the group decoder 32. The field 35 of the output register 21 has, as indicated, 30 bits;

<to gen connected to the fixed decoder 36. This solid Decoding has heretofore been used in known systems. This is for the one described above adaptive decoding is not essential. Apart from the example of the indicated in the drawing

fixed decoding, further explanation is not necessary for the purposes of the invention.

When using fixed decoding grouping, as in connection with field 35, it is expedient, the common in all episodes

so micro-operations comply with the predefined decoding signals assign. This takes some of the load off the group control decoder, and the maximum number of micro-operations that can be used in most workflows is reduced.

consequences occur for the adaptive decoder.

For this purpose 3 sheets of drawings

Claims (1)

Patent claims: 1. Control element for the generation of micro-operations with a read-only memory in which a plurality of microinstruction words is stored, each of which is made up of a plurality of Bits from which the micro-operations are derived, with control devices for Generation of prescribed micro-operations as a function of the micro-instruction words, with an output register in which the microinstruction words read out from the read-only memory be temporarily cached, and with access facilities for such access to the read-only memory that micro-operations to meet operational requirements in a prescribed sequence are generated, characterized in that for expansion the interpretation of the microinstruction words said control devices an ao Contain group control register (26), which via a logic arrangement (24) with a first register area (22) of the output register (21) is connected in such a way that it is from this register area (22) forming a group of a first as part of the respective microinstruction word Bits receives that the logic arrangement (24) controlled by a command the relevant the first part of the respective microinstruction word is allowed to be introduced into the group control register (26), that a first decoder (38) on the group of in the group control register (26) Stored bits responsive to generate a plurality of control signals and that a second decoder (32) with a plurality of circuit arrangements (70, 71, 75, 76) on one second register area (31) of the output register (21) is connected in such a way that these circuit arrangements (70, 71, 75, 76) from this register area (31) of the output register (21) take a plurality of bits, which a second Part of the same or a different microinstruction temporarily stored in this output register (21) represent, and with these bits selectively one by the output from the first decoder (38) Control signals specified micro-operation from a large number of micro-operations (34) produce. 2. Control element according to claim 1, characterized in that the decoder (38) is a system of OR circuits (60, 63, 67) each of which belongs to the first group of bits Bits are fed. 3. Control element according to claim 1 or 2, characterized in that for generating the Micro-operations switching devices (34) are provided, each of which contains an amplifier, that the switching devices (34) AND gates (70, 75) with two inputs and each post-register (21) contained bits of responsive fixed decoder (36) is provided, whose respective output Output signals define microoperations that are most common in microprogram sequences represent occurring operations. 5. Control element according to claim 4, characterized in that by combining the bits the first and second groups (22, 31) of bits define at least three times as many micro-operations are as indicated by bits in the third group of bits.