DE1816081A1 - Integrated semiconductor circuit arrangement - Google Patents
Integrated semiconductor circuit arrangementInfo
- Publication number
- DE1816081A1 DE1816081A1 DE19681816081 DE1816081A DE1816081A1 DE 1816081 A1 DE1816081 A1 DE 1816081A1 DE 19681816081 DE19681816081 DE 19681816081 DE 1816081 A DE1816081 A DE 1816081A DE 1816081 A1 DE1816081 A1 DE 1816081A1
- Authority
- DE
- Germany
- Prior art keywords
- zone
- transistor
- collector
- shaped area
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 102000004207 Neuropilin-1 Human genes 0.000 description 1
- 108090000772 Neuropilin-1 Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Description
SIEMENS AKTIENGESELLSCHAFT München 2, den Berlin und München Wittelsbacherplatz .2SIEMENS AKTIENGESELLSCHAFT München 2, the Berlin and Munich Wittelsbacherplatz .2
pa 68/3244pa 68/3244
Integrierte HalbleiterschaltungsanordnungIntegrated semiconductor circuit arrangement
Die Erfindung betrifft eine integrierte Halbleiterschaltungsanordnung mit komplementären Transistoren in einem einzigen Halbleitersubstrat, in dem einkristalline wannenförraige Bereiche eines ersten Leitungstyps durch Isolationsschichten von einem polykristallinen Trägerkörper getrennt sind.The invention relates to a semiconductor integrated circuit arrangement with complementary transistors in a single semiconductor substrate in which monocrystalline well-shaped areas of a first conductivity type are separated from a polycrystalline carrier body by insulation layers.
Es ist an sich bekannt, bei integrierten Halbleiterschaltungsanordnungen komplementäre, d.h. pnp- und npn-1'ransistoren in einem Halbleiterkörper- unterzubringen.It is known per se for integrated semiconductor circuit arrangements complementary, i.e. pnp and npn-1 'transistors in to accommodate a semiconductor body.
Dabei kann man beispielsweise von einem Substrat eines ersten Leitungstyps ausgehen und darauf eine epitaktische Schicht eines zviciten Leitungstyps aufbringen. Zur Bildung von npn-Transistoron können dann beispielsweise bei η-leitender epitaktischer Schicht nach Art eines Planartransistors eine p- und eine η-Zone vorgesehen v/erden. Yfeitcrhin kann in dem η-leitenden Substrat eine p-Zone eindiffundiert werden, wobei diese p-Zonc, die epitaktischo Schicht und das Substrat Emitter, Basis und Kollektor eines pnp-Transistors bilden. Eine derartige Ausbildung eines pnp-Transistors in oiiier integrierten Schaltung hat jedoch den Nachteil einer schaltungsraäßigen Beschränkung bei der Anwendung der integrierten Schaltung. In aller Regel liegt nämlich bei integrierten Schaltungen das Substrat elektrisch an Masse, so daß der pnp-Trans!Dtor, dessen Kollektor durch das Substrat gebildet v/ird9 in der Schaltung potontialmäßig nicht vollkommen frei zur Verfügung steht.In this case, one can, for example, start from a substrate of a first conductivity type and apply an epitaxial layer of a second conductivity type thereon. In order to form npn transistors, for example in the case of an η-conducting epitaxial layer in the manner of a planar transistor, a p- and an η-zone can be provided. A p-zone can be diffused into the η-conductive substrate, this p-zone, the epitaxial layer and the substrate forming the emitter, base and collector of a pnp transistor. Such a design of a pnp transistor in an integrated circuit, however, has the disadvantage of a circuit limitation in the use of the integrated circuit. As a rule, the substrate is namely in integrated circuits electrically connected to ground, so that the pnp-Trans! Dtor whose collector formed by the substrate v / ith is not in the circuit 9 potontialmäßig completely freely available.
Es ist weiterhin bekannt, in integrierten Schaltungen pnp-Transistoron als sogenannte laterale Transistoren auszubilden. Dabei werden beispielsweise, in einer auf einem Substrat vorgesehenen epitaktischon Schicht eines Leitungstyps zwei ZonenIt is also known to use pnp transistor in integrated circuits to be designed as so-called lateral transistors. In this case, for example, in a provided on a substrate epitaxial layer of one conductivity type two zones
PA 9/493/928bPA 9/493 / 928b
1a·1968 "sm/me 1a · 1968 "sm / me
dos anderen Leitungstyps nebeneinander angeordnet, die als . Kollektor und Emit tor· des Transistors wirken, während der zwischen diesen beiden Zonen verbleibende Teil der epitaktischen Schicht die Basis darstellt. Derartige Transistoren 'besitzen den Nachteil, daß ihre Stromverstärkung sehr kleindos other line types arranged side by side, which are called. Collector and Emit tor · of the transistor act during the The part of the epitaxial layer remaining between these two zones forms the base. Such transistors 'Have the disadvantage that their current gain is very small
Eine weitere bekannte Möglichkeit pnp-Transistören zusammen mit npn-Transistoren in einer integrierten Schaltung auszubilden, besteht darin, in einer auf einem Substrat befindlichen epitaktischen Schicht neben einer npn-Zonenfolge eine pnp-Zonenfolgc in Planarbauweise anzuordnen. Bei Verwendung der gleichen Diffusionsschritte für beide Zonenfolgen haben die hergestellten Transistoren keine optimalen Daten. Bei Verwendung getrennter Diffusionen für beide Zonenfolgen sind zu viele Diffusionsschritte notwendig. Another known possibility pnp transistors together with to form npn transistors in an integrated circuit, consists in an epitaxial layer located on a substrate, in addition to an npn zone sequence, a pnp zone sequence to be arranged in planar construction. When using the same diffusion steps for both zone sequences, the produced Transistors do not have optimal data. If separate diffusions are used for both zone sequences, too many diffusion steps are necessary.
Der vorliegenden Erfindung liegt die Aufgabe zugrunde, eine integrierte Haibleitorschaltungsanordnung anzugeben, bei der die vorgenannten Nachteile bekannter Anordnungen vermieden werden.The present invention is based on the object of specifying an integrated semiconductor circuit arrangement in which the the aforementioned disadvantages of known arrangements can be avoided.
Zur Lösung dieser Aufgabe ist bei einer integrierten Halbleiterschaltungsanordnung der eingangs genannten Art vorgesehen, daß im unteren Teil eines ersten wannenförmigen Bereichs eine den Kolloktor eines Transistors einer ersten Zonenfolge bildende Zone des zweiten Leitungstyps vorgesehen ist, welche sich an einer Seite bis zur Oberfläche des ersten wannenförmigen Bereiches erstrockt, daß an der Oberseite des ersten wannenförmigon Bereiches eine weitere, den Emitter eines Transistors der ersten Zonenfolgo bildende Zone des zweiten Leitungstyps ^i vorgesehen ist, wobei die zwischen den Zonen des zweiten Leitungstyps liegende Zone des ersten Leitungstyps die Basis eines Transistors dor ersten Zonenfolgo bildet, daß in einem zweiten wannenförmigen Bereich des ersten Leitungstyps zwei ineinander geschachtelte Zonen des ersten und zwoiton Leitungstyps vorgesehen sind, welche Emitter und Basis eines Transistors einer zwoiton Zonenfolge bilden, wobei dio ver-This object is achieved in the case of an integrated semiconductor circuit arrangement of the type mentioned provided that in the lower part of a first trough-shaped area a Collocator of a transistor of a first zone sequence forming zone of the second conductivity type is provided, which on one side to the surface of the first tub-shaped area dried up that on the top of the first tub-shaped Area another zone of the second conductivity type forming the emitter of a transistor of the first zone sequence is provided, the zone of the first conductivity type lying between the zones of the second conductivity type being the base of a transistor dor the first zone sequence that in a second trough-shaped region of the first conductivity type two nested zones of the first and two-tone conduction type are provided, which emitter and base of a transistor form a two-tone zone sequence, with dio
- 3 — 009826/1240 - 3 - 009826/1240
BAD ORIGINALBATH ORIGINAL
PA 9/493/928b - ? - .PA 9/493 / 928b -? -.
bleibende Zone des zweiten wannenförmigen Bereichs den Kollektor eines Transistors der zweiten Zonenfolge bildet.remaining zone of the second trough-shaped area Forms collector of a transistor of the second zone sequence.
Weitere Merkmale und Einzelheiten der Erfindung ergeben sich aus der nachfolgenden Beschreibung eines Ausführungsbeispiels anhand der Figuren»Further features and details of the invention emerge from the following description of an exemplary embodiment based on the figures »
Eine erfindungsgemäße Halbleiterschal tungs anordnung wird im folgenden anhand ihrer in den Figuren 1 bis 4 dargestellten Herstellungsschritte beschrieben.A semiconductor circuit arrangement according to the invention is illustrated below with reference to it in FIGS Manufacturing steps described.
Gemäß Fig. 1 geht man von einem beispielsweise n-leitenden Silicium-Blnkristall 200 aus, in den durch maskierte Diffusion eine η -Zone 5 und eine ρ -Zone 10 erzeugt wird. Der Einfachheit halber ist die maskierende Oxidschicht in Fig. 1 nicht mit dargestellt.According to FIG. 1, an n-type silicon single crystal 200 is assumed, for example, into which diffusion is masked an η zone 5 and a ρ zone 10 is generated. Of simplicity For the sake of this, the masking oxide layer is not shown in FIG. 1.
Gemäß Fig. 2 wird im Halbleiterkörper 200 in der dargestellten Weise eine Grabenstruktur geazt und auf dieser geäzten Struktur eine Silieiumdioxidschicht 6,7 abgeschieden. Auf diesem Oxid wird polykristallincs Silicium niedergeschlagen und der nleitende Ausgangskristall längs der Ebene II - II in Fig. 2, beispielsweise durch Polieren entfernt.According to FIG. 2, a trench structure is etched in the manner shown in the semiconductor body 200 and a silicon dioxide layer 6, 7 is deposited on this etched structure. Polycrystalline silicon is deposited on this oxide and the conductive starting crystal is removed along the plane II-II in FIG. 2, for example by polishing.
Dadurch entsteht die in Fig. 3 dargestellte Struktur, bei der in einem polykristallinem Trägerkörper 100 zwei wannenförmige, durch Isolationsschichten 6 und 7 vom polykristallinen Material getrennte Bereiche vorhanden sind. Im unteren Teil der linken Wanne ist dabei die η -Schicht 5 vorgesehen, während sich in der rechten Wanne die ρ -Schicht 10 befindet.This creates the structure shown in FIG. 3 , in which two trough-shaped areas separated from the polycrystalline material by insulation layers 6 and 7 are present in a polycrystalline carrier body 100. The η layer 5 is provided in the lower part of the left tub, while the ρ layer 10 is located in the right tub.
Gemäß Fig. 4. können in den wannenförmigen Bereichen nun zueinander komplementäre Transistoren ausgebildet werden. Durch aufeinanderfolgende an sich bekannte Diffusionsschritte wird dabei in der linken Wanne ein npn-Transistor 1, 2, 3 gebildet, während in der rechten Wanne ein pnp-Transistor 8, 9, TO gebildet wird. In entsprechende Fenster einer Oxidschicht 21 wird Kontaktmaterial, beispielsweise Aluminium, gedampft, wodurchAccording to FIG. 4, transistors which are complementary to one another can now be formed in the trough-shaped regions. By successive diffusion steps known per se, an npn transistor 1, 2, 3 is formed in the left well, while a pnp transistor 8, 9, TO is formed in the right well. Contact material, for example aluminum, is vaporized in corresponding windows of an oxide layer 21, as a result of which
009826/me - 4 -009826 / me - 4 -
PA 9/493/928b - 4 -PA 9/493 / 928b - 4 -
dio entsprechenden Kontakte - 11, 12, 13 und für den Transistor 1, 2, 3 und 18, 20, 21 für den Transistor 8, 9, "10 entstehen. Unter dem Kollektorkontakt 13 des npn-Transistors 1, 2, 3 ist eine hochdotierte n-Zone 4 vorgesehen, welche zur Vorbesserung der ohmschen Eigenschaften dieses Kontakts dient. Entsprechend ist auch unter dem Bcsiskontakt 21 des Transistors 8, 9, 10 eine hochdotierte n~Zone 19 vorgesehen.dio corresponding contacts - 11, 12, 13 and for the transistor 1, 2, 3 and 18, 20, 21 for the transistor 8, 9, "10 arise. A highly doped n-zone 4 is provided under the collector contact 13 of the npn transistor 1, 2, 3, which serves to improve the ohmic properties of this contact. Correspondingly is also under the Bcsiskontakt 21 des Transistor 8, 9, 10 a highly doped n ~ zone 19 is provided.
Beim npn-Transistor 1, 2, 3 wirkt die n+-Zono 5 als "burriedlayer"-Schicht, welche in an sich bekannter Weise den Kollektorbahnwideretand des Transistors verbessert.In the case of the npn transistor 1, 2, 3, the n + zone 5 acts as a "buried layer" layer, which improves the collector track resistance of the transistor in a manner known per se.
2 Patentansprüche
4 Figuren2 claims
4 figures
- 5 -009 8 26/1H6- 5 -009 8 26 / 1H6
Claims (1)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19681816081 DE1816081A1 (en) | 1968-12-20 | 1968-12-20 | Integrated semiconductor circuit arrangement |
| NL6915025A NL6915025A (en) | 1968-12-20 | 1969-10-03 | |
| CH1869969A CH504110A (en) | 1968-12-20 | 1969-12-16 | Integrated semiconductor circuit |
| FR6943697A FR2026660A1 (en) | 1968-12-20 | 1969-12-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19681816081 DE1816081A1 (en) | 1968-12-20 | 1968-12-20 | Integrated semiconductor circuit arrangement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE1816081A1 true DE1816081A1 (en) | 1970-06-25 |
Family
ID=5716944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19681816081 Pending DE1816081A1 (en) | 1968-12-20 | 1968-12-20 | Integrated semiconductor circuit arrangement |
Country Status (4)
| Country | Link |
|---|---|
| CH (1) | CH504110A (en) |
| DE (1) | DE1816081A1 (en) |
| FR (1) | FR2026660A1 (en) |
| NL (1) | NL6915025A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4232328A (en) * | 1978-12-20 | 1980-11-04 | Bell Telephone Laboratories, Incorporated | Dielectrically-isolated integrated circuit complementary transistors for high voltage use |
-
1968
- 1968-12-20 DE DE19681816081 patent/DE1816081A1/en active Pending
-
1969
- 1969-10-03 NL NL6915025A patent/NL6915025A/xx unknown
- 1969-12-16 CH CH1869969A patent/CH504110A/en not_active IP Right Cessation
- 1969-12-17 FR FR6943697A patent/FR2026660A1/fr not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| CH504110A (en) | 1971-02-28 |
| NL6915025A (en) | 1970-06-23 |
| FR2026660A1 (en) | 1970-09-18 |
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