DE1801215C - Associative memory - Google Patents

Description

60

) \ c The invention relates to an associative memory with a multi-digit input register. which has a word and a password memory part and includes comparison devices for comparing the data age of one or more columns of the input key with the positions of the password and / or word memory part, each memory being set up in such a way that it receives a correspondence signa! generated when the compared data bits in the password and / or data word memory part match the corresponding bits in the input register and in which an output register is coupled to the input register.

An associative memory for storing digital data differs from a conventional memory in that, in a conventional memory, a data word is addressed by specifying the memory location in which the word is to be found. whereas a data word is addressed in an associative memory by specifying at least part of the memory location content. If z. B. d ^; e words in an associative memory consist of account numbers and account balances, the word containing the account balance can be read out and brought up to date by specifying the account number for this account number. On the other hand, if it is assumed that the account balances are signed, then through. Specification of a negative sign, e.g. B. all data words are read out, which relate to accounts mi ;. Relate target stock. For the sake of simplicity :; the data such as code number or negative sign that are used to identify a word to be read out, referred to below as Kennwon. Such an associative memory is ζ. Β described in the Taschenbuch der Nachrichtenverarbeitung \ oi: K. S tci π buch on p. 653.

In the usual form of associative memory, the password is set in the bit positions of an input register which correspond to the bit positions ci_passwords in the data words in the memory, and the password and data words are compared with one another. A mask record ensures that the comparison is only made between certain image positions of the input register ur. i such the data takes place. These data words. the " corresponding bit positions", agree with the characteristic value, are marked and an output register is read out afterwards.

To mark the words selected for reading, it is common practice to use a bistable toggle circuit associated with the memory location 1- ' which contains the selected word in a correspondingly predetermined stable state. The setting of this bistable multivibrator is used afterwards to control a read or write signal on the memory location marked in this way !. So far it has been customary to have only one such bistable To provide a flip-flop so that only one write or read cycle could take place.

When an associative memory in a data processing system z. B. use as ßefehlsspeicher; becomes, and in it thus commands of a main pro gramms and commands of subroutines or microprograms are stored, had to be with the previously known associative memories with only one toggle switch to display the agreement of the Where content with the search term or part of it after each command has been processed in both the main program and the microprogram a complete new search can be initiated to look for the next instruction in memory and read out. The address of the next command to be read out was in each case in a part of the previous command.

With this solution I had to for each command

_f in full search and a read ahead a-.v. ''Itattfindcn. However, this method, caused by the structure of the memory, required a great deal of time to process long programs that were only used to search for commands and to load them into them. A '.! -! -'- enütiüi vurde of commands found. Ineffective operations since a data processing system equipped with such a spoke. is thereby considerably reducedee-e;, · ;.

The preamble therefore lies to the inception /.iiaruiide. _K tinen.-Vo / iativspeicher to sound the NKt-: erun- , _{en U} i; i entered data mi e!: M '- !: ch ;. that when writing L- or Heim v, u-, p. _; :.; ' , _{ι: ι} ^ _{,; _ m} spoke or in the Speieher only. · ■: ·, -ü-iimie. / u a ('tuppe belonging data ap.uc ^ r-roelvjM wviden. ι-

Qie. ■ in accordance with L (Kuhü ..!;. ■■ Au:.:. ^ K "e -;, - H in it. ■ '^ -' every Kcnnwon- im ::, '.. ■';.;., ■;.: ··, ■■■ - ··. Speieiu: '- il with a multitude of :. ■;. ■ K ·, ■■ <;■■■>: ■■■■. ■: ■ ■ .-, - pen ur.- ^; -'a multitude of second Ku «; · -:, .. ;;;:;:;. ·; .. ·: - bund-. ·" · ■ - ■ · ^l -i ^'s eingangsseilig uK: · i u _.:;■:.· · · · · · Won-- -Hing and Deco · ^1; ■ · - _·;, ■...... -,

Stcui.:'-'~ ^{>! Jr} \ erbunden are ur.c. '.-. v. \ . ..,; :., · ;; vom - '^ ü'-th Überemstimmu'.iu --- ¹ . ■ - ,.: ■ .... ■. · -, ·; | _n ha !: '- ^ tax register including;: -.,' · ■■ .: ■ ■ · .-. ^! ·.; ,, - Tilt ·. ¹ :! Values of neighboring v · -. _: ·. ·, ._ ..-.!; _; each · ¹ - - ■: '■ · -' line for controlling π ■.; . ·. '"..- · ■■■■:. ·.; .. because · -es Kippschahungspa;:;. -. · ■■ ' ■, '■■'■>.;>..; ■ from /'.:and of the previous!: ·.: .- ■■. ■; ■■■ '.,; ■ - _: .. ·.-pairs; - are tied.

In.-In execution examples: 1:. \ .., · ■ · _: ·. . · -. ·. rather- · each word memory mi; . '. _; . ·; ■ .. ■ ..:; : -i stabi ':. · Storage devices ; ·: -:'<]<■) ■ :: -:,: bund.; ·, those with the first Kippscli.ii "'.:! ..- :: - / .-. ■ ·. · - ■■.; · ..- Kjpp · .. '!.! Blades are labeled.

Di-. . Execution turns out to be ί ^ - ·· · ■. . ·?> · ■: -.;!> ■ h; .!. i _ne ·· Development of lists \ -ί ... ■■ · ■;.. ■, _:); · Η-words ";.-'.'- ie machine instru!; '.:! ·; ^; -:'-; ■,. 1;:. ··. B. the A -; -. ' ssation of instruction ^ -.-. o ¹ ':; i ,. / i: iii Hau; - ·'.;"ürarnm belong, by l;:; M..iL :. >', r first K: pr-chaltungt: n controlled v. . · =.! .- ■: :: ;;. ': D: e address ---; eruns; of instruction wori. ;:. Ji. ; ■: ·. L'p.ie;"-rüLiin:; belong, can be controlled by Γ.ι ^ κ'Ί '. ::., · Tier /w.ii-:■ Tilting · iialiungen.

\\ .- i; i one of the selection tipsehaii ^ iiüen ü> -.e! / '. i.-t. can .n; Access for a reading or viewing ration ^ u i;.: ü /. belonging word spoke '· eiiolgen. Every Kipp ^ e'ultung can optionally be set to to / .eiiien that the data content a ·; Word spreader, identifier queried with d> .ni for a search operation word matches. In addition, however, depending on the action of the selection device ·; !! one of the Selection flip-flops of an adjacent word memory are set when the other word memory generates a match signal. The associative memory is arranged to be optional the switching state of the selection toggle switches that are assigned to certain word memories corresponding selection flip-flops of neighboring Word memory is able to transfer.

The invention is explained in more detail below on the basis of exemplary embodiments and the drawings explained. It shows

Fig. 1 is a schematic representation of an inventive Associative memory,

Fig. 2 is a circuit diagram of a data storage cell which is suitable for use in such an associative memory,

FIG. 3 shows a schematic representation of a bit N <: haluing6 as it is used in the FIG. 1 shown memory is used.

F i ■ · '4 a schematic representation of a mask circuit 5. as used in the storage device shown in FIG. 1, and

Fi ii. 5 is a schematic representation of a progression 15. As shown in the in Fig. 1 is used.

The associative memory shown in FIG. 1 contains a scanning memory 2 with a number of scanning memory cells 3. A mask register 4 with the large number of mask circuits 5 as there are memory cells in the scanning memory, for each mask position a bit circuit 6 =. several word memories 7, each of which contains as many data memories / lines as there are bit circuits in front of it. Mild, and finally an output register with the corresponding wizah! of output memory cells 10. The memory ■ "consists, so to speak, of" several columns, each of which is a binary memory line 3. a mask circuit. a bit storage unit 6, a binary output memory / elle IU and / between the last two-named contains as many data memories as word memories 7 are present. The elements of each column are connected via bit lines 11 and 12, which are designated with zero and one allocation, respectively. When the zero bit line Π is marked. a binary zero is transmitted on the bit line and ■■■ if the one-bit line 12 is marked. a binary one ?. As will be explained in more detail below, these bit lines have the triple function of the input-output query. and the marking is different according to the function. In Fig. 1, only dif- a cst flip-flop 16 and a second flip-flop 17 contains.

As shown in Fig. 1, the operation is of the associative memory controlled by the content of a separate, multi-digit control register 18 ) 5 of their output signal through a decoding circuit: 19 is analyzed, which then generates control signals on lines 20 to 26 and 73, which the connections between the decoding circuit 19. the mask tester 4, the bit circuits 6 and the word Establish circuit 15. Data are transmitted to the memory via input line 27 gen, which is also connected to the control register 18 via a branch 27 ″, as well as from the memory away via the international trunk line 28, the exit of which branch 28λ with the input manifold 27 ver

is bound. . .

In the case of the I i g. 1 shown Ausführungsbeispie

is the control register 18 of the input register 2 ge

separates arranged, which means that the spoke

externally ^ is controlled. Each W01 to be processed

however, it can also contain a control field, which

those on the dates of the word including de

The control field determines the operation to be performed and the memory from an external control unit makes you pending.

In an associative memory, a data memory cell 8 must be able to indicate whether the data content de Ze ¹ Ie corresponds to a binary value oac

not, which is represented by an interrogation signal. that does not interfere with the data content. Associative cells with such properties are well known and consist for example of transistor circuits, Kryotron * or magnetic cores. Any known associative cell can be used for the data storage cell 8 will.

The in F i g. The data storage cell 8 shown in 2 is a tristable transistor circuit made up of two bistable circuits with the cross-coupled transistors 71 and 7'2 or 7 3 and 7 4. The transistors T1 and 74 are double-semiconductor transistors. Each stable state of the circuit is defined by the fact that one of the transistors in the two bistable circuits is conductive. In the memory shown in FIG. 1, three of the four possible stable states are used: if the transistors 71 and 73 are conductive, the cell stores a binary zero, if the transistors 7'2 and 74 are conductive, the cell stores a binary Hin , and when the transistors T1 and 73 are conductive, the cell is in a stable state, which is called the ^ state. In order to interrogate the cell without changing its content, predetermined voltages are applied to the bit lines 11 and 12 (FIG. 1) by the bit circuit 6 explained in more detail in FIG. 3.

In order to query the one-state, a relative becomes a uezugspoieiiiial. l. B. earth, high voltage, put on the zero bit line Π and a low voltage on the Hins bit line 12. When the transistor 74 is conductive, the current is therefore directed through the emitter £ 41 to the one bit line 12 and over practically no current flows into the word emitter line 14 from the emitter E 42. When the transistor 71 is conductive, the current is conducted through the emitter E 12 to the word emitter line 14 because of the relatively high voltage on the zero bit line 11. It follows that no current will appear on line 14 and thus a match will be indicated if a binary one is stored in the data line. In contrast, a current appears on the word averaging line 14 and thus does not indicate a match if a binary zero is stored in the data line.

The query for the zero state is carried out analogously by applying a high voltage to the one bit 12 and a low voltage to the zero bit definition II. As with the query on the One state then no current appears on the word emitter line 14. If a binary one in the cell Zero is stored, indicating a match. On the other hand, shows a current on the word emitter line 14 no match. if the cell contains a binary one.

An important feature of the data storage cell shown in Fig. 2 is the response to the query to one or zero if the cell is in the X state. The transistors 72 and are in the ^ state 73 conductive and no current appears on line 14 regardless of the interrogation signal. In this state the answer to an interrogation is therefore in any case an overtiming signal. This feature provides great flexibility in the use of an associative memory of the type described, since in known associative memory cells with only two memory states the position of each is queried Zciic is significant for determining the outcome of the loss.

Because the data memory cells can assume the Z state, e.g. B. the simultaneous query different fields in different words possible, which allows a detailed table search and similar evaluation methods are possible.

In order to read the content or the status of the data storage cells, the voltage on the word emitter line 14 is raised. Depending on whether the transistor 7Ί or 7'4 is conductive, current flows via ίο the emitter £ 11 or £ 41 to the zero bit line 12. If the cell is in the X state, no current appears on a bil line. In order to write to the data storage cell, the voltage on the word emitter line 14 is increased and the spants on the word collector line 13 are decreased. Voltages on the bit lines 11 and 12 with the same value as the interrogation voltage are sufficient under these conditions to switch the bistable signals. A high voltage on the bit line, for example, makes the transistor 71 non-conductive or keeps it in this state, whereas a low voltage makes or keeps it conductive.

The carry out in the described associative memory 1 The basic operations are as follows:

a) Choose primary, choose secondary

The binary values in the positions of the input register 2 which are not masked by the mask register 4 are compared with the binary values in the corresponding positions in all word memories 7. There is a match when a data memory cell 8 stores the same binary value as that corresponding input memory cell 3 or if the data memory cell 8 is in the .Y-Zusland. the Word emitter line 14 is for all data storage cells 8 of a word memory 7 together, so that a Niclu agreement in only one cell Word results in a "no match" display for the entire word. As in more detail below is described, each mask circuit 5 includes a bistable circuit. Called mask trigger, with the stable states one and zero. In the case of an elective operation, a comparison takes place only in those Set the worlspecichcr for which the mask trigger is in the state one. The wordspi "her. The emit a match signal, for which there is no current on the associated word emitter line 14 flows, set the first flip-flop 16 odci the second flip-flop 17 depending on whether the operation is a primary choice or a secondary choice.

b) Read primary, secondary read

The content of the word memory, its first or second flip-flop is set depending on the operation, is read out to the output register 9. Just the positions in the memory for which the mask trigger is set to zero are read out. If more than a first or / wide flip-flop is set the operation is effectively an OR operation in the output register for the content of those word memories, for which the trigger is set. The status of the first or second toggle switch is thereby not changed.

c) Write primary, secondary write

The content of the input register is read from the binary digits into the word memory for which the mask wearer is at zero, depending on the op-

r-tion for the the first or second flip-flop bit driver has two with the letters H and L.

S κ, 'D "S.;" - * -; ^ »-, κ, ΡΡ- Ä Ä

circuit is n.chl gL.md.rt. ^ _cjncr ^^ ^ _Bc7 _- _{voltage ho! len Spanmm,.}

d) Primarily select the next word memory. _{5 unc} ] _{wcnn e y n} input /, is switched on, st that

Read primary output signal of the associated bit driver on ci-

Secondary select the next V location. _{ner re} i _at i _v to the reference potential low voltage.

Secondary read if neither of the two inputs is switched on.

In the first part of this operation, each set is the output of each bit driver so large

ör second flip-flop reset and OK like the reference voltage. The inputs H and /. who-

ic second 'flip-flop de, the next one controlled via AND circuits 32 to 36

WorSchers set. The next word memory starts. Lines of the input signal for each of the LND

wonspeicners S "^" ¹ · store in a gcge circuits 32 to 35 is the output signal of the

defined as the bena.hbarJc Spe.chcr w a ^ gt, _OR . _s ^e _chahung 37, _the ihrerse.ts as inputs the

? cs ^ne n ⁿ äS5Sre WOn ⁸ S eiXe'rstng'e'sTa.tet and "signals on lines 23 and 24 received by the decoder, the connection between circuit 19 required for this purpose.

S hl 15 is schema Line 23 is energized when a Schre.bopera-

tion H 'is required and line 24 if a

TrtfaCfrnS dial operation 5 required, st. Line 24 dieni

Operation described primarily read or Se- 20 also as an input for the AND circuit 36.Sn i id most frequent De outputs Ua and 12a of an input memory

"He 3 2 l of Eingangsregistcrs, efcrn the other input signal for the l.ND Template obligations 32 b s ₃₆ L _eitun gij _{a) st} energized when the cell 3 is a rv.- _{nare aJ} ^ f ull stores and Line 12o. when it stores a binary one. The line 110 is connected as an input to the AND circuits 33 and 34 and via the inverter 38 to the UNL> -

κΤρΓΓηϊεπί is observed. D circuit 36. The line 12a is used as an input

nnw-rd d «after the currently selected won 30 to the AND circuits 32 and 35 and via the fn o t Tine application of this verter 39 connected to the AND circuit 36. the

- ^ outputs of the l ^ ND soundings 32 and 34 are mi

the corresponding inputs L of the B.tleirunes driver circuits 30 and 31 connected. The outputs of the AND circuits 33 and 35 are connected to the corresponding inputs // and the external

the necessary g

Sen adjacent word circuits 15 is schematic ! T control line 29 is shown. the

Stotelb ™ at the

wrote Operati

Sleeves This surgery is the most common S Run through a series of consecutive machine instructions used.

e) Switch primary. Switch secondary

tion is nrakisch identical to the above option _{and differs from JHSI 1} Mi now the setting of the Γϊ is observed. Through this

SSc word auteelescn
Read out the following word.

Instruction is the new Hu
e.nem instruction set.

^ _y . ^ _by ..π .. ..ζ g _a

f) Switch primary and set mask. Secondary switch and mask set Ooeration plcicht the previous Opew ^ t, ^ ^ result not on the

ration e). je oc ■ auseel'sen but in the

d Tn uS the file register copies. , 0, L Precision-n "incr bit circuit 6. If" S hd oll must

P, details

must be carried out

α nH · "". "11 and 12 7U the data storage

p «another ^ suitable

AND circuit 36 is connected to both inputs I. the bit driver.

A single mask circuit 5 of the Mask.er.re2i sters 4 _g in Fi. 4 shown. Each mask person contains a mask trigger 40, which determines !. whether the signals on the bit lines lift. 12A in front of the input register on the bit lines He. 12 «/ u bit circuit 6 should be transmitted or not

ration .S are executed v,! i. in which the cell is to be queried for the on-state or in a "write operation W emc binary one is to be fully written into the cell, the zero bit line must be switched on relatively high voltage" and the F- JnvBiticifun 12 relatively P ™ ^;? zuzspctential low voltage When the 7 / rlle to the zero state ^ ^ abeefraet in a vihlopet "™ S or at a.

a gg

If e, ne Wahlope- 45 The output 40a of the trigger 40. which is energized d d Zll f when the trigger is stable EiZd h

W a NuJt

when the trigger is at the stable one state, is connected as an input to the AND circuits 41, 42 and 43 and the other output of the trigger 40, which is energized. when the trigger is at the stable zero state, is connected as an input to the AND circuits 44 and 45. The zero bit line 116 from the input register 2 is connected as an input mi * to the AND circuits 43 and 45 "and the one-bit line 12 b from the input icaster 2 is

i: v to gp

and the one brotherhood ^ raised «Span-

■ l ZcH «- p-vhr.-txrn become -λ», d: e zero- 55 input must be connected to acn AND circuits 42 and 44; _t ,;,; 'j' · . _aui r, wi fclai: v tied to the reference potential. The selection bit 24 from the decoding switch- · "- '^ -''' - ^JJ - ^c: "^D; * '~ * ""' like 19 is as input5 with the AND circuits

42 and 43 allied !, the write ritune 23 as input W with the AND circuits 44 ″ and 45 and

D> through / ufbhien'k Opcr ^ .on w, rd through control 6c the line 21 as input /? , _n it the ÜVD-Schal- U- .. cww. κ. , " - _A _ rw ^ timg41. The outputs of AND loops 42 and

44 are al; Entrances with the O ^ ER-Shahun »46 sell. their output signal on d-r one-bit Ismmg 12 c appears -jiiü the outputs of the (JND-

SSS ¹ ^.? "Si ^{4S 5iDd} ^ ^{5 Ei} " chants miider f ^ iS ^ Vl ^{% er} ' ^llnd - ^the output ^ · - E321 ₂ rf der Nun-Buleitungll «, appears. D ₁ . B ^.

> ina 126 are the corresponding input

low'i-ϊπ

12 on eintr rrlativ / um

tion,

^Λ '£ ηΤ / £ ύή * εηϊϊnnA 24 -from the Deco-'l9 b ^ ürrim? Whether diew Operzbon emeo hin »'At: NuH bttnrl · -» ird bssmnait im St ^ nd dir enUprcch ««'

cherz.dk 3 ti «F-Jn ^ ngtregnUrr». ,. ^ _{Trs = iH} ^

the »itv,» wH «ng 6 contains the biüe: Uingi-Treiberscrwivjjiswn 30« wl 31, whose ae hirkiiuagtn 11 '»* · ^J2 & -

yftl |

309 6 ¹ S 2i3

■ <·

ίο

inputs to the AND circuits 48 and 49. That is S to whom the election output line 24 is from

Mask setting line 20 from decoding circuit 19 decoding circuit 19 is not energized. The arrangement

is also available as input SM with the two AND connections with the inverter 64 and with the AND circuit

Circuits 48 and 49 connected. The purpose of the device 65 is to connect the input L of the line

Details of a word circuit 15 ... are shown in FIG. 5 5 circuit 52 always to be energized when the

shown. The circuit includes the first toggle switch input // not energized except when running

device 16, dk second flip-flop 17, a transfer of a selection operation. The AND circuit 66 receives

gungtrigccr 50, a LeiUings driver circuit 51 also catches the write output as input W

for the word collector line 13 and a line 23 from the decoding circuit 19. Driver circuit 52 for the word emitter line 14. io The output indicating the match signal

The line driver circuit 51 is constructed to feed line 54 from the line driver circuit 52

that the voltage on the word collector line 13 is connected as an input to the OR circuit 68

■ Ormalerwcise a first higher value is for reading bands, which are also the output as the other input.

Nd selection operations on the data storage cells 8, output signal 69 of the set transmission trigger 50

tiit which the line 13 is connected. When he has 15. The output 29 is the output leL.mg for

However, input 53 is energized, the voltage drops to control the next dial that energizes

of line 13 is set to a second lower value in order to generate the first or second flip-flop circuit of the

for write operations on the data storage cells. next lower word switching in the operation

The word line driver 52 operates in a similar way to driving "select next word memory". The * ie the drivers 30 and 31 of the bit circuits. When the corresponding output line of the neighboring input // is excited, the word circuit, which is the next higher word circuit, is used as input line 14 with a voltage that is high relative to the reference voltage for controlling the next selection process, and when the input L is excited, the one input leads to the AND circuit 70 gcle_i, the line 14 a low relative to the reference voltage and also as input N, the output line 22 to the voltage. If no input is energized, the »5 control carries out the next selection process from .i <DeLeitung 14 reference potential. The line driver coding circuit 19 picks up.

Circuit 52 differs from drivers 30 in order to describe the execution game And 31 in FIG. 3 in that they simplify the additions or removals of the associative memory, we i the Nature of the current on the word emitter line Description of the clock system omitted. the 14 feels. It is recalled that current on 30 construction of a suitable clock u: v..I die tier line 14 as a signal no match activation of gate wiping controlled by the clock the content of the circuits connected to the line 14 with reference to FIGS which data storage cells and the content of the memory that is written to is only done with general information

tangsregister indicates, whereas in the absence of this known technique. A suitable clock for tromes there is a match. 35 the memory described generates a time in .wall

Accordingly, the line driver 52 energizes with two equally large sub-intervals. In the first

an output line 54 in the absence of the current sub-interval a dialing operation should take place,

out of the word emitter line 14 when both inputs for setting the first or second Kippsüialgangs H and L are not excited. The output line to a selected word memory or aiii the device 54 is via the AND circuit 55 and the two adjacent word memories, in addition to the selected one, the AND circuits 56 and 57 each with the word memory. Or it leads to an over-input of the first toggle switch 16 or to the transfer of the setting of the first or second toggle switch 17. The AND switching circuit to the corresponding trigger circuits

Device 55 receives an input signal N via that of the next word memory. In the second sub-intermediate input 58, which is excited when the line 45 is vall a read or write operation should take place. 22 to control the "next" selection process from All memory operations are combinations the decoder 19 is not energized. The AND circuit 56 processes which occur in the two sub-intervals with an input on the primary output lines, although some operations more than one newspaper. 25 connected by the decoder 19, and the interval may need for execution. AND circuit 57 is connected with an input to the decoder 19. If the inputs for setting the trigger are excited, the outputs 59 or 60 of the selection operation are respectively set first or second toggle switch. Gate of a line 63 connected. The AND circuit 61 circuits ensure that the output signals of the ge receives as input P also the primary output set first and second flip-flops not line 25 from the decoding circuit 19 and the // inputs of the line driver circuit AND circuit 62 as input SY the secondary 52 (Fig. 5) are given. The AND circuit on the output line 26 from the decoder circuit 19. 60 65 prevent the output signals of the invert - as long as the lines 67 are not energized, as with the // input of the line driver 52, as a result, both inputs H and L are not excited via the inverter 64 and the AND circuit and the word emitter lines 14 carry Be 65 with them the L input of the line driver 52, and 65 pull potential. In the case of a selection operation, binary digits of the input register 2 with the input also correspond to 53 of the line driver 51 via the AND circuit 66. The AND circuit 65 compares the positions of all word memories, which also has an input line 67 which excites mask circuits 3 , whose trigger 4

(Fig. 4) is in the stable one state. The election exit line 24 is energized when a dial operation is required and consequently the AND circuits 42 and 43 in the respective mask circuits are enabled to output the signals on bit lines 116 and 126 from the input register to let through to the bit circuits via the bit lines 11 ″ or 12 ″. At the in The bit circuit shown in Fig. 3 becomes the AND circuits 33 and 34 energized when the zero bit line ilc is marked, then the zero bit line 11 from the line driver 30 with a low voltage and the one-bit line 12 from the line driver 31 is supplied with a high voltage. When the one bit line 12a is marked, the AND circuits become 32 and 35 turned on, whereupon a high voltage on the zero bit line 11 and a low voltage is applied to the one bit line 12. When the mask circuit is a marking of the bit lines 11 ″ or 12 ″ prevented, the AND circuit 36 is switched on and both bit lines 11 and 12 fed with a low voltage.

With reference to FIG. 2, it has already been described above how these signals on the bit lines II and 12 affect the data memory cells 8 when the word emitter line 14 carries reference potential. When a match signal appears on an input line 14, the output line 54 of the connected line driver 52 (FIG. 5) is energized. In the case of a primary selection operation P , the output line 25 of the decoder 19 is excited, whereas in a secondary selection operation .ST the output line 26 of this decoder is excited. Depending on whether line 25 or 26 is excited, the signal on line 54 sets first flip-flop 16 or second flip-flop 17 via one of AND circuits 56 or 57.

Operation "Select next word memory"

In these operations, the next lower word memory ("lower" as shown in FIG. 1) is selected by setting the corresponding first or second toggle switch of the word circuit to be controlled, which is assigned to the word memory to be selected. Such a selection operation can consist of setting the toggle switch of the next word memory immediately after a word memory emits a match signal, or of transferring the setting of the toggle switch in a word memory to the toggle circuit of the next memory. In the first case, the selection line 5 and the output line N for controlling the next selection process are energized simultaneously by the decoder 19, depending on the requirements together with the primary line 25 or the secondary line 26. As a result, the in FIG. AND circuit 55 shown in FIG. 5 is not energized, whereas AND circuit 70 is energized. The signal on line 54 from line driver 52 is routed via OR circuit 68, the "next" output line 29, which is also the "next" input line 29a of the following neighboring word circuit, and thus sets the first or second toggle circuit of the next word memory . In the second case, when the setting of a first or second flip-flop is to be transmitted, the selection output is not energized. When a first or second flip-flop is set, the Augang the flip-flop turns on a transmission trigger 50, which the "next" output line 29 he ^r egt a line 69 and via the OR circuit 68th

Read operation

For a read operation, the word emitter line 14 should carry a high voltage and the bit lines 11 and 12 should carry the reference voltage. The read operation only takes place in the word memories that were previously selected by setting the first or second flip-flop. Depending on whether the operation is to take place in the word memories whose first or second flip-flop is set, the AND circuits 61 or 62 of all these word circuits are energized in accordance with the output of the decoder 19. In the word memories with the flip-flop set, the W input to the word driver circuit 52 is energized and the voltage on line 14 is raised to a high value. Since the read operation is not a dialing operation, the AND circuit 65 is energized in the remaining other word memories and thus the line 14 is kept at a low voltage, whereby each in the transistors T1 and TA of the connected data memory cells 8 (Fi g 2) The current flowing is directed onto the word emitter line 14, thereby preventing erroneous signals from appearing on the bit lines.

From Fig. 3 is m oaks, daii none of the AND circuits 32 are energized to 36 during a read operation, which causes the bit lines 11 and 12 carry the reference potential. Raising the voltage on the word emitter lines 14 'of the selected word memories conducts any current flowing in the transistors 7-1 and 74 of the data storage cells of the selected words to the bit lines. The read operation is thus an OR operation on the same binary digits of all selected words, the result of which appears in the output register 9.

A read operation only takes place at those locations in the word memory for which the mask trigger 40 is in the stable zero state. In order to enable this control, the two bit lines 11 and 12 are connected to the output register 9 via a corresponding AND circuit 71 (FIG. 1). The AND circuits 71 for each pair of image lines of a data storage cell have a common input from an inverter 72 which is driven by the output of the AND circuit 41 in the corresponding mask circuit 5 (FIG. 4). The AND circuit 41 is energized when the mask trigger 40 is in the stable one state and a read operation R takes place. As a result of the arrangement just described, the data read on the bit lines 11 and 12 are only passed into the output register at the binary positions for which the mask signal is zero.

Write operation

For a write operation, the same voltage is to be applied to the bit lines 11 and 12 as for a «select operation. If no data are to be written into one or more data memory cells of a word memory, the corresponding bit lines are kept at reference potential. For diesei case no precautions need to be taken to who, such. B. for an elective operation by dh

I 801 215

AND circuit 36 (FIG. 3), since the outputs are at reference potential anyway if none of the inputs for the bit drivers 30 and 31 is excited. For a write operation, the voltage on the word collector line 13 should be decreased and the voltage on the word emitter line 14 should be increased. With selected words the output signal! of the set primary or secondary trigger to the // input of the line driver 52 and also via the AND circuit 66. Its other input H ^- fed through the write output line 23 of the decoder 19 w, rd, to the input 53 of the line driver 51 given. If words are not selected, the L input of the line driver 52 is switched on as in the read operation, which separates these word memories from the bit lines and thus ensures that signals on the bit lines have no influence on the memory cells in the unselected words.

Toggle operation

These operations include combinations of the operations described above for selecting the next word memory and read operation, however the setting of the mask register is not taken into account. For this purpose there is a sound conduction from the decoding circuit shown in FIG 19 on the one hand with the AND circuits 71 so

, in that the effect of the mask register is canceled during reading and on the other hand, Si is (F ig. 4) to the AND circuits 74 and 75 in joder mask circuit 5 is connected so that when a switching SW the B.tleitungen Uh

ίο and 12fr corresponding to the bit lines 11 λ and 12 "be connected through regardless of the Ems \ e! Lun" of the respective M-.sk trigger 40. To a Toggle operation can also set ues Make-up reoisters that do the reading of the: e-

_IS chose Wort'in the mask trigger 40 umtai.U. When the external line 20 is excited by the decoder switch 19 as a mask set line SM, the AND circuits 48 and 49 are switched on and connect the bit lines lift and Ub n:

the ones of the mask trigger 40th Gee.gn, · TorchesaUuneen under the control of the M as κ -.:-- SetzHtungiO are used for data transmission via U. Line 28a (Fig. 1) from the output of the register · ' to the input register 2. where you set the bit line

Mark lift and 12b accordingly.

1 sheet of drawings

Claims (4)

Patent claims: 1. Associative memory with a multi-digit input register. which has a data word and a password memory part and comparison devices for comparing the data content of one or more places in the input register with the places de. Xpassword and / or data word memory part, each memory part being so arranged. that it generates a match signal when the compared data bits in the password and / or file word memory match the corresponding bits in the input register and in which an output register is coupled ^{to the Eii 1!} - and / or data word memory part (7) with a plurality of first flip-flops (16) and a plurality / further flip-flops (17) connected to the input side via a common word circuit (15) and a decoder (19) a control register f 18) are connected and can be set as a function of the generated match signal and the content of the control register * (18), the flip-flops (16 and 17) of adjacent memory parts (7) each being controlled by an L-iiun «(29) of the state of a pair of tilting positions (16 and 17) depending on the state of the previous tilting position (16 and 17). 2. Associative memory according to claim 1, characterized in that the control register (18) via a decoder (19) and its output lines (24, 25 and 26) acts on the toggle switch pairs (16 and 17) assigned to the individual memory parts (7). 3. Associative memory according to claims 1 and 2, characterized in that the output ! Longitudinal register (9) via a line (28a) to the input of the input register (2) and to the Input of the control register (18) is connected. 4. Associative memory according to claims 1 to 3, characterized in that each memory part (7) contains a tristable data storage cell (8) for each binary digit, the first of which is more stable State embodies a binary zero, whose second stable state embodies a binary one and its third stable state is characterized by the fact that it is characterized by both the state Zero as well as after the state one can be queried and when the state of the data storage cell is queried (8) generate a match signal. 55