DE1789175A1 - METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR WITH AN INSULATED CONTROL ELECTRODE - Google Patents

Description

N.V.- Philips' GIo e ilamp enf abri eken, Eindhoven / Holland

Method for producing a field effect transistor with isolated control electrode

The invention relates to a method for producing a. Field effect transistor with an isolated control electrode, consisting of a silicon semiconductor body with one part of a first conductivity type in which two adjacent Surface zones of opposite conductivity type are attached, soft the source and the drain zone of the field effect transistor form, where.bei on a surface of said part, an insulating layer is applied, the one lying between the source and the drain region Part-has that is thinner than surrounding parts of the layer, wherein a gate electrode is applied to the thin part of the insulating layer lying between the said zones.

The gate electrode of a field effect transistor with an insulated control electrode forms together with the semiconductor body and the intermediate insulating layer a capacitor, in which the conductivity is in a channel in the semiconductor body

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between the source and the drain zone can be influenced with the aid of a voltage across the capacitor. In the In practice one leaves the gate electrode the source and the Overlap the drain zone a little to ensure that the channel makes good contact with the source and drain zones has and / or the conductivity in the channel over its entire length between the source and drain regions to be able to influence.

When it is mentioned in the present specification that the gate electrode on the thin, between the source and the drain zone lying part of the insulating layer is arranged, this must be understood to mean that the thin part of the Insulating layer and the gate electrode, the source and the The drain zone can overlap somewhat.

Metal layers are usually attached to the insulating layer, which are connected to the gate electrode and to the source and drain regions via openings in the insulating layer are. These metal layers can also be combined with other circuit elements attached in the semiconductor body be connected and / or be provided with connecting conductors. The metal layers are preferably on a • thick insulating layer attached, among other things so that the Capacity between these metal layers and the semiconductor body and the risk of a short circuit between one Metal layer and the semiconductor body is lowered via a hole (pin hole) in the insulating layer.

It is known, the surface of the semiconductor body of a Field effect transistor to which the source and drain zone limit, to provide with a thick insulating layer, for example silicon oxide, and this oxide layer between to make the source and drain regions thinner by etching. This requires a very precise photo masking technique, yet it remains difficult to be reproducible in this way to achieve a desired thickness of the thin part.

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In addition, the transition between the thick and the thin part of the insulating layer a large step on which a later applied metal layer can break. It is also known to completely etch the thick oxide layer between the source and drain regions to remove and then apply a new, thinner oxide layer. The thickness of the thin oxide layer can be adjusted precisely in a simple manner, but for removal the thick oxide layer between the source and drain zones is a very precise photo masking technique here too required, the accuracy being adversely affected by the fact that the thick oxide layer is locally removed must become. It is known that an opening can be made more precisely in a thin oxide layer than in a thick one Oxide layer. In addition, there is a big one here too Step between the thick and thin part of the oxide layer.

: It is possible to provide those parts of a surface of a silicon semiconductor body which border the source and drain zone to be attached with a thick silicon oxide layer doped with dopants and then to diffuse the source and to apply the drain zone, while the remaining surface is provided with a thinner silicon oxide layer by oxidation. No precision photo masking technique is required for this, but there is a disadvantage that the metal layers to be applied to the insulating layer have to be applied practically completely on the thin oxide layer.

The invention is now based on the object of specifying a simple method for producing a field effect transistor of the type mentioned, which avoids the disadvantages of the known methods set out above, at least for the most part . . - -

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The invention is based, inter alia, on the knowledge that by Use of an insulating layer, the thick parts of which consist of a at least over part of its thickness in the silicon semiconductor body recessed silicon oxide layer exist, the disadvantages described can be avoided, and thereby the advantage is achieved that the thin and thick parts of the existing insulation layer is flatter than with the field effect transistors produced by the known method.

The stated object is achieved in that, starting from a silicon semiconductor body with a part of a first conductivity type, the surface areas of said Part of the semiconductor body that correspond to the source and drain zones to be produced and the surface area between them, over which, insulated from it, the gate electrode will later be arranged, with an overlay masking against oxidation masking layer containing at least part of its thickness silicon nitride is covered, then the uncovered surface regions be subjected to an oxidation treatment in order to produce a silicon oxide layer over, at least part of its thickness is sunk into the silicon body, then by introducing dopants into parts of the during the oxidation masked surface areas to the sunk Silica subsequent and distant from each other Source and drain zones are generated and a gate electrode is applied between the source and the drain zone, which between the source and drain regions of the semiconductor body is separated by an insulating layer that is thinner than the buried silicon oxide layer, the gate electrode extends over the recessed silicon oxide layer. Included can at least the silicon nitride-containing part of the masking layer During the process step after the oxidation treatment, the silicon nitride is removed with the aid of an etchant attacks much more than silicon oxide.

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Thanks to at least part of its thickness in the silicon semiconductor body recessed thick parts of the insulating layer, a flatter surface of the component is achieved, which is advantageous, among other things, with the arrangement of the gate electrode. The method according to the invention can also be used can be carried out without using a precision photo masking technique, i.e. a photo masking technique, in which a mask with great precision compared to parts that have already been manufactured, for example the Source and drain regions, must be aligned. This is discussed in more detail below.

The oxidation treatment can advantageously be continued until the at least part of its thickness Layer parts sunk into the silicon semiconductor body are thicker than the mask masking against oxidation. This has the advantage, among other things, that openings for the diffusion of the .Source and drain zones. Placed very precisely in the thin mask can be. .

In a preferred embodiment of the invention, the one originally located between the source and drain regions Part of the mask replaced by a silicon oxide layer. which is thinner than at least over part of its thickness recessed layer parts made of silicon oxide. The gate electrode is then arranged on this thin silicon oxide layer, which extends over the buried oxide layer for contact purposes. A thin silicon oxide layer can, for example be desirable if a high stability of the field effect transistor is required. Furthermore it is possible to use a double layer of e.g. silicon oxide and silicon nitride under the gate electrode.

However, a mask can also be used which consists of a there is a silicon oxide layer bordering the silicon semiconductor body, which is masked against oxidation with a

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Material layer is covered, wherein after the application of the source and drain zone, the mentioned cover from against Oxidation masking material is removed, after which the Gate electrode is attached. Before the gate electrode is attached, the originally with against oxidation masking material-covered silicon layer still subjected to a stabilizing treatment and / or somewhat thickened will. A significant advantage here is that after the source and drain zones have been attached, the thin silicon oxide layer, on which the gate electrode can be attached is already present, so that the component is not or at least for a shorter time, again at high temperatures, which are required when applying a thin oxide layer and which influence the already attached source and drain zone can, needs to be subjected.

Openings can be provided in the layer which mask against oxidation are attached, which are adjacent to the buried oxide layer and through which dopants can be diffused, to create the source and drain regions. By using An etchant that etches away the silicon nitride faster than the silicon oxide can use a precision photo masking technique be avoided.

Preferably, silicon nitride is used as a material masking against oxidation, since it gives very good results have been achieved

Embodiments of the invention are in the drawings and are described in more detail below. It demonstrate

Fig. 1 is a schematic section through an inventive produced field effect transistor along

the line I-I in Fig. 2,

Fig. 2 is a schematic view of the field effect

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transistor according to Fig. 1 and

3-5 schematic sections through this field effect transistor, showing different manufacturing stages represent.

Figs. 1 and 2 show an example of one corresponding to that Field effect transistor produced according to the invention and having a silicon body 1 of the one conductivity type in which two adjacent surface zones 2 and 3 of opposite conductivity types are arranged, the source and drain regions of the field effect transistor. form with insulated control electrode 4. An insulating layer 5, 6 is arranged on the surface of the silicon body 1, which has a part 5 between the source and drain zones 2 and 3, which is thinner than the rest of the area surrounding it Part 6 of the shift. On this thin part 5 of the insulating layer 5 »6 lying between zones 2 and 3 the gate electrode 4 is arranged. The part 6 of the insulating layer 5, 6 consists of silicon oxide and is at least one Part of its thickness sunk into the silicon body 1. '

The thin part 5 of the insulating layer has a thickness of at least 0.1 µm.

The gate electrode 4 is with one on the part 6 of the insulating layer 5, 6 provided part 8, with which a connecting conductor can be connected. With the ones on part 6 Metal layers 9 and 10, which are connected via openings 11 and 12 in the part 6 to the source and drain zones 2 and 3, respectively leads can also be connected.

The silicon body 1 can be part of a larger silicon body form, in which further circuit elements are provided. The silicon body 1 is then part of the one Conductivity type of the larger silicon body. The metal layers 8, 9 and 10 can then in the usual way be designed * that they are connected to other circuit elements. 7Q9842 / 0008

Since the thick part 6 of the insulating layer b _t 6 übar 3 a part

its thickness is recessed into the silicon body, ^the. surface of this layer is shallower than b, ei known, field effect transistors having an insulating layer with a thick and a thin part. This is of great advantage when attaching the "! Gate electrode.

It also needs when performing the procedure , according to the invention, no precision optics photo masking technique - to be applied.

The following is an example of the application of the method according to the invention for the production of a field effect transistor

according to FIGS. 1 and 2 described. . ^: ■ '-''-. ■ w

In the method according to the invention, the part of Surface of the starting silicon body 1 on which the thin and part 5 of the insulating layer provided with the gate electrode 4 5i 6 must be attached, and those adjoining-. ' the. .Parts of the surface that coincide with those in the masking layer

to be arranged openings 14 and 15 match, or with ; other locations, the source and drain zones to be attached are covered with a silicon nitride-containing layer 26 (see FIG. 3) masking against oxidation, after which • 'by oxidation over part of its thickness in the silicon. - Body 1 sunk silicon oxide layer 23 is attached.

By introducing dopants into "during" the oxide / " treatment treatment masked surface parts (see Fig. 4 and 5) are then the recessed silicon oxide layer adjacent, .. source and drain zones 2 and 3 which are spaced apart from one another are generated.

Between the source and drain zones 2 and 3, respectively, a Gate electrode 4 attached between the source and drain separated from the semiconductor body 1 by an insulating layer 5 which is thinner than the recessed silicon oxide layer 6 (see Figs. 1 and 2).

A part 8 of the gate electrode extends over the recessed silicon oxide layer 6.

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The masking layer 2β contains silicon nitride and is ■ completely removed during the process steps after the oxidation treatment mentioned with the aid of etchants which attack silicon oxide less severely than silicon nitride.

5 'By using an etchant that does not contain silicon oxide

or at least much less rapidly than silicon nitride A precision "photo masking technique" can be avoided here to have to apply. Phosphoric acid, for example, is suitable as an etching agent,

.It is, for example, from a P-conductive silicon body (Fig. 3) with a specific Voider stood of, for example, 10 XI / cm; ΐ * ^{η <} * assumed a thickness of 200 μm. The other dimensions of the silicon body are not important; they just have to be large enough to be able to produce a field effect transistor in the silicon body. . ". ■

- - ■ - Usually one becomes in a silicon body at the same time

• produce several field effect transistors and then divide the silicon body. . · ·

^: A silicon nitride layer with a thickness of about 0.2 μm is applied to the silicon body. This layer can be applied in the usual way by passing over a gas mixture of silane and ammonia.

- - kiert against oxidation. .

- With the help of a standard photo masking technique, "With the exception of part 26, the silicon nitride layer has been removed.

Thereafter, a silicon oxide layer 23 with a thickness of

• about 0.3 / µm generated by oxidation. For this purpose, e.g. water vapor guided over the silicon body kept at a temperature of about 1000 C until the desired thickness of the Oxide layer is reached.

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Thereafter, those adjoining the silicon oxide layer 23 are made Openings 14 and 15 with dimensions of approximately 950 µm 25 µm .. using a common photo masking technique and one Etchant introduced into the silicon nitride layer 26. the Openings 14 and 15 (Fig. 4) adjoin the silicon oxide layer

• 23, but thanks to the use of an etchant that removes the silicon oxide attacks faster than silicon nitride, the application

* No need to use a precision photo masking technique. Openings which overlap the silicon oxide layer 23 can then be made in the etching mask. In the one shown in Fig. shown cross section is a certain difference in width the openings 14 and 15 to be attached are irrelevant.

Phosphoric acid can be used as an etchant.

Phosphorus is then diffused into the silicon body 1 through the openings 14 and 15. For this purpose, the silicon body is heated together with an amount of silicon powder doped with phosphorus for about 10 minutes to a temperature of about 1000 ^° C. in an evacuated quartz tube. . and then removed from the pipe again. ".

The silicon body is then brought to a temperature of about .1000 ° C heated and water vapor conducted over the body, a silicon oxide layer up to the openings 14 and 15 of about 0.8 / µm in thickness. The silicon oxide layer 23 becomes thicker and reaches a thickness of about 0.85 / µm. It is then a thick silicon oxide layer 6 emerged, which are practically over the entire surface • of the silicon body outside the channel area in the surface layer 7 extends and which is sunk approximately 0.35 / μm deep into the silicon body 1. · ".

The silicon surface layer, which adjoins the oxide layer 6 sunk over part of its thickness over its entire thickness, thus has a thickness of approximately 0.35 μm. Fnosphorus continues to diffuse during the oxidation process, so that after the completion of the layer 6 the N-conducting source and drain zones 2 and 3 respectively have a thickness of more than 1 μm. ^ 7098 42/0008 '

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'The thickness of about part of its thickness in the silicon body 1 sunk silicon oxide layer 6 is much greater than the thickness of the original between the openings 14 and 15 lying part 16 of the mask 23, 16 which mask against oxidation.

Although the gate electrode 4 is on the part 16 of the mask 23, 16 can be attached, is in this example with a view to desired electrical properties of the manufactured Field effect transistor this part 16 by 'a silicon oxide layer 5 (Figs. 1 and 2), which is significantly thinner than the oxide layer 6 sunk over part of its thickness, replaces, after which the gate electrodes are then placed on this thin oxide layer 5 is applied. ". · '." "" ". -.

The silicon nitride layer 16 is removed by immersing the silicon body in phosphoric acid at a temperature of about 190 ^° C. until the layer 16 is removed. The oxide layer 6 becomes thinner and finally has a thickness of 0.7 μm. \ "* ·

Subsequently, for generating the silicon oxide layer 5, the •. The silicon body 1 is ^{heated to a temperature of 1000 °} C. for 10 minutes and water vapor is passed over the body at the same time. In order to improve the quality of the oxide layer 5, the silicon body 1 is then ^{heated again for about 10 minutes in oxygen to a temperature of about 1000 °} C. and then for about 5 minutes to a temperature of 1000 ^° C. in. Nitrogen and finally over about 30 minutes to a temperature of about 450 ^° C. in nitrogen containing water vapor. The layer 5 then has a thickness of approximately 0.2

With the aid of a conventional photo masking technique and an etchant, the openings 11 and 12 are then dimensioned of about 850 μm 10 μm is introduced into the oxide layer 6.

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Thereafter, the gate electrode 4 with the in the usual way Part 8 and the metal layers 9 and 10, which are connected to zones 2 and 3 via openings 11 and 12, attached. . The layers 4, 8, 9 and 10 can consist of aluminum.

The actual field effect transistor is thus produced.

In the usual way, connecting conductors can then still be connected to the Me-. ^: tallschichten 8, 9 and 10 connected and the transistor housed in a housing »

"Instead of the silicon nitride layer (Fig. 3 and 4) can also a mask made of a silicon oxide layer

consists, which with a masking against oxidation, SiIi-. zium nitride containing material layer is covered. Thereby: after applying the superfine part of its thickness, "f, silicon oxide layer 6 lowered the cover against oxide-15 ' tion masking material removed and then the gate elec- .. trode attached to the remaining oxide layer, which then

immediately forms the oxide layer 5 (FIGS. 1 and 2). The layer "can, for example, consist of an arrangement on the silicon body 1 - put a silicon oxide layer with a thickness of 0.2 / µm, which is covered with a silicon nitride layer, which can also be approximately 0.2 μm thick. The quality - .- the one remaining after the silicon nitride layer has been removed Oxide layer 5 can in the manner already described above and Way Before attaching the gate electrode 4, improved v / grounding. This method has the advantage that 'Zones. 2 and 3 in this way less long high, to apply the layer 5 required temperatures.

The field effect transistor to be produced using the method according to the invention can of course have a geometry that deviates from that shown in FIGS. 1 and 2, e.g., concentric Have geometry »·

Patent claims:

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Claims (2)

Claims ί I / O 9 175 1. Method for producing a field effect transistor with insulated control electrode, characterized in that, starting from a silicon semiconductor body with a part of a first conductivity type, the surface areas of said part of the semiconductor body, which correspond to the source and drain zones to be produced and the Surface area between them, over which, insulated from it, the gate electrode will later be arranged, with a A masking layer masking against oxidation and containing silicon nitride over at least part of its thickness covered * then the uncovered surface areas are subjected to an oxidation treatment to form a silicon oxide layer to generate, which is sunk into the silicon body over at least part of its thickness, then by introducing dopants into parts of the surface area masked during the oxidation on the "sunken" Source and drain zones (2, 3) adjoining silicon oxide and spaced apart from one another are generated v / ground and between a gate electrode (4) is attached to the source and drain regions between the source and drain regions of . the semiconductor body is separated by an insulating layer (5), which is thinner than the recessed silicon oxide layer, whereby the gate electrode extends over the sunk silicon oxide layer extends. 2. The method according to claim 1, dadu rch gekennzeichne t that at least the silicon nitride-containing part of the masking layer is removed during the process steps after the oxidation treatment with the aid of an etchant that attacks silicon nitride much more strongly than silicon oxide, - ' 709842/0001 badoriginal