DE1774832C - Method for reducing the power loss caused by the information streams in a core memory - Google Patents

Description

1 2

The invention relates to a method for As now from the above statements

Reduction of which is clearly evident from the information flows, are above all the information

power loss caused by a core memory. currents responsible for the power loss caused

A core memory usually consists of η memory.

levels. According to the ri levels of a core 5 D: e invention has set itself the task of a

Memory blocks it is possible to specify η binary digits (bits) method by which the power loss,

to summarize in an encrypted word. caused by the information flows in the core

The number of storable and retrievable words, storable, is reduced. Succeeds according to the invention

d. H. of addressable words depends on this in the case of a core memory that corresponds to the

Number of storage elements on a level. In general io word length of π bits consists of η memory levels,

Ferrite cores are used as storage media by the fact that for each word to be written one

which takes place in the form of a matrix, consisting of .v lines and a check to determine whether the number of "0" -

y columns, are arranged. Corresponding to the .v line-valued bits within a word greater than or

kernels and y column kernels is then the,. η is an inversion in the affirmative

storable word capacity m = χ · y words. 15 ^B 2 ' ^{J &}

For writing and reading information of the word to be written takes place and that in one

are driver-additional (p + l) -th memory level for each word through all cores in .v- and ^ '- direction

lines passed through. The most widespread me-. a (/; + l) -th bit is used to determine whether the

method of writing information into the kernels or reading out the information from the relevant word

read out, makes of the coincidence principle (partial ao must be inverted or not,

current principle) use. In this case, when screaming, FIG. 1 to 4 of the drawing should be in

. ,,. ■. · ■, Im. , The following, the invention will be explained in more detail. It

ben positive half-current impulses + ₂ in the x- and ^ _{in the einrinen}

^ Drivers generated. Only in the crossing points, F i g. 1 a single ferrite core with the

where row and column lines cross, add 25 required driver wires,

• uj · 11 lu. - 1 , fm ■ ,, 11 F i g. 2 the basic structure of a core memory

s.ch de half-current pulses +. ₂ to a full flow f _mjt £ _he g _{ndungsgemäß} provided to-

impulse + Im, which is sufficient to store the cores in the positive additional memory level,

Retentive state to urge to which the digital value "L" F i g. 3 shows a circuit arrangement for generation

assigned. To read the '' .erne it is necessary to add 30 of the additional bit ZB,

to generate negative half-current pulses or the F i g. 4 a logic gate for inverting the

Reverse current direction. Cores that positively magne- word information.

are tisicrt and which are located at the intersection of the two in F i g. 1 shows a single ferrite core, negative read half-currents are now toggle into the through the .v- and ^ -driver wires for the purpose of shrine negatives Retentive state, to which the digital value "0" 35 ben and reading of the information are threaded and assigned. Through a read wire, det through all of the continue the read wire and the Infor cores Matrix is threaded, it can be determined that mation wire is threaded.

whether a is located at the intersection of the half-currents- F i g. 2 shows a memory block with η memory

Iichcr core was in the positive remanence state. levels corresponding to the word length of η bit, with

A written core memory word 40 in a further memory level for a check bit PB and not in all of its binary digits has the value digital “Z.” according to the invention with an additional memory. Rather, the statistical mean is the value level for an additional bit ZB. In the foremost level, digital »0« appears just as often within a word. are the cores of a matrix and the associated parts. That means that columns and row driver lines are drawn in some memory levels. The image of an "L" in the crossing points of the 45 others is what all cores of a matrix must prevent through driver lines. For this purpose, an information wire ("inhibit wire") is indicated for each running information driver wire and the reading wire of the memory level.

provided that penetrates all the cores of a matrix. The advantages of the inventive method

and, for example, the j-driver wires in the opposite direction - we shall now use a specific example in the following

works. By exciting this information wire with 5 ° the following can be explained:

A half-current pulse can include writing a core memory, for example

"/." be prevented. While the write and check bits have a word length of 13 bits. The memory word

Read pulse only .v cores of a line and then itself has a length of η ----- 12 bits. Of these

y cores of a column enforce, the In- η bits must each be Κ _λ bit "0" -value and K ₂ bit "L" -

formation impulses all m - ■ χ · y cores of a storage 55 valued. The check bit PB is then z. B. in each case

enforce chermatrix. With a typical memory * create that the number Af ₂ of »/.

capacity of, for example, m = 4 kilobits (64 - 64 together with the check bit PB becomes an even number (pari-

- ■■ 4096) thus results for a memory matrix, validity check). To the «bits of the word information and

that the coordinate streams when writing only to the check bit, which results in the word length of 13 bits,

l \ m 128 cores and the information streams every 60 still comes in according to the inventive proposal

m must enforce 4096 cores. Additional bit 2B added.

Each current through the nuclei is primarily responsible for the number. In the known process, the number is determined

Losses in the wires. On the other hand, it is the required information flows out of the number

known that a temperature around 10 "C that of the" O "-valent bits within the word information

Lifetime of the affected components of the core 65 and the test bit, so that in the worst case the

Memory is reduced by about half , each stream requirement results in the information in all 13 levels

Durdi the nuclei caused electrical currents to continue to drive through the nuclei. According to the

Faults in other core memory components. Proposal of the invention succeeds here in a decisive one

i 774 832

Improvement by checking whether the η bits of the word information "or."

more bits have the value ..0 «. If this is the case, the word information to be written and the check bit are inverted. The information that an inversion takes place is stored in a 14th memory level by marking an "L" in the appropriate place. As long as there is no inversion, it is necessary to mark a "0" in the appropriate place in the 14th memory level, which requires an additional flow of information. However, this minor disadvantage cannot overall impair the advantage of the inventive method.

The table below shows the difference between known and new Procedure clearly.

Word information Value £. " Check bit Known Additional bit / I worth New procedure ti = (A ', + λ',) bit A ", PB proceedings Ptl <L> ■ 0 « number of 12th worth number of for .Ov Inhibit currents 11th Inhibit currents "0" SJ, Number of bits with the 10 ■> 0 « "0" Value · 0 « . 9 1 «0« 2 8th "0" 1 .0 « 2 0 7th λ Ln 3 »L * 4th 1 6th .lO « 3 "L" 4th 2 5 * L * 5 »L * 6th 3 4th "0" 5 -L * 6th 4th 3 "Z." 1 -L- 6th 5 2 "0" 7th -Lt 6th 6th 1 »L * 9 -Li 4th 7th 0 * 0 « 9 4th 8th D L « 11th 2 9 "0" 11th 2 10 13th 0 Il 12th

From this table it can be seen that when using the inventive method, the number of simultaneously flowing information streams has decreased from 13 to 6 in the best case.

Has means, first of all, a reduction the power loss. Because the electrical data of the magnetic cores used and the aging of the components is temperature-dependent, once while maintaining the design of the core memory, i. H. Maintaining the permissible operating temperature range, a reduction in the statistical probability of errors and thus increased security against malfunctions can be achieved. On the other hand, there is a possibility of the permissible To expand the operating temperature range, which is of great interest, for example, in storage for military applications.

Furthermore, one achieves resourcefulness when using the e Method both a reduction in the electrical caused by the information flows Interferences in other core memory circuits as well as a reduction in the information flow for the information required maximum power requirement. The latter fact allows together with the through the inventive method resulting in small fluctuations in the power requirement (maximum six Streams of information instead of thirteen) single line at the feed source delivering the streams of information.

If a memory level fails, the results required for the method according to the invention result additional storage level has the advantage that this storage level takes the place of the failed storage ' level can step. As a result, the memory can continue to operate in the manner known hitherto. In this case, the supply voltage source power be provided with sufficient reserve capacity. The target bit therefore serves as a reserve bit.

In order to implement the inventive method in circuit technology, the memory block has to be expanded once - as already mentioned - by a further level for the additional bit ZB.

_{Furthermore, a circuit arrangement} is to be provided, which for the case that Ί or more than bits

of the core memory information to be written have ti ic valency> 0 ", the information is inverted and an additional bit ZB with the valency" Z. "is generated.

For the decision K ₁ >" where Λ ', the number of

Bits with the value "0", a circuit can advantageously be used which consists of a digital-to-analog converter and a downstream comparator, as shown in I i g. 3 of the drawing can be seen. The outputs of the information register for the / 1 bit of the word information JA ₁ ... JA _n are fed to the inputs of the digital-to-analog converter 30, which evaluates each input with the same weight. In the simplest case, the D '^ ital-analog converter / he can from the parallel connection of /; consist of equal resistances, which are brought together in a common sum point. The analog output of the digital-to-analog converter is then connected to one input of a differential amplifier 31. A reference voltage U is applied to the other input of the differential amplifier, the magnitude of which is selected so that the differential amplifier outputs a "Z." Ziisat / bit ZB when K _t >". This addition / bit is in the

5s additional memory cbcnc to be saved.

It is then / between the outputs of the information register for the η bit of the word information JA ... JA _n and the check bit JAfn and the core

ipeicher-Infoftnationseedänge KJA _x . . . KJA _n , KJApB to provide a logic switching element that fulfills the following Boolean equation:

KJΑμ = JAμ ZB + JAμ ■ ZB.

This equation is fulfilled by an OR- NOT element 42, which is preceded by two AND elements 40 and 41, the respective valenie information register output JAμ and the additional bit ZB and the two inputs being fed to the two inputs of the one AND element 40 of the second AND element 41 are each acted upon by the complementary signals. How to use the F i g. 4 of the drawing, the core memory information KJΑμ is always negated with respect to the information register content JAμ when the additional bit ZB = L.

Claims (3)

Patent claims: 1. A method for reducing the power loss caused by the information flows in a core memory, the core memory consisting of η memory levels according to the word length of η bits, characterized in that for each word to be written a check is carried out to determine whether the number of t0 «-valent bits within a word greater than or equal to " is that in the affirmative case the word to be written is inverted and that in an additional (n + 1) th memory level for each word in an (n + 1) 4th bit whether or not the information must be inverted when the relevant word is read out. 2. Circuit arrangement for carrying out the method according to claim 1, characterized in that the outputs of an information register for the η bit of the word information are fed to the inputs of a digital-to-analog converter (30) with equal weighting of all bits, the analog output of which is connected to an input of a Differential amplifier (31) is performed, and that the other differential amplifier input is connected to a reference voltage Vr, f, which is selected so that the differential amplifier only supplies a Z. output signal (ZB-L) when half or more bits of the word information have the digital value »0«. 3. Circuit arrangement for carrying out the method according to claim 1, characterized in that between the outputs of the information register for the / 1 bit of the word information (JA _x . JA _n ) and the test bit {JAp _B ) and the core memory information inputs each logic circuit elements ( 40, 41, 42) are connected, which is the Boolean equation KJΑμ = JAμ ■ ZB + JAμ ■ ZB
realize. 1 sheet of drawings