DE1774627C3 - Method of enabling numerous logical operations - Google Patents

Description

The invention relates to a method according to the preamble of claim 1.

A practical system for performing logical operations that integrates in a memory array or would be distributed in this (memory with

a5 shared logic), has long been the goal of the relevant Been experts. Such a facility would, for example, implement an associative one Enable the logic, control and storage functions to be fully integrated into economic

are integrated in a more practical way.

The previous associative or content-addressable memories regularly required extensive and expensive semiconductor devices or a complicated interface between electrical lo-

gic circuits and magnetic memory cells.

This costly and, moreover, inflexible circuit component made such memories Economically unattractive, especially when it comes to larger storage units, although such

From a theoretical point of view, memories hold promise.

The recent developments in the field of magnetic domains have promised promising prospects Application to this field. For example, in

the USA.-Patent 2919432 describes a memory arrangement in the context of a shift register-like Operation domains bounded by two domain walls through a transmission medium transmitted through that

for example in the form of a magnetic thin film. Here are opposite to the surrounding magnetization reversely magnetized as well as from a leading and a trailing domain wall limited domains generated at an entry position in the thin film and along a transmitted in a certain direction through a multi-phase transmission field. Such a device usually requires anisotropic magnetization, with the transfer of the reversely magnetized Domain along the axis of easy magnetizability or, alternatively, along the axis difficult magnetizability (magnetically hard axis) takes place; and the domain walls that the limit reversed magnetized domain, extending to the boundary edge of the Layer perpendicular to the direction of transfer. Because the domain walls are limited by the edges of the layer are, is the propagation of such domains

limited to one direction along this boundary edge. In addition, there are troublesome domain wall creep effects occur that require special security measures.

Another known arrangement in which the use of domains is limited because of the Requirement to rely on a predetermined structure is described in the articles "Controlled Domain Tip Propagation", Part I and II of R.J. Spain et al. in the Journal of Applied Physics, Volume 37, Number 7, June 1% 6. With this arrangement Domains expanded along paths defined by limited channels in the magnetic assembly and there could be useful effects from the expansion and interaction of unipolar domain tips be derived. Again, the domains cannot be moved outside of the channels and the domains cannot fully interact with one another, since they have the property of becoming a single domain under the conditions described there unite when trying to move two domains to the same position.

On the other hand, an older patent (German patent specification 1549136) relates to a completely new magnetic one Transmission arrangement in which single-walled domains are moved through localized fields be able. These fields create gradients, which lengthen the domains because they are stable structures, move as a whole. A single-walled domain differs from that in the United States patent 2919432 domains to the effect that it has a shape independent of the geometry of the layer, d. H. that they are not off the edges of the Layer, but are limited by a single, self-contained domain wall. These domains can be understood as magnetic dipoles localized in the layer, which because they do not penetrate laterally the layer are limited, can be moved freely in two dimensions. Arrangements with single-walled Domains work, therefore deliver an unimagined high flexibility and also have very high Packing densities, low energy consumption and a comparatively high working speed.

A solution to the problem has now been found in the further development of this single-walled domain technology found how an AND or OR operation can be made possible in a very simple way, the can be implemented without difficulties and in principle without additional circuit complexity, in this respect therefore especially suitable for a memory with split logic.

This solution for the procedure described in the introduction results from the characterizing part of Claim 1.

In the method according to the invention, use is made of the fact that the single-walled Domains understood as localized magnetic dipoles that can be shifted easily to and fro within the layer which are all oriented in the same direction and consequently mutual repulsive forces are subject to how they generally occur with magnets with the same polarity.

The method according to the invention has numerous advantages, such as this in the description below will be explained in detail. The invention also enables the use of the invention Exploitation of the interaction effects between single-walled domains in a storage structure, in which both logical functions and control functions as well as the actual storage function can be integrated in one and the same arrangement, or that additional "Hardware" is required.

The invention is explained below with reference to the arrangements shown in the drawing for carrying out the method; it shows
ίο Fig. 1 is a schematic overview drawing of an exemplary arrangement for the invention,

FIGS. 2 to 42 are schematic representations of certain parts of the arrangement according to FIG of the operation show the magnetization states present in each case, and

43 shows a schematic illustration of an exemplary system organization of the memory arrangement according to Fig. 1.

In experiments preceding the invention, an arrangement was set up and operated in which single-walled domains magnetized inversely with respect to the ambient magnetization were controllably transmitted by pulses on transmission conductors oriented in X and Y into a layer of magnetic material that had a preferred direction of magnetization perpendicular to the plane of the layer. It has been found that the next adjacent single-walled domains of such an arrangement show repulsive interaction forces, as can also be observed with magnets with the same polarity.

It has been found that the controlled movement and interaction of single-walled domains is the realization complete groups of information processing functions, especially logic functions, at any point in a memory.

As explained using the example herein, the invention is based on the knowledge that when information is in a magnetic layer by certain patterns of single-walled domains in corresponding bit storage locations is represented, the information can be selectively moved and manipulated in a manner can that all logical functions, as well as the actual storage functions, on different Pulse sequences can be led out on the transmission conductors, and this - it should be emphasized without any additional device-related additions to the effort required for Execution of the storage functions alone is required. It is known that a distributed logic has the ability to implement any computer function. The following information below regarding bit capacities and operating parameters will show the high utility of such an arrangement.

At this point in the description it appears useful to provide a compilation of expressions for easier reference to reproduce in the description of the exemplary embodiment:

1. Bit Storage Location: A group of 18 blocks arranged in 3 adjacent block columns are (Tab. I), where a block denotes a domain position.

2nd cell: Nine blocks that form half of a bit storage location.

3rd binary digit: Represented by the presence of a domain in one cell of a bit memory

cherstelle with simultaneous lack of a domain in the other cell of the bit storage location and vice versa.

4. Digit element: Either the presence or the absence of a domain in a cell representing one Corresponds to half of a binary digit.

5. Basic operation unit: Three adjacent bit storage locations in one line.

6. Intermediate position: Refers collectively to two blocks in a block column, the corresponding one Separate digit elements in two binary digits, which are separated from each other by this block column Distance.

7. Intermediate block: A block, the first and second corresponding digit elements in first and keeps second binary digits at a distance from each other.

8. Input Tag: Characteristic to be searched for (part of a word).

9. Comparison tag: Feature in memory that is compared with the input tag.

In an exemplary embodiment of the invention, conductors oriented in X and Y are sequentially pulsed on a magnetic layer in such a way that the whole is operated as a content-addressable memory. The layer is made up of a rare earth orthoferrite, for example. The conductors are organized, for example, in groups that subdivide the memory into operational units yet to be defined, each of which has 54 possible positions for a single-walled domain. By controlled movement of the domains as well as by interactions between them, logic operations can be carried out in each of the operating units. The correct order of the field patterns in the magnetic layer causes the logical operations to be carried out and their results to be collected in prescribed portions of the layer, thereby enabling exemplary content addressable memory operation to be implemented. An operation, e.g. B. the receipt of a group of related stored information can accordingly be carried out by pulse trains independently of the information stored in the magnetic material, without having to sense any effects occurring in the layer.

1 shows an exemplary content-addressable memory 10. The memory 10 has a layer 11 made of magnetic material which has a preferred direction of magnetization approximately perpendicular to the layer plane. A first plurality of transmission conductors PYl, PYl ... PYn are adjacent to layer 11 and between a Y driver 12 and ground. A second plurality of transmission conductors PXl, PXl. .. PXn, which for the sake of explanation run perpendicular to the first transmission conductors, is also located adjacent to layer 11. The conductors PX1 ... PXn are connected between a -Y driver 13 and ground. The transmission conductors can be manufactured by well known printed circuit manufacturing techniques and can take the form of interconnected current loops. As an alternative to this, the conductor loops can also be pulsed individually.

The arrangement is flexibly operated to perform numerous functions as can be seen below.

In order to be able to utilize the full flexibility of the arrangement during operation, it is necessary to pulse the transmission lines PYl ... PYn and PXl ... PXn in an appropriately controlled manner. To this end are the X and F drivers are connected to a control circuit 16 via conductors 14 and 15, respectively. The control circuit 16 in turn responds to coded input signals on the input conductors ι in FIG.

A consumer circuit 18 is also with the

connected to control circuit 16 via a conductor 19. The circuit 18 has a plurality of inputs, each coupled to a specific position of the layer 11 in a manner yet to be described are.

Any components that can perform the function intended for them here can be used for the various circuit modules.

A two-dimensional shift register using a magnetic layer accordingly

ao of layer 11 and the transmission conductor and driver was set up and operated on an experimental basis. It assume here that the domains are present in layer 11 and that on the transmission conductors Delivered impulses have pushed the domains into the initially required positions, such as this one will be explained in detail below.

Information is basically single-walled in layer 11 due to the presence or lack of it Domains saved in selected locations. in the The information is represented individually as a pattern of single-walled domains in certain bit storage locations, which are located at a distance from one another are that various logic operations can be performed in between.

The various logic operations should first be combined with the pulse trains to their Implementation are described. Then several of these logic operations are performed Hand of consecutive input pulse trains to receive of all words in the memory that match an input word, as required for content-addressable memories. To the Understanding the various logical operations, however, it seems useful to start by building a to reproduce ner arrangement according to the invention, this structure is described as the basis for explaining the logic operations.

Basic system organization

The arrangement according to FIG. 1 has a large number of domain positions each defined by transmission conductor loops. The transmission conductor winder have such a distance from each other that when pulsing a conductor loop (with the corresponding hurrying polarity) generated magnetic field in one into one adjacent conductor loop attracts the domain, which means that it is a Lester loop moved. The conductor loops are connected to one another in the manner described below are pulsed in a three-phase manner in order to Move domains in the selected direction zi. Such connected to each other Loops are partially shown in Fig. 2 and defl in this way rename the individual domain positions. Last are simply shown as blocks in the drawing and are also referred to below as. SSe are arranged in rows and columns The transmission! head, interconnected and along the lines

len oriented conductor loops are denoted by H (horizontal) and those that are oriented along the gaps in the block are denoted by K (vertical). Nine K-lines KlI to V9 are shown. Each representative line, which is summarized in the drawing by brackets, has three different groups of interconnected conductor loops Pl, Pl, P3 , as shown in the conductors // 6 and Kl. The group Pl couples the first, cherstellc. Thus, only one domain is normally present in a bit storage location at any given time.

The binary ones and zeros are selectively moved by pulses on the transmission conductors. A transmission pulse on a transmission conductor creates a (positive) field that faces the reader is directed at each of its conductive loops. Did-

Designations of the blocks from left to right along the line // 6 are H6P3, which then again repeat // ^6/5 I, HDPL, the designations. Jesolchc domain can take the position of any block in FIG. If a domain is stored in one of the two blocks K2P2, which are also coupled by a conductor HSP2 or H2P2 , and a domain is missing in the other of the blocks at the same time, this represents a binary one or a zero. The assigned lack of a domain (not shown in Fig. 2) is shown below by a circle without an inserted plus sign (see. Fig. 3).

fourth etc. block; the group P1 couples the two 10 Each group of 1K blocks, such as those in the table th, fifth, etc. block; and the group P3 couples and is shown in Fig. 2, corresponds to a bit storage

the third, sixth etc. block, and / was read ~ '"- ^K1 - ' ¹ ^ ....

from left to right for line Hd or from bottom to top for line KI.

Each block can be identified by the transmission conductor and by the phase ( P1, P2 or P3) coupled to the magnetic layer on this block. For example, the blocks are coupled from bottom to top by the line Vl

are, with Kl Pl, Vl P2, Vl P3, after which ao neutrally the positive field will then repeat the block designations only within the Leisich. The loop generated along the pulsed conductor.

Outside the loops there are negative fields that point away from the reader. A single-walled domain is therefore subject to a field gradient,

the block is, of course, two lines that create a shift in this domain, and arranges and can accordingly designate a positive pulse on a transmission conductor in two ways be net. The table below shows the designations used to identify such a gradient for each block in a group of witnesses. A pulse on the conductor K2P3 shifts eighteen blocks in area 1 of FIG. 2. The memory then either the stored one or the saved the names of these two buttons zero by one block to the corresponding prayers uniquely identifies a block in these drawn blocks.

Group of 18 blocks. Similarly, an impulse shifts on the

Head K3P2 each binary digit one block to the right. However, a pulse on the conductor H1P3 shifts only one domain in a block H2P2 the table to the right, while a pulse moves on the lead HSP3 only one domain in a block HSPL right. The transmission circuit can be viewed as being designed to generate a transmission field in any selected block in the described group of 18 blocks. Each group of 18 blocks, which form a bit storage location, has adjacent to it, either in the horizontal or vertical direction, similar unambiguously accessible groups of 18 blocks which form further bit storage locations. Each of these blocks can be designated as explained above, it being recalled that the K lines are numbered from 1 to 9 and the designation of the blocks reflects these line designations. The layer can therefore be construed as being in

// 6Pl
Kl P3 // 6P2
K2P3 // 6P3
K3P3 H 5 pl
V \ P2 HSPl
VlPl H5P3
K3P2 // 4Pl
KlPl H 4 pl
VlPl H4P3
V3P1 // 3Pl
Kl P3 HiPl
Vl P3 H3P3
V3P3 HlPl
VlPl HtPl
VlPl St. P3
V 3 pl HlPl
VlPl HlPl
VlPl St. P3
V3P1

Groups of 18 blocks are organized, each group comprising a bit storage location.

A basic surgical unit can be on hand

As a result, a group of unambiguous correspondences between the various imaginary blocks of a group of 18 blocks (FIG. 2) and the _3a buffers can be defined. When the H and V transmission is present here, the system structure described will normally couple blocks. not all bit storage locations used for storage

Such a group of 18 blocks is now defined. At this point it is appropriate to assume that £ a bit storage location in which the presence and the magnetic layer of FIG. 1 are missing lines and spaces a domain has one or the other bit storage locations arranged in binary 60. Ir

Fig. 2 are the columns with I, II, III, I, Π _etc. denotes for adjacent bit storage locations in a bit storage location line. Only the bit storage locations in columns I are used as areas for permanent in-

This seminal direction is used as the negative direction 65 formation storage. The remaining bits assumes then one towards the reader to storage location columns are for operations on the ii magnetized single-walled domain reserved by one of a column I stored binary values a plus sign surrounded by a circle. A basic unit of operation for the exemplary egg

609620/98

worth representing. If you have a magnetic
Layer begins whose preferred direction of magnetization is perpendicular to the layer, and if one
the magnetic saturation of the layer in the

Structure can accordingly be defined as one Row of three groups of 18 blocks, one in each of columns I, II, IN, as shown in FIG. The representative // and K lines of the Fig. 2 can therefore be understood as corresponding to the basic unit of operation.

All similarly labeled blocks in bit storage locations along a given row or column have similar fields generated therein when the transmission conductor coupled to the magnetic layer in those blocks is pulsed. It should be noted that in Fig. 2 the designation for the bit storage location columns is repeated, which means that the basic unit of operation repeats along any given bit storage location line. The vertical conductors V associated with a basic operation unit are numbered 1 to 9 in FIG. 2. Thus, along any given line of bit storage locations, many vertical conductors have the same designations. For exemplary operation, it is assumed that all identically labeled vertical conductors are pulsed in parallel. Similarly, the horizontal lines associated with a basic operation unit are numbered I through h. Accordingly, along any given column of bit storage locations, many horizontal conductors have the same designations. For exemplary operation, however, it is assumed that like-labeled horizontal conductors are pulsed individually.

The 18 blocks of a bit storage location can be understood as subdivided into two cells of 9 blocks each, e.g. B. one below and one above a double line in column I of FIG. 2. The group of 9 blocks above the double line in each bit storage location is designated as cell C1, and the group below the double line as C2. The cells Cl and Cl therefore together form the bit storage location designated BLW in FIG. 2. If a domain (FIG. 2) is present in cell C1 but not in row C2, then a binary one is stored in bit storage location BLW. If, on the other hand, a domain is present in cell C2, but not in cell C1, then this is regarded as a storage of a zero.

The cells of a bit storage location can be arranged in either of 2 orientations. Fig. 2 shows a cell C1 and a cell C2 which are arranged vertically to one another. Such an arrangement is called Type A. The other arrangement in which the cells Cl and Cl are horizontally adjacent to each other is daigestellt in Fig. 3. This arrangement is called Type B. 3 shows the arrangement of type B in an abstracted form, with only cells C1 and C2 separated by a double line being shown without blocks and transmission conductors. Both a one and a zero are shown as the arrangement would be if adjacent bit storage locations contained the indicated information. A clockwise rotation of 90 ° of each representation in FIG. 3 shows the correspondence between type A and type B very easily. There will still be an opportunity to change the information format from type A to type B during the operating mode described below, and it simplifies the whole thing to understand the two-cell symbol as a domino in this context.

The various logic operations will now be described using the above system structure will. It is important to note that these operations have four fundamental physical properties Steps. In detail, a domain is moved, canceled, i.e. H. extinguished, and divided into two domains. Also, two domains repel each other, each time attempted Collision between them. These steps are explained in the individually explained.

Logic operations
Duplication (Figs. 4 to 7)

In order to perform logic operations, a duplicate operation is first required, which results in a Duplication of information stored in memory results. Fig. 4 shows two adjacent groups of 18 blocks, i.e. two adjacent bit storage locations. They are arranged and labeled in columns 1 and II, as shown in FIG. Each bit memory

jo cherstelle contains a cell Cl and a cell C2. The storage of a zero is associated with an empty circle in cell Cl (missing domain) assigned circle with a plus sign in cell C2 (existing domain) of column I

J5 represents. The binary digit representation shown is shifted by one block column to the right by a pulse on the conductor V3P1 which generates (+) transmission fields in the blocks of FIG. 4 which are provided with only a plus sign. Respond to this

Accordingly, the information moves into blocks HIP3 and H5P3 (FIG. 5). According to the assumed arrangement, fields are also generated in other blocks when pulsing. However, these are not required for the description of the various logic operations and therefore do not need to be taken into account. Next, pulses are applied simultaneously to conductors VIP1 and V4P1 , which generate the (+) transmission fields as shown in FIG. Under the influence of these fields, the respective domain of the numerical representation splits into two domains each, which then move into the positions according to FIG. So there is a split of digits. A pulse is then passed to the conductor VS Pl , which generates the transmission fields indicated by the plus sign in FIG. Fig. 7 shows the resulting arrangement of the binary digits. The binary digit originally only present in one bit storage location in column I now also appears in an assigned bit storage location in column 2, and is therefore duplicated.

It can be seen that the duplicate operation is performed on transfer fields that are concurrently in Blocks are generated on either side of a binary digit. The operation is basically that of one

Information shift. But if there is a field with the same sign on both sides of a binary digit generated for information shifting, the binary cipher is subject to a Constriction. It should be remembered that a binary

6 "digit by an existing in a first position and a missing domain is shown in a second position. To simplify the explanation, an agreement must be made that every binary digit is made up of two digit elements, by

where one is an existing domain and the other is a missing domain. The constriction requires then that each digit element is split up. This is a matter of course for a missing domain.

borrowed no problem. From an existing domain however, it is believed that it initially changes shape to an oval during the partitioning process and then in a dumbbell shape before the domain because of the around each positive transmission field generated negative field. Under certain circumstances, an additional negative field on the necked part of the jacket to promote the division. However, such are additional negative fields largely unnecessary. Understanding the nature of the process of dividing a domain is however, not essential to an understanding of the present invention. Suffice it to say that the Division of a domain observed for the generation of transmission fields on both sides of the domain will. Typically the fields to accomplish such a division are larger than one ordinary transmission field that is of the order of a few oersteds for most suitable magnetic materials, as will be explained below.

Inversion (Fig. 8 to 13)

The inversion operation reverses a binary digit. If, for example, a binary one is represented by a domain in a block HSP2 and by the lack of a domain in a block H2P2 of a bit storage location (see FIG. 8), the inversion operation leads to a domain in block H2P2 and to a missing domain in block H5P2 (see Fig. 13).

The operation is carried out by generating a pulse train that carries the domains (and also their lack of them) from one position to the next. This can be done in a number of ways. For example, the pulse train shifts H2P3, V3P3, V3P \. K3 / '2and // 5 P2 a domain (or lack thereof) from block V2P2 (or H2P2) to block H5P2. The pulse program HSPi, ViPl, VXPi, V \ P2 and «2P2 simultaneously shifts a domain (or the lack thereof) from block H5P2 to block H2P2.

Figs. 8 to 13 show the sequential ones Results of the individual steps of the inversion operation. Each figure contains plus signs that represent the Show fields for effecting the next shift. A comparison between FIGS. 8 and Figure 13 shows that an inversion has actually been created.

AND operation between two binary digits

It should be repeated that each binary digit is represented by a first digit element in cell C1 and by a second digit element in cell C1 . Corresponding cells C1 in two adjacent binary digits include the presence or absence of a domain, and those binary digit elements are located in blocks HSP2 (see FIG. 2) which are separated from one another by two intermediate blocks. Similarly, each of the cells C2 of adjacent bit storage locations includes such a digit element in a block H2P2 , and those blocks are also spaced two blocks apart. For the sake of simplicity, it should be agreed that when both elements of a binary digit are meant, they are described as either taking up "positions" or being pushed into the same. If only a single digit element is meant, the block drawing is used.

The AND operation between two binary digits involves the initial shifting of those digits into two Positions separated by an intermediate position. The digit elements in neighboring, equal designated cells are accordingly pushed together by one block. The operation includes cine pulse train in the two positions as well as in intermediate positions. The first and second positions are specifically defined as positions formed by first and second binary digits, for example of type A (see FIG. 2), which are separated from one another by a block column, can be taken. The intermediate position refers collectively to the two blocks of the middle block column that contain the elements separates the two binary digits.

The operation between the digit elements in adjacent cells C1 is dependent on the operation on the Digit elements in neighboring cells C2 are different. A transmission field is used for neighboring cells C1 generated to push domains (or lack thereof) into the intermediate block. When two domains are present, only one moves into the intermediate block excluding the other, because of the mutual repulsion between two neighboring domains. Next a field of a sign is created in the intermediate block in order to delete any domain that is present here. A further transmission field is then generated in the intermediate block in order to transfer the in to move any domain remaining to the adjacent blocks of the first or second position. It it is clear that a domain occupies the intermediate block if and only if there is a domain in each of the neighboring cells Cl was present and therefore as the result of an AND operation between neighboring cells can be perceived.

However, the AND operation between the binary digits themselves is not yet complete; because it muli the domains (and their lack thereof) in cells C2 of those digits can also be acted upon. A transmission field is generated in the corresponding block of the intermediate position for this purpose, and in turn, only one domain (if any) moves in response to this, into the intermediate position. In this case, however, fields of a sign (negative) are used for domain cancellation in the adjacent blocks of the first and second positions instead of in the intermediate block. Was a domain originally in one of the assigned blocks of the first or second positions, one is occupied Domain the intermediate block at the end of the pulse train. Insofar as a domain occupies the intermediate block, when at least one of the associated blocks of the first and second positions is initially from a domain was occupied, the operation can be considered an OR operation between two neighboring ones Cells C2 are perceived. The AND operation between two adjacent binary digits can then

60. be understood as an AND operation between the cells C1 of these digits in conjunction with an OR operation between the associated cells C1 of the digits.

a) AND operation between two cells
(Figs. 14 to 18)

The AND operation between two cells will now be described using a specific example.

Nine arrangement in the bit storage locations of columns I and II corresponds to a zero for column I and one One for the gap part (Fig. 19).

The operation starts initially in the same way as the AND operation between two cells, and in fact the same set of vertical conductors up to that of Figure 16 can be used for this AND operation appropriate phase. This can be seen from a comparison of Figures 14 and 19 and also

15 and 20. A comparison between the Figures 16 and 21 show that a domain is the intermediate block occupied in every Fah. It can be seen in the OR operation between two cells, that a domain is present in the intermediate block if a domain is either in column I or in column II was initially present.

However, the wiping step is different for this OR operation. As in Fig. 21 are shown, erasure fields are not

'ίο' s block is generated, as is the case for the AND operation between two cells, but in the assigned blocks of adjacent cells C1 in columns I and II Leaving fields one and only one domain in the intermediate block if a domain was initially present in one of the two cells C2 or in both cells. Figure 22 illustrates the shift of this domain into the center block of cell C1 in column II, which is the normal position for storage in column II.

Table II below is well known in the language of logical operations:

After this - see FIG. 14 - a domain is stored in cells C1 of columns I and II. This AND operation, illustrated in Figures 14-18, can be briefly described as follows: Vertical conductors VAPI identify the selected block column which contains an intermediate block in which the eventual element is stored. The result is that a domain is only left in this intermediate block if domains were initially present in both cells C1 in columns I and II (FIG. 14).

The pulse train for the AND operation between two cells comprises several steps, the main being the erasure of one domain and the placement of the remaining ones in the intermediate column. As can be seen from the description below, it does not matter which domain is deleted. According to FIG. 15, which shows a specific detail, a pulse is applied to the conductor VAP1 in such a way that an attractive field is generated at the block VAP1 , as shown in the figure. Only one of the two domains moves into the intermediate block, the other is excluded from it because of the repulsive forces that exist between adjacent domains during an attempted collision.

It is conceivable that specially symmetrical positions lead to a situation of unstable equilibrium in which neither of the domains would fully enter the intermediate block, but rather both only partially. However, this unstable equilibrium has not been found to be of practical importance and was never actually observed: The possibility of such an equilibrium can nevertheless but avoided by slightly changing the symmetry of the transmission conductor geometry, for example in that the driving current loops are not made exactly circular.

The result after which the domain of column I has moved into the intermediate block is shown in FIG. This domain is extinguished by generating a negative field in the intermediate block via a pulse on the conductor VAP1. This field is represented by the minus sign in FIG. It can be seen that if the domain of column II in Figure 15 had initially moved into the intermediate block, it would now have been erased.

A (positive) transmission pulse is next fed to the conductor VA Pl (FIG. 17), so that the remaining domain is transferred to the block VA Pl (FIG. 18).

From the above it can be seen that a domain appears in the intermediate block if and only then when domains were originally present in each of the cells C1 in columns I and II. When nvir a domain was present it would be resolved by the operation described in connection with Figs extinguished so that there would be no domain in the terminal position.

b) OR operation between two cells (Fig. 19 to 22)

The OR operation between two cells works in such a way that a domain would be left in the intermediate block if there was a domain in one or the other. The table shows that the OR cell was present. This is explained in FIGS. 19 to _{5, the} operation between two binary digits 22 for a special case in which one is effective to generate a binary one when there is at least one one domain in cell C1 of column I pending. Such an operation is absent in cell C1 in column II. This domain is realized between neighboring binary digits

Table II

AND

Entrance II
0

Entrance 1

0 1

0 0

The table shows that the AND operation between two digits is effective to generate a binary one only when there are two ones. From FIGS. 2 and 3 it can be seen that the information processed as described leads to results which match the table when an AND operation is carried out between neighboring cells C1, and an OR operation between neighboring cells C1 .

OR operation between two binary digits

Table III below is also readily available in the language of logical operations
of course:

Table III

OR

Entrance II
0

Entrance I.

0 1

/ IO

by performing an OR operation between the adjacent cells Cl of these digits and an AND operation between the associated cells Cl. It can be seen that the operation is the reverse of the AND operation, as can also be seen from a comparison of Tables II and III.

In performing the various logic operations, it is necessary to generate certain fields in the various blocks of FIG. Any such field can be generated by a pulse on a conductor H or V. The particular conductor selected to be pulsed in a particular operation is determined by the action of a pulse applied to that conductor on the other bit storage locations along that conductor. Correct selection of the conductors allows for a certain economy because, for example, when an AND operation is carried out between two digits, both an AND and an OR operation between two cells can be carried out at the same time, since they - except for erasure steps in these operations - require the same impulses. Useful circuits are accordingly arranged in such a way that the same operations are carried out along one coordinate conductor for the sake of economy, as well as erasure operations along the other coordinate conductor in order to influence only identically designated cells of different bit storage locations accordingly.

The basic structure of an arrangement according to the invention has been explained above, as well as a number of possible logic operations that can be performed with this arrangement. It an exemplary content addressing that includes some of the mentioned logic operations can therefore now be explained includes.

As will be seen, this content addressing will include familiar functions. First, a Duplicate representation is created for each word in memory. Second, this duplicate is acted upon, in accordance with the supplied comparison character, referred to as "input tag", for generation of compliance and non-compliance indications. Third, all match indications and associated stored words made available. All operations are selected simply by creating fields in Blocks of different bit storage locations executed, with these fields for shifting the domains serve from block to block or to erase domains in selected blocks.

These general functions can be converted into consecutive logic operations, it gives The following exemplary operation is therefore:

1. The duplication of all the words in the memory is of course carried out by the duplication operation. Since all bits of all stored words have to be duplicated, the vertical conductors V are used for this operation. Since only the bit storage locations in columns I are used for storage, the duplication operation returns the duplicate words in the assigned column H.

2. To generate the match and mismatch information, the duplicate words are moved, for example, to a separate part of the memory where the operations acting on them do not disturb the stored information. For this purpose, 1 ^ conductors are used to transmit the information along the columns II in a separate logic part. It can be seen that H- conductors can be used to act on information in columns II in the logic part of the memory without destroying the associated information in columns I of the original memory part.
An inverting operation is then carried out on the information in column II in the logic part with the aid of pulses on W conductors.
It should be noted that the inversion operation is performed in response to an external signal. In this case, the signal is the input tag that determines the first group of binary digits for which a comparison is desired. It should be understood that these digits can be any group of digits in a word. This input signal selects the correct W conductor in the logic part. In response to this signal, the content of each of the selected bit storage locations in each word is shifted into an assigned column IN, where it is inverted for the sake of simple programming. The programming for the inversion operation does not need to be set to the corresponding input tag, as this is an operation that is invariant to the input tags. After the inversion operation has been completed, each inverted bit is transported back into the assigned column II with the aid of pulses on Η letters.

Each column II in the logic part contains a binary word at this point in the operation. However, only those words that have a comparison tag that matches the input tag all contain binary ones. The bits in column II are rotated from type A to type B to perform AND operations between adjacent cells in column II and between adjacent cells in column III. Successive AND operations of this kind provide a domain indicative of the match in a column H only if each cell in the corresponding column has a domain. A match is indicated by a word containing all ones. When such words are rotated into Type B form, column III does not contain domains.
3. For each match between the comparison tag of a stored word and the input tag, a single domain is present in the assigned column II of the logic part in the cell C1, for example the first bit storage location. Successive duplication operations are then performed over the // ladder to create domains in each cell of column II that are associated with the comparison tag. Of course, each duplication operation alternates (or concurrently) with appropriate transfer fields in order to correctly position the last duplicated domain. When all cells are occupied in this way, the domain groups of columns II are transferred to the assigned columns III. It is essential to note that every cell in the logic portion of Columns III is now

609 620/98

has a domain. After that, a continuous sequence of domains appears in column III of the logic part generated the corresponding words in corresponding columns I of the memory part assigned.

The words stored in the memory section are then duplicated and transferred to the associated ones Columns II of the logic part moved to align with the consistency and Receive non-compliance indications. AND operations are then between associated with the content in cells of columns II and the content in corresponding cells Column III executed. It can be seen that all matching words keep and all mismatched words are eliminated.

The desired result is that only those stored words which match Tags are available in the logic part. This is achieved in response to an external signal, that specifies the input tag in such a way as to provide an inversion of the corresponding bits of the Effect comparison tags. The external signal naturally controls the W-conductor, which contributes this operation can be controlled. In the operation explained, this is the only time where the operation is effected directly by external signals. It is not a reading of the result any operations required to perform the remaining logic operations that lead to elimination of all mismatched words and to keep all matching words lead, occur on the basis of a predetermined assigned pulse train, such as this one is described.

Exemplary operation as a content-addressed memory

FIG. 23 shows part of the layer 111 of FIG. 1, where each of the first and second binary words are represented by consecutive "dominoes" which are arranged from top to bottom in the type A shape of FIG. Only 2 words are given and only the comparison tags of those words are shown. In detail, the first 3 (upper) bits each word can be understood as the comparison tag of each of these words. Assume that single-walled domains initially created and then slid into the positions shown.

Figure 2 shows a row of bit storage locations in which each bit storage location is in a bit storage location column is arranged. The columns are labeled I, II and III, after which the drawings are repeat from left to right as explained above. Neighboring binary words (see 23) are in successive bit storage locations from top to bottom only along columns I. saved. The next adjacent stored binary words then take bit storage locations in bit storage location columns one, which by two columns corresponding to the assumed basic unit of operation are separated from each other.

Fig. 23 shows only the comparison characters of each word, hereinafter collectively referred to as the comparison tag while the remainder of each word is not shown. The comparison tags of the words and 2 are (K) I and 100, read from top to bottom in each column I, for the left and right respectively. right column.

The various logic operations are illustrated by the domino symbol in FIGS. 2 and 3 the explanation of the exemplary content addressing

5 operation shown. The pulses for carrying out the various logic operations are provided via the Y and ^ drivers 12 and 13 of FIG. 1 under the control of the control unit ί 6. For this purpose, the transmission lines PYl ... PYn

ίο and ΡΧΛ ... Arn of FIG. 1 correspond to the transmission conductors of FIG. The designations used in connection with FIG. 2 ″ allow a simple description of the exemplary organization according to the invention.

Duplication operation

The first logical operation in the content addressing operation is to assign all stored words duplicate. The result of such an operation is on

ao the comparison tag of words 1 and 2 is shown in FIG. You can see that the comparison tag in the each assigned column II is repeated.

The pulse program for duplication is as follows: First, a pulse is applied to conductor ViPl which causes the presence and absence of domains (ie, digit elements) in the binary digits of column I of FIG. 23 to be shifted one block to the right . Second, a pulse is applied simultaneously to each conductor K2P2 and K4P2 in the memory portion of the memory, resulting in the actual duplication as well as the return of a group of digit elements to the original position of the corresponding columns I (Fig. 24). Third, a pulse is provided on conductor VS P2 .

to move the newly generated digit elements into the correct positions in the middle block column of column II to shift (Fig. 24) These three consecutive field patterns complete the duplication operation, as has already been described above in connection with FIGS.

Shift to the logic part

FIG. 25 shows the duplicates of the exemplary comparison tags located in columns II, the original binary digits in columns I not being shown. It is now useful, but not necessary, to move the duplicate digits to a different logic part of layer 11. The information is shifted by simply successively pulsing the conductors KSfI, VSP 3, VSP 2, KSPl ..., with columns II of the layer being operated as (vertical) shift register channels. The integrity of the information is of course maintained. FIG. 25 can then be interpreted in such a way that it represents a logic part of the layer II which is situated opposite the position of the original information in such a way that it can be reached by the shift pulse program just described.

Inversion operation

The next operation is all bits of the compare tags invert to positions that are the relative positions of zeros of an assumed input tag correspond. Assume that 001 is the entry tag. The first and the second bit of the comparison tag of each word in the memory are inverted in response to an external signal which is transmitted via the

Control circuit 16 of FIG. 1 determines which H- conductors are driven for this operation.

• The first step in the investment operation is the binary digit in each of the first two bit storage locations of the comparison tag of all stored To move words in the logic part of the memory to the right, from column II to column III. Fig. 26 shows the results of such an operation for the words stored as an example to the assumed one Day of one day. The first word, the left one, contains 2 zeros in the first two bit storage locations. Consequently, the domains as well as the associated missing domains that have these zeros move one column to the right into column III, where they in turn represent zeros (see Fig. 26). However, the second word contains a one and a zero in the first and second bit memory locations, respectively. which can now also be found in column IH.

The pulse program for shifting the binary digits of the first two bit storage locations from column II (Fig. 25) to column III in the logic part (Fig. 26) is as follows: First, the conductor HI P3 is pulsed. In response to this, each domain in a block HIPI of column II is shifted one block to the right. Next, the H5P3 conductor is pulsed. In response to this, each domain in a block H5 P1 of column II is shifted one block to the right. Subsequently (or at the same time) the conductors HIPI, HSPL and then HIPI are pulsed in order to shift the displacement of these domains from the positions in column II to the corresponding positions in column III, as shown in FIG. The information is now in a column where it can be inverted without other stored information that is not to be inverted being disturbed.

The actual inversion operation is then only performed on the information contained in the Column III is in the logic part. It consists in the mutual exchange of the existing domains and missing domains in the two cells of each bit storage location. Therefore, if a domain is in a Position is to represent a one in a considered bit storage location, this domain is in the "0" position is transferred and at the same time the missing domain in this position is moved to the "I" position convicted. This operation is shown in Fig. 26 by the dashed arrows.

The result of the inverting operation is shown in FIG. A comparison of FIGS. 26 and 27 represents the inversion of the information in column IH.

The information in column III is then transferred back to the corresponding column II (FIG. 28). This operation is accomplished by an impulse program with impulses on conductors HIPL, HSPl, HI P3, HSPi, HI Pl and HSPl. The inversion operation is now complete.

Conversion of type A to type B.

Next, it is desired to perform AND operations between the digit elements in corresponding cells in 6 adjacent binary digits of a bit storage location column. For this purpose, it is convenient to convert the form of the information from type A (FIG. 2) to type B (FIG. 3). A simple rotation of the digit element in one cell by that in the other of each binary digit brings about the change, as shown for each ZMier by the dashed arrows. The resulting B-type shape is shown in Figure 29, with the domino symbol with dashed lines for better reference

is drawn for the sake of It is confessed that the broken lines in Fig. 29 are mere imaginary lines and are only used to pair up the presence and absence of domains. The Impulse program to obtain this result

summarizes consecutive pulses on ladders St. P3 HlPl, HlPl, K8P3, V8PI and VSPL.

Successive AND operations between
Digit elements

Fig. 29 shows the arrangement of the stored comparison tags, taken as an example, when a AND operation is initiated between two digit elements. A comparison between Figs. 29 and Fig. 2 shows that the digit elements of the digits in

so Fig. 29 are in blocks H5P1 . First, the elements of the digits in each binary digit third (from the top) are moved each comparison tags into blocks H3P1 which are removed to a position of the appropriate number of elements each second binary digits (Fig. 30). The pulse program for performing this operation is done with pulses on conductors H6P1, HIPI, HIPI and H3P2. Only the // conductors coupled to the positions that are assigned to the respective third binary digits are pulsed at this point in time.

The AND operation between adjacent digit elements is initially carried out with a pulse on the conductor HAP1, which corresponds to the intermediate position in FIG. The arrangement of the domains as a result of this pulse is shown in FIG. For purposes of explanation, it is assumed that the third binary digit (domain) in word 1 is shifted to the intermediate position, excluding the second binary digit (domain). It should be noted that for the second and third binary digits in word 2, no domain is excluded in this way, and the result of this operation is that one domain from each digit shifts to the intermediate position (see Fig. 31). After that an impulse becomes one of them

The sign supplied to the corresponding conductor HAPl that the domains are erased in corresponding blocks HAPl. A pulse is then fed to the conductor HA Pl , which transfers any remaining domains to the block HAP1 .

It can be seen that AND operations are performed simultaneously on corresponding digit elements of the respective second and third binary digits are executed. The results of the operations are shown in FIG. A domain remains for word 1; for word 2 there is none. The first binary digit in each case The operation does not change any word, as can also be seen in the figure. The concurrent AND operations are now between the digit elements of the first Binary digit of each stored comparison tag and the corresponding result of the just described AND operations repeated. Again, the operation requires the postponement of the Digit resulting from previous AND operations moving up to a position by one position from which the first binary digit is removed. The arrangement of the number elements in the various Stages during this operation are shown in FIG. 33

/ 15

and 34 shown. Only a single digit element remains as a result of the operation (Fig. 35). The The pulse program for obtaining the second AND operation is completely analogous to that used for Execution that was first described.

A domain only becomes a domain if a stored comparison tag matches the input tag appear in the position according to FIG. 35 in a column II.

It can be seen that the AND operations, for example, fields in second and third bit storage locations, but not in the first bit storage locations, and vice versa. For one Complete flexibility in this regard is, for example, an individual driver for each H-conductor intended. As will be explained in detail below, are more economical organizations possible. It is essential that the AND operations between corresponding digit elements in next adjacent binary digits are executed in each comparison day until a single Digit or none remains for each stored comparison tag, like this one for the words 1 and 2 in Fig. 35 is shown.

For example, if the binary number one remains, a match is displayed. Missing a one mismatch is displayed.

If there is a one, then a domain is positioned in the corresponding block H5P2 in the assigned column II. Accordingly, the information indicating alW * matches in memory is also made available in memory. Let us now explain how this information is organized into a useful form.

Before doing this, however, remember that the choice of example was random. Because z. For example, if a stored comparison tag has been written which is the reverse of the input tag, a null representation (a domain in a column III) would be left in the position assigned to this word in FIG. This is of course of no consequence in the present operation, since the presence of domains in Column III is not representative of matches and can simply be canceled by applying a pulse to the conductors VHPZ under the appropriate sign.

Elimination of mismatched words

There is now a digit element in column II for each comparison tag in the memory that is identical to the input tag supplied, but the words that do not match have to be eliminated in the memory. The procedure is as follows: The domain shown in column II of Fig. 35 is duplicated five times in a manner as described in connection with Fig. 5 to include all cells in the bit storage locations of the comparison -Tags to fill. (In practice, as many domains are created as there are cells in a stored word .) When the additional domains are created, they are pushed down in FIG. 35 to positions shown in FIG. 36 for the first two additional domains and in 37 for five additional domains are also shown for the original domain. The pulse train to obtain this result is as discussed in connection with Fig. 5, this pulse train being applied along with a basic transmit pulse train to shift any additional domain down as it is generated.

Next, the correspondence information in column II (see Fig. 37) is shown in parallel transferred to column II (see Fig. 38). The pulse sequence for this is not described in detail, since they are similar to the one specified for other operations

xo Hch is.

Duplication of all words

Next, each word is duplicated in memory as described in connection with FIG the binary digits are regenerated, which in this figure only applies to the comparison tags are shown. The words (see column II of FIG. 24) are then again entered into a logic part of the Shifted sheet (see Fig. 25), as this in verse

ao binding with FIG. 25 has been described. The resulting arrangement of domains is in columns 29 for the comparison tag of each word. The impulse programs to run these operations are completely analogous to those described above.

There is now a duplication of each comparison tag (and an associated word) in memory in a Column II of the logic part is present (see Fig. 39). It is also a continuous one in adjacent columns III Series of domains or, alternatively, of missing domains as an indication that whether each stored comparison tag is the same as the input tag.

There is now an AND operation between the digit elements in the cells of each of the comparison tags in columns II and the corresponding match indications (domains) in the next adjacent columns III executed. There is no need for a previous transformation from type A to type B as shown in Figs. In the present case, because the information to be processed is located in the next adjacent block columns and not in one Block column is arranged vertically, as was the case earlier.

AND operation between digit elements

40 shows the digits in column II which have been shifted one block column to the right before the actual AND operation. Fig. 41 shows the result of the AND operation. The arrangement of the domains in FIG. 41 is identical to that represented by the comparison tag of word 1 (see FIG. 23). No digit of word 2 remains, as shown in FIG. 41 . Accordingly, only matching words appear in the logic part of sheet 11. Non-matching words are eliminated. Of course, when each binary digit is generated in a comparison tag , the entire corresponding memory word is generated, whereby only the information is available which is assigned to the stored comparison tags which correspond to the input tag.

The basic logic operations and their

Uses to obtain the familiar content addressing function are now described. The use of the information in the form provided by such operations is within the skill of the art

also familiar. For example, may be desired be to bring the information associated with a particular comparison tag up to date. The new information can be introduced into the logic part of the layer and along columns of bit storage locations in the logic part of layer 11 (Fig. I) in Positioning! be pushed to the position of the corresponding to changing word. Then the changes are made in a manner similar to the one above corresponds to the described, logic operations are also carried out if necessary. Alternatively the words that match the respective input tag can be stored in a parallel way in Shift register channels can be viewed, from where they are then put into starting positions Sampling can be transmitted by the consumer circuit 18 of FIG. 1, which is a printer can be. The latter selection alternative takes place with the help of ladders that lead to those starting positions are coupled, as indicated by the inputs to the consumer circuit 18 in FIG.

The basic structure of an arrangement according to the invention requires a magnetic layer and transmission conductor along with input and output assemblies. As has been further explained, a complete set of logic operations in this structure are accomplished with appropriate pulse trains on the transmission conductors. It has also been described that successive pulse trains enable the implementation of various familiar functions, as has been explained using an illustrative content addressing operation. For the relevant One skilled in the art should understand that implementing a complete set of logic operations also enables the implementation of all computer operations.

At first sight it appears that the structural simplicity achieved at the expense of complication the control and driver circuits has taken place. This is not the case. Layer 11 is perfect able to save micro-logic sequences or sub-programs in a specific part. Such a micro-logic sequence can be in the form of successive ones There are binary words that are stored in parallel shift register channels. As can be seen there is no need, by external means, of the stored in these microphones Read out information. Performing a logical operation would then be essentially nothing more than require the classification of such micro-sequences in terms of input signals. Not just classification of microsequences is a relatively simple matter, but also a driver circuit based on a such a consequence can be carried out relatively easily being.

But consider FIG. 2 again for a moment. Basically there are 6 // conductors and 9 F conductors required to achieve all of the operations described. Each of these conductors has 3 phases, consequently 45 separate conductors are coupled to the blocks of each base unit in the array. The same named K-conductors are shared. Assume that each // ladder has a separate Driver required. 42 then shows a simple scheme for sequencing the drivers to accomplish the exemplary operation.

Fig. 42 shows part of the layer 11 or, alternatively, a separate layer which is a part the control circuit 16 of Fig. 1 forms, with one Define a plurality of shift register channels 56 to 56 " are. Such a shift register channel knows

Transmission means for moving the domains along the channel from left to right. For this Parallel transmission operation can use additional transmission conductors along with suitable drivers (not shown) can be used. Domain patterns are in parallel in each Channels saved.

Heads AHiPl ... AV9P3 are coupled to the starting positions in corresponding channels, each of which responds to the passage of a domain,

in order to activate the correspondingly designated transmission conductor via assigned amplifier A.

The corresponding domains in each channel are simultaneously advanced to the starting positions, thus forming a binary word in a stored micro-sequence. The micro-sequence for the duplicate operation will now be explained. The operation is carried out first with a pulse on conductor K3P2, followed by pulses on conductors V2P2 and V4P2, and finally by a pulse on conductor VS Pl. The duplication sequence then contains three consecutive binary words, each of which contains a domain or domains according to the transmission conductors to be pulsed. These domains are again shown in FIG. 42 by plus signs provided with a circle.

Means (not shown) are also provided to transfer domains into the corresponding channels re-enroll after they have been read. Such means expediently have an electrical one or optical pickup at the exit end of each channel to capture a domain on The input end of each channel is generated whenever a domain is in a starting position arrives.

An additional transmission channel PIC , as shown in Figure 42, is provided for shifting an additional domain in each binary word to control the polarity of the pulse applied to selected transmission conductors, such as required to perform an AND operation between adjacent cells is. The additional channel is coupled by a control conductor CHVi. A conductor is coupled to each of the amplifiers A through an amplifier A. To this end, a switch is provided in each amplifier A which is responsive to an indication of the presence of the additional domain to determine the state of the switch and hence the polarity of the pulse intended for selected transmission conductors. This operation can be viewed as a pulse inversion operation, whereby a domain in a pulse inversion channel, PIC, is a reversal of the normal pulse polarity of the im-

pulses causes.

Several of the exemplary logic operations require increased drive currents. For example, the duplication operation requires a pulse whose amplitude is greater than the amplitude of the pulse required to simply move a domain. An additional pulse gain channel, PAC, is provided for this purpose (Fig. 42). An exit conductor CHVZ, who is connected to a

609 620/98

such a channel is coupled responsive to the passage of a domain to activate an amplifier A ". The amplifier A" is in turn with each of the amplifier A of FIG. 42. for example, the gain to increase each simultaneously activated amplifier A. Amplifier circuits which operate in this manner are known.

The sequence for the inversion operation (not shown) expediently has domains around which all bits in a comparison character correspond W-conductor /.u pulse. The external signal which designates the bits to be inverted, blocks all // conductors except the desired ones

When the next following microphones in the same Modes are designed to assign the transmission ladders as necessary to perform the operation pulse, then everything required to carry out a multiple comparison operation, for example, is that is, where the advancement of domains is done to the right in Fig. 42 in response to a first signal, which expediently activates an input to the control circuit 16 according to FIG is.

The sequence can conveniently be terminated by putting a domain in an additional channel (not shown) in order to block a further transmission via the control circuit 16 of FIG. 1, when the presence of this domain is detected at the appropriate starting position. Alternatively an "operation end" micro-sequence can be added to an existing one Channels must be inserted.

Of course, the consequences can be rewritten and / or rearranged to perform various functions. It is then clear that the Sequence of different logic operations determines the function performed and that different sequences in the manner shown in Fig. 42 for selection on an associated input signal / ur control circuit 16 can be saved separately.

43 shows the layer 11 system organization 1 according to the described memory and logic parts 51 and 52, with a further control part 53 is provided, as shown in detail in FIG. The column designations according to FIG. 2 are also available here, as are the control section outputs according to Fig. 42. The logic section 52 has, as shown, Outputs to circuit 18 of FIG. 1.

As described, the basic unit, according to which the memory of FIG. 1 is organized, requires 45 treble conductors, and ideally these are also common to other basic units. Some surgeries may require and in fact this also requires complete flexibility in that different basic units be pulsed while others are not pulsed, as this can also be seen from the exemplary Operation results. Accordingly, the embodiment requires the // conductors to be separate Drivers have. It is of course more economical to minimize the number of drivers. This can be done by keeping the number of // conductors small, ideally to a small number, which is related to the number of bits in a word. Alternatively, the logic operations be arranged in a manner to encourage common drifting of identically named // conductors enable. Such considerations can lead to a reorganization of memory into basic operational units different number of blocks lead. In any case, the most economical organization is through determines well-known considerations and is not described in detail here. However, it is weekly. note that it is not necessary to change the transmission circuit geometry in order to to change the basic unit of operation. All that is required is that the existing ladder be different be classified.

ίο The present description was based on a Information representation in which a domain is in a prescribed position within a bit storage location is present and at the same time in another prescribed position in the same bit storage location a domain is missing. This representation is redundant in that it is a binary one and one Zero also through the presence or absence of a domain in just a single position of a bit storage location represented and so the packing density could be increased; but the various logic operations could then be less easy with the simple uniform coupling geometry the transmission conductor, as shown in FIG. 2, is accomplished. There are indications that

as that an even more extensive redundancy an additional Facilitates simplification in the implementation of logical functions. They are therefore different Compromises between package density on the one hand and simplicity of logic operations on the other possible. The arrangement according to FIGS. I and 2 allows a great deal of variation in this Respect. Because for this it is only necessary to change the transmission pulse sequence in order to complete the whole operation and / or to change the basic unit of operation.

A further simplification in operation can be implemented without changing the basic operating unit already described. For example, could the matching indications are more easily generated when the zero digits are erased before the rotation from type A to type B is performed. In fact, in this case, the Rotation from A to B unnecessary. However, the described operation allows a larger one to be explained Number of logical operations. Again, there are no structural changes to implement the easier operation necessary. It is just a change from that described in connection with FIG. 42 Pulse train necessary.

The invention has been described with reference to transmission conductors having a loop configuration. Such a configuration is exemplary only and there are alternative configurations that include an elevated Enable packing density.

As mentioned above, it is possible to use the various logic operations from four basic ones physical steps to build up. These steps are during the explanation of the logic operations have been given in detail and are summarized as follows: 1. Displacement of a Domain, 2. deletion of a domain, 3. division of a domain and; 4. Collision between domains. Typically, the shift occurs by generating one or two oersteds on one opposite side the location of the single-walled domain offset position and under a sign that corresponds to that of the Domain corresponds. The domain then "sees" itself in front of a potential well and wants accordingly take this position of lowest energy. It fin-

/ Ιί

A corresponding shift therefore takes place when the transmission field exceeds the domain wall movement threshold of the material used.

The extinction of a domain, which in itself is in energetic equilibrium with the surrounding magnetization and is accordingly stable in size Again, requires a field of only one or two oersteds, typically not more than 10 oersteds produced on the site of a domain. However, the field has a sign that seeks to reduce the domain diameter. For complete extinction it is then only necessary to exceed the stability threshold value parameter of the material. '5

Sharing a domain in at least two domains requires higher fields than necessary for the domain shift and domain extinction, this is because the process requires pinching a domain into two domains, and this ^ao two domain walls need to be driven towards each other, to which a field of approximate size 4 _n M _{s is} necessary. Here, M _{s is} the saturation magnetization of the material, which is typically 100 Oersted. ^a 5

A collision between domains as used here only prevents a shift towards a transfer field and therefore does not require one higher field.

In an actually operated arrangement, the triple conductors were expediently arranged in vertical slots in a highly permeable base plate and were not in the form of a separate printed circuit. A layer of Erbnumorthoferrite (ErFeO ₃ ) was placed over the upstanding cones formed by the slits. The various physical steps were carried out as described, using the following driving currents:

Transmission + 150 mA

Extinction + 75 mA * °

Division + 500 mA

Collision + 159mA

The domains were about 0.35 mm in diameter and were slightly larger than the cone size that Was 0.25 mm with 0.125 mm wide slots.

An indication of the achievable packing density, as well as about other operating parameters provides a meaningful identification of the memory organization of Fig. 1. Specifically, domains of the order of 0.125 X lu ^b m are shifted by means of a printed circuit board of 2.5 X 10 ~ ^A m, which gives a packing density of more than H) ⁵ domains per cm ² . Driving currents of about 50 mA are used. The arrangement is able to carry out all comparisons for correspondence in the memory in about 1 msec.

The logic operations described form a complete group with which all computer operations can be implemented. Some of these operations, e.g. B. the duplication operation where division of a domain is necessary requires that the area of the domain be enlarged. In other operations, such as the AND operation between two neighboring cells, the domain area is not enlarged. A complete set of logic operations in which some operations are performed without increasing the domain area and other operations require such an increase are called mixed groups. However, a complete set of logic operations can be formed without any increase in the area of a domain. In these cases a domain pool is provided, for example in each bit storage location, with a concomitant reduction in the packing density of a given memory. Of the basic physical steps, only domain shifting and collision then need to be used. The steps of dividing and deleting domains need not be used in this case. Instead, the domains are kept, and operations, /. B. the duplicate and delete operations are performed on a logical basis, with domains then being borrowed from and returned to a pool.

A typical operation in this mode of operation can be the collision interaction between two domains use. For example, consider two rows of three blocks that form three columns. Everyone The block in the first column is occupied by a domain. The block in the first row, third column is also occupied by a domain. The goal is now to match the two domains in the first column To move blocks of the second column by creating transfer fields in those corresponding blocks. When the domain in the third column is made stationary, it shifts only the domain in the first column, second row in its corresponding block. the Repulsive force between domains in the first row prevents such a shift here. The operation in the first line enables you to form an AND operation / u. The operation in the second Line enables you to form an OR operation.

The wiring geometry, field strength values, coercivity, etc. determine whether the collision interaction effective across a single domain position (block) or across two (or more) positions is.

Operation with domains that retain their shape is possible through an operation area dedicated to the magnetic material used is characteristic. The multifariously shaped domains that normally z. B. are present in orthoferrite layers previously heated to the Curie point, are familiar Appearance. If a bias field with a negative sign is perpendicular to one Layer is applied, the domain shapes change, they become smaller overall. With a certain one Bias field, each domain becomes circular (actually cylindrical) with the radius being one Function of the material and the thickness of the layer. Exceed further increases in the preload then possibly the stability threshold and cause the domain diameter to zero shrinks, so the domain is wiped out. In the case of a pure group of logic operations, that is, where the domains retain their shape and are neither duplicated nor obliterated, become stationary Bias fields used to keep the domains circular. Such a bias field can easily be generated with the help of a permanent magnet.

A complete set of logic functions

29

ru layer easy to determine.

can also be thinned out in a magnetic layer - · _{Invent jsl on the basis of} single-walled domains

in which the domains are not circularly sinü. ^ Layer with preferred direction of magnetization

The magnetic layers, in which operations have been described _{perpendicular to the} layer plane,

this kind are carried out, but have dominant lu iy _Dom änen form in magnetically

rende coercive force. That is, the material is generally ₅ ni '* layers, in which one is preferred

characterized by a preselected coercivity anisive _direction in the plane of the layer

versus domain wall movement. A UO _other yidg b _enac hbarte domains in a sol

activator domain then takes in such layers every form of lie ■ · _{s e} toßkräfte only if they

which is required by the applied fields and rather, ~ ™ f _{ic hard} n axis of these materials

remains in this form when the fields are removed ₁₀ ^Ian ^ "! _ts f _nd neighboring domains running along the

will. Here is the geometry of the various angco '"magnetizations are arranged,

Head of the form-controlling factor. Somewhat stationary axis ^ ™ 8j " _kräf f _e .

Preload can also be present. In egg zeigerι ^ _{$ o] chen to} j _so tropical layers Loner can such a mode are the domains not "con _ operations being served with single-domain". ¹ S f ~ P, _{It is} only necessary that the Do-Die described mixed group of logic- tunrivv. ^ _{Domain surrounds; In itself,} operations require both a prepaid maneuver, a _limitation for the domain to bil-coercivity of, for example, 1.0 oersted and also includes, ummm g ^ ^ _{n ß en the ma}

a stationary bias of 8 oersteds. The co ^de "'. ^ P _n layer in which the domain comparable

erivity and the bias to generate optimal ₂₀ gnettsc ^ne "^ ^Clllcnt '

ler limits are pushed through experiments for each magnetic wii α.

In addition 9 sheets of drawings

Claims (6)

Patent claims: 1. A method for performing logical operations in a layer of magnetic material in which information-representing single-walled domains can be moved in a controlled manner, the layer being assigned a field generating device (12 to 16 PY ₁ to PY _n , PX ₁ to PX _n ) , which in you can generate selected patterns of magnetic fields (e.g. positive fields at the blocks H2P3 / V3P2 and H5P3 / V3P2; Fig. 19) and the information is represented and evaluated by the presence or absence of single-walled domains in discrete positions are defined within the layer for the domains, characterized in that magnetic fields are generated in selected positions in order to urge domains which are so far apart that they exert only negligible repulsive forces on one another, against one another in such a way that the mutual repulsive forces of a domain refuse to move into a selected position, which this in the absence of de r other domain would have occupied. 2. The method according to claim 1 for performing a logical AND operation between a domain in a first position (C1, I in Fig. 14) and a further domain in one second position (Cl, II), which are separated from one another by an intermediate position, thereby characterized in that in the context of the generation of magnetic fields a) Fields of one polarity are generated which form a domain (e.g. in column I, Fig. 14) move to the intermediate position (Fig. 16), b) fields of the other polarity are generated, which extinguish the domain moved in this way (Fig. 16), and c) In turn, fields of one polarity are generated which were previously involved in such a movement move the hindered domain to the intermediate position (Figs. 17 and 18), and that then the content of the intermediate position is detected. 3. The method according to claim I for performing a logical OR operation between a domain in a first position (C2, I in FIG. 19) and a further domain, or that Absence of the same, in a second position (C2, II), which are separated by an intermediate position, characterized in that within the framework of the magnetic field generation a) Fields of one polarity are generated which form a domain (e.g. in column I, Fig. 19) move to the intermediate position (Fig. 21), and b) Fields of the opposite polarity are generated which any, previously involved in such a movement delete domains hindered from the first and second position (Fig, 21), and that the content of the intermediate position is then determined. 4. Arrangement for performing the method according to claims 1 to 3, characterized by a a part (Fig. 42) of the magnetic Layer comprehensive control device (14,15,16, Fig. 1) for generating the magnetic fields. 5. Arrangement according to claim 4, characterized in that it is used to build an associative memory is applied, the magnetic layer (11) being divided into memory, logic and control parts (51, 52, 53 in Fig. 43), in each of which single-walled domains can be stored and moved. 6. Arrangement according to claim 5, characterized in that the memory and logic parts (51 or 52; Fig. 43) each occupy areas that are distributed over the entire magnetic layer (11) are.