DE1774390C3 - Data acquisition system - Google Patents

Description

3 '4

system existing components considerably, from which the data acquisition system serves, as explained, There is a substantial increase in the cost of the sy- to receive data from a variety of stems results. Sources for assembling the data into characters The object of the invention is to provide a system with a predetermined number of bits and a data acquisition system thereon with a queuing 5 subsequent feeding of the composite characters Beware of creating compound characters in an output register in the order in which they are added includes fewer additional components and composition. The system has a memory with so that lower additional costs are fooled. a variety of sections, their number This task is carried out through a data acquisition which corresponds to the number of data sources and which respectively system of the type specified in claim 1 ro a first part in which the corresponding solved by one, the source received bits are stored during the additional advantageous refinements and further assembly, and a two-way formation of the invention emerge from the lower part, in which the composite claim. Characters (in a queue).

The inventive design of 15 when the output register is full.

Data acquisition system it is made possible that the execution shown in the drawings

Storage during the assembly of the example, the output register is an interface

Characters and the storage during the waiting registers for a data processing device and

echlangenfoildung of composite characters in stores not only the processing za together

lind with respect to the same block section of the 20 set characters, but also an address of the

Storage takes place. This in itself already reduces the memory section in which the character is

Demand for components and increased memory was set. Each memory section has a

utilization of space. Another reduction in construction- first part on. in which the characters during the

elements results from the fact that the alternating assemblies are stored. In the second

The relationship between the storage sections for the 25 part of each storage section can

characters set (in a queue) for setting and queuing operations.

a considerable integration of the hitherto large ones can be guaranteed if a previously assembled one

allows separate control functions. Character is still being processed.

In a data acquisition system, it is essential, with a separate input circuit for each data, that the sequence with which the composite source and a scanning device are processed for successive characters is the same as the subsequent scanning of the input circuits for fixed characters. the one with which the signs are composed. Position whether they have received a bit of their respective data- For this purpose, in addition to storing a source, the scanning device der- Address of the memory section - where this is arranged in Verart that it periodically scans the output 35 working characters during the register , and, if the output register has been assembled empty - in memory, is on, and a queue has been created, causes. Queue registers are provided to store the address of the next character in the queue from the section of memory in which the last character was removed from memory and put together in the character output register. When a new one is fed in. 40 characters is composed, and the output-Such input circuits supply is empty when they are registered, and as long as no queue has been formed, each sample a signal, which is any bit received from each of the composed characters, directly into the respective data source indicates. An output register fed in together with the character assembly circuit responds to the address of the memory section in which this signal and the content of the first location of the respective memory section is stored during the assembly. For a sign. Was, however, if a new character and its composition is not completed by this and there is still a character in the output, it is written back to the first register, or a queue was formed, so storage space. For a character which at this time is the newly composed character in one of the “point completely composed”, a second part of the memory (in the manner of a waiting character routing circuit, the forwarding of the queue) is queued. The second part, in which the composed character is either stored at the correct newly composed character, is the storage location of the second memory section locations determined by the address if queue register or to the output register, depending on the. order is made in this way. of whether queuing is required 55 that a reassembled character is always in or not. The indication of the presence of a second part of the memory section is stored. Queuing is provided by Queue Indicators in which the immediately preceding new drawing facility was supplied and an indication of the memory stored during compositing. cher section in which the next character in a? When a composite character has to be introduced from the queue, a queue register is provided by 60 queues in the output register. In the following, an hf of the drawing is shown. In the part the drawing shows the next character in the series stored is. By such an arrangement, the to-Fig. 1 is a flow chart to explain the 6 ₅ composed characters fed into the output register by the data acquisition system, the order in which they are composed.

Fig. 2 is a schematic block diagram of the set.

Data acquisition system. With reference to F i g. 1 becomes in the following

5 6

the mode of operation of the data acquisition system in accordance with the implementation of the procedures referred to in FIG. 1

of the invention described. operations described, is now under

F i g. 1 is a flow chart showing an assumption on FIG. 2 described,

number of blocks in which logical opera- The bits are taken from data sources 22 to 25

actions are carried out. The operations of the 5 conducts, the outputs of which are preceded by individual bistable

System are connected by a device counter 10 directions 26. The device has

controlled one operation of the system in every two flip-flops; that takes one of the flip-flops

Time initiates in which the counter 10 to the one predetermined state when a

is brought up to date. If the device information bit is from its corresponding source

processing counter 10 is brought up to date, io is received while the operating state of the

a signal is fed into a block 11, where other flip-flops depend on whether the information

an operation is performed to check whether the tion bit is a "0" or an "I". The operating

the output register a composite character stands the flip-flops in each device

is present, and it is successively checked via a conductor 12 by signals from

The signal is sent to a block 13, where a device counter 27 is used for operation. These signals

the status of a selected device is checked are fed in via lines 28; every device

However, if the output register is empty, so is treatment 26 is designed such that when it is

a signal fed to a block 14, where a test signal from the counter 27 is applied, the device

operation is performed to determine whether a device produces two output signals when it has a bit

composite character in queue ao received from its corresponding source. A

is available; if so, the first of the output signals (indicating that a bit

System actuated at block 15 to the next character received) is entered into logic circuit 29

fed into the queue from the memory to the output, the other output signal (which

to transfer register. If this operation shows whether the bit is a "0" or a "1"), in

is performed, or if there is no queue there is a logic circuit 30 for drawing

is, a signal is fed to the block 13. setting fed. The way the logical

The selected device, the operation of which circuit 29 is checked by the corresponding off in the block 13, is one of an input signals of the devices 26 and of a number of devices for receiving bits from the signal controlled by the device counter 27 selected data sources. Each device has 30 comes. This logic circuit 29 controls in turn two operating states. one of which indicates the operation of a read selector 31 so that a that one bit was received while the other was partially composed of a character State the presence of such a bit is read out at a predetermined location in a memory 32 shows. The devices are made in turn when through one of the bistable devices checks how the device counter 10 generates an output on the 35 26. The memory 32 learn booth is brought. Should the selected one be divided into a number of sections, whose Device indicate that no bit has yet been recorded - number is equal to the number of sources 22-25. Of the A signal shown in the memory device 10 can store sixteen words fed in, which is then updated and is in four sections «(00), (01). (10) and (11) is subdivided to 40 the next operation of the system, each of which comprises four words; the words kick off. However, if a bit has been received, the in FIG. 2 indicated places. The places will - if available - partially together- (00) and (10) and most of the places (01) Set characters received from the same source of each section are removed from memory in a block 16 for control purposes and the det. The remaining spaces in the sections new bit is converted into a character in a block 17 d. H. the places (0011), (0111), (1011) and (1111) and composed, where it is again checked whether the second half of the spaces (0001), (0101), (1001) Character is complete. If the character is incomplete and (1101) are used to store bits, the system operates in a block M. det, which is derived from its respective sources 22-25 ara bring the character back into memory and be received, where dk places (0001), (010 \). the counter 10 is brought up to date. 5 ° (HH) I) and (1101) for speculation partly together - however, if the sign is complete, set signs are used. The places the system carried out its operation by inspecting the forces in (UOH). (Olli). (1011) and (KIl) are each in a block 15, whether the output register is empty: three pages 33. 34 and 35 below-nlt, of which the if this is the case and no queue is part 33 not used wild, while part 35 is too then the new character at 20 in 55 compound character arrangement (i> the output register transferred. Alternatively, if you think of a snake, and the part 34 to Output register is full or there is a queue specifying the address of the memory section has formed, then the character in the memory is turned into, in which this character is during the To arranged in a queue. This is stored in a compose. Block 21 executed, with the character in the second 60. The memory 32 has an output register 31 Part of the memory section is stored in which its output is connected to a logic circuit 37 the immediately preceding character while is bound. by dk number of bits in the character the composition was saved. After counting, dk is removed from memory Implementation of a through the block 20 or the output of the register 36 is also with the log The operation shown in block 21 will see a signal from the signal composition circuit 30 given to keep the counter 10 up to date by bits π received from sources 21 to 25 bring «. previously collected and stored in memory 32

F. to put together a form of training of the basic system. The exit of the R

7 ^ 8

gisters36 is also indicated with an AND circuit 38, in which the last one to the output register 40 Frets, which form part of a Zekhen routing circuit 39 characters supplied during assembly, completely composed characters, the system is designed in such a way that neither to an output register 40 for a data that the next compound character in the Processing device 41 or to a suitable 5 queue in part 35 of the same memory Parts 35 of the memory 32 via a line 42 to section is stored. That from memory 32 conduct. The circuit is also used to return the extracted characters along with the partially compounded characters in the memory address of the memory section in which it is during via the line 42. In addition to the AND switch the composition was stored (derived from device 38, the circuit 39 has an AND circuit and the corresponding part 34) to the AND circuit gen 44 to 47, OR circuits 48 and 49 and 38 are applied, which also receive a signal from the pre-inverter43, SB and 51 on. The master circuit 39 - direction counter 27 only receives when one is in the the mode of operation of which is described below - character located in the queue is removed from memory controlled by a fin signal that is removed from one. The other input signal for the stable formwork52 comes, whose operating state »5 processing38 is generated by the AND circuit45, is sensed by the device counter 27. The one when the output register is empty and one The operating state of the bistable circuit is reversed. Queue is formed to receive signals from the bistable reverses when the output register 40 is empty. Circuit 52 and queue indicator 54 Character routing circuit 39 is also received by signals to open circuit 45, which then controls an output signal from a queue register 53, 20 for opening the circuit 38 Queue indicator 54 and the counter 37 testifies. The signals that the sign and its come. The queue register 53 stores addresses that represent the OR-the Address of the memory section in which the last circuit 49 completed in the output jester 40 Character was put together and fed.

generates an output for the queue 35. While this character is being processed, an indicator 54 is displayed. This indicator is a bistable pre-signal to a selected device in the bistable direction, which also feeds a signal from the interface register devices 26 to operate -40 receive !, which to check the address of the memory status. If the selected device indicates a section in which the last character input to the output 26 has not received a bit since it was last checked, register input characters were composed. If the two testify to the queue indicator 54 and the operation of the system continues in perceived output signals, the device counter 27 does not generate an output signal is empty.
If, however, the selected device 26 has an output signal which the AND circuit 44 and the 35 bit has received, it generates an output signal when tested by the OR circuit 48. The memory 32 provides the device counter 27 with two output signals; the has a Schrcibselection circuit 55, whose working an output signal is the logic circuit 29 controlled by a logic circuit 56 is supplied; the other signal indicates whether the empdie in turn> is controlled by signals which are a "1" or a "0" from the caught bit and will come to the device counter 27, the queue register 40, character composition logic circuit 30, 53 and the circuit 39 . fed. Furthermore, the device counter 27

The removal of 7 ·. · ^ Amrru-ngcsetz characters, which are fed into the logic circuit 29 a signal; the memory 32 are arranged (in queues), the coincidence of this signal with a signal from is controlled by signals which cause the logic circuit of the selected device 26 that the 29 are routed from the device selector 27 and 45 logic circuit 29 the read selection circuit 31 further by signals which operate the logic circuit in order to be fed from the memory 32 any partially via conductors 57 and 58, which are to be cntregister 40 \ are bound. distant. There will be a signal indicating this sign

The mode of operation of the system is then applied to the logic circuit 37 by the Vor so

Direction counter 27 is controlled before checking the number of bits in the partial

State of each bistable device 26 checks whether set character counts; this signal will also be «

the task register 40 is empty. The latter test is still sent to the logical character collection circuit 30 uncj

depends on the state of the bistable circuit 52. applied to the AND circuit 38. The function dei

which then, ν enn the output register 40 is empty, the 55 routing circuit 39 then depends on the number of bits in the

Device counter ²⁷ supplies a signal. If not partially assembled, from memory 32

such a signal is present. the characters removed from the device go off.

counter, the state of one of the bistable If the received bit is not sufficient to:

Device to be checked. ^ N 26. However, if to complete the compound sign, st

input register 40 is empty, the device counter 60 reads the bit in the character which

27 a signal to the logic circuit 29, which is then fed to the AND circuit 46. There

when it receives a signal on the line 57, the partially composite (collective character

shows that a queue has been formed, the read is also fed into the AND circuit 38, the

wählschaltnnp 31 is actuated to get out of the memory 32 but does not result in any operation because of the failure

the next compound character in the 65 presence of a signal from the device!

Read queue 71. The place where this character counts 2 * /. The other input signal for the scarf

is stored. is generated by a signal on trigger 58 device 38 comes from an OR circuit 48. Di.

determines which the address of the memory section logic circuit37 only generates an output

9 10

signal, if the character just put together will indicate the address of this memory section. In this case, therefore, the circuit 37 would cause the reassembled to produce no output signal, so that the inverter SO characters written in part 35 of this section produces an output signal to become the circuit 48. The address of the memory section in which the open, thereby permitting the partially reassembled character to be stored in the same place in the setting during the reassembly, is also written back into memory 32. This is enclosed by the corresponding part 34 of the memory 32, the logic circuit 56 for the write selection keys. This is achieved in that one controls this tuüg 55, which is actuated in a corresponding manner by address indicating signal from the device counter three signals applied to the logic circuit 56 in the logic character assembly circuit. Two of these signals are fed in from signals 30. The device counter 27 is also derived, which is applied to the AND circuit 46 if a signal is sent to the queue register 53; the third signal is carried by the device to feed the address in the register to the counter 27 and to bring the location in the memory up to date, namely the address of -32 in which the partially composed character 15 of that memory section, in which the new zuzTiriick must be written. In some cases, compound characters reside during the compound when a bit is received in which the set was stored. This is not partially initiated by the logic circuit 37 by a signal corresponding to the space in the memory 32.
compound sign. Alternatively, the system will operate if the output register 40 is then similarly empty to the bit in the memory and no queue is formed to be written. new compound characters in register 40

Should that be fed from the selected device 26. This is done by feeding the signal

received bit to complete a to- from the bistable circuit 52 to the AND switch

If the composite character is sufficient, device 44 is reached. The other input signals for the

Characters are fed into the output register 40 when 23 AND circuit 44 are activated by the logic switch

this is empty and no queuing device 37 and sourced from inverter 43, which is a

became; if the output register 40 is full and / or output signal only during the absence

a serpent is formed, then it is created in one of his a serpent. The output signal of the

of the parts 35 of the memory in a queue AND circuit 44 allows the opening of the AND

lined up. 30 circuit 47, and the newly composed character

In this case, the logic circuit 37 generates via the OR circuit 49 into the output register an output signal to be fed to the AND circuit 44 40. Then, as before, the address is fed. If the output register 40 is empty, the memory location where the character was entered during the thus AND gate 44 receives its second ranking from the device counter output from bistable circuit 52; if 35 27 derived and about the logical signs together Output register 40 is full, the non-setting circuit 30 causes the output register 40 to be present an output signal from the bi-leads. In addition, the queue register 53 stable circuit 52 that the inverter 51 is fed a signal from the device counter 27 a signal to generated for the OR circuit, which is also used to receive the address in the register up to date catch a signal from the queue indicator 54 to bring 40 to the address of the one switched off is when a snake is formed cut of the memory 32 in which the newly merged, characters set during assembly

Should the OR circuit 48 store an output signal.

It should be noted that in each part 35 the circuit 46 is opened and the composite 45 of the memory 32 at any one time only one character is sequentially assigned via the line 42 into the memory 32 (fed in one. The inscription of the character in the queue) can be arranged.
For this purpose, each memory section is equipped with output signals from the AND circuit 46 to the logical part 59, in which a bit is controlled. Since the character is completely 50 when a compound is compounded in this section, it must be queued in the memory 32 in characters; the bit is taken from the corresponding parts 35 (in a queue) only when the characters are assigned to the. This is passed through a signal to an output register 40. Another should be routed, which is applied to logic circuit 56 composed of the characters in a section logic circuit 37. The part 35. in 55 den, if the previously in this section also the compound character (in a compound character still in the queue) is placed by a signal bc- is located in the part 59 this Coordinates which bit stored by the queue register 53 section used to get the instruction of the newly composed character fed back and fed into the logic circuit 56 Pass queue register 53 and that of 60, and to give the corresponding sources 22, 23, 24 the signal coming there to instruct the section of the memory or 25 that the character returned 32 in which the immediately preceding was indicated, so that the information bits were assembled into one character; causes the signal. later date back again by the source that the newly composed characters can be carried into the part.

£ this memory section is written. 65 For digital computers where data is in bit form from a

For example, if the immediately preceding number of sources were being fed

Characters at the place (1101) was composed, systems suggested that the bits in single characters

«O would collect the signal from queue register 53 for each source and the collected

to feed (composite) characters into a queue register in the order of their composition, where the characters are stored before they are in turn, e.g. processing devices, can be entered. When using queue registers the amount is that required "Hardware" is considerable, which means that the data acquisition systems are relatively are expensive.

The bits are assembled into characters and stored in a memory during assembly a plurality of sections, the number of which is equal to the number of sources from which

these bits are received, and means are further provided to convert the bits into their corresponding To feed sections into the stores. It was found that in many stores one Part of each section is not used; it was therefore envisaged to remove the unused parts of each Use this section to arrange compound characters in queues. By a such an arrangement, the provision of a separate queue register can be avoided, whereby the necessary "hardware" is reduced; this reduces the cost of such systems.

For this purpose 2 sheets of drawings

Claims (4)

ι 2 the or in the memory (32) form a queue of patent claims> if the bits represent a complete character. 1. Data acquisition system for receiving 5 Bit data from a variety of sources, to compose the data into characters with
specified bit numbers and for feeding in the composite characters into an output A well-known data acquisition system for receiving register in the order of composition io catch data in bit form from a variety of of the characters, the data acquisition system sources, for assembling the data into characters a memory with a number of sections with fixed bit numbers and for feeding in the includes the number of characters combined with the number of data sources in an output register corresponds, with each section having a place in the order of the composition of the characters in which the bits from the respective data 15 has a memory with a large number of qi'elle during the composition of the cut on, the number of which equals the number of Characters are stored, thereby ge data sources and in those of corresponding indicates that each section of the storage sources received bits during their chers (32) also has a second place (35) to store characters. With this one closes, the with queue control device- ao data acquisition system, the data sources of the gen is connected, which respond to a signal, scanned in sequence and upon receipt of a bit this indicates that the output register (40) is filled from a data source that was previously filled by this data source is to form a queue by the fact that the data source received and partially after the output register has been completely filled, characters set from the corresponding memory (40) Fully composed characters taken in 25 sections. The new bit is then with the second place of the memory section is directed to the partially composed character. in which this is set immediately beforehand and is, if it is still incomplete dig compound characters during the condition is returned to the memory section, was saved. If the incomplete sign by the new 2. Data acquisition system according to claim I, is completed when 30 added characters are which each data source has an input circuit of either complete compound characters is assigned and the one scanning device is supplied to an output register, where the together to successive scanning of the inserted characters was processed, for example, output circuits to determine the fact, or it is indicated in a queue for so long the input circuits one bit from each 35 assigns until the output register to receive the respective data source have received. composite sign is ready. characterized in that the scanning device- Due to the high operating speed of the device (27) is designed such that it can periodically data acquisition systems the speed, the output register (40) is scanned and then, when the characters are put together, some- the output register (40) is empty and turns out to be 40 times greater than the speed at which The queue has formed the removal of the compound characters to be processed next character in the queue from the can. Memory (32) and its feed into the output It is essential that the sequence with output register (40) causes. which the compound characters in the output 3. Data acquisition system according to claim 2, that 45 registers are fed in, is the same as that characterized in that one with the memory order in which the compound characters (32) connected character composition shells are queued. So it is device (30) and a control circuit (39) for further necessary that the data acquisition system irgcndlcitung Incomplete characters from memory- a device that has the compound burst in the memory (32) to put together 50 characters in a queue in such a way that Put them into the output circuits in the correct order with the corresponding input circuits received bits and fed into the forwarding register. conduction of compositions of these characters- In the known data acquisition system was Bits to the output register (40), if this is achieved through a queue register. Obs composite Bits of a complete character 55 are likely to satisfy such queue registers and the output register (40) is empty, or working positively, they require the use of a to the memory (32) when the composite further memory in the data acquisition system. Further Bits do not form a complete character or the queue registers also assign this to other allocated output registers (40) is full, are provided. obeyed circuits in order to ensure that the 4. Dalen detection system according to claim 3, characterized 60 composite characters by the queuing are moved forward by a counter (37) for counting registers when combined Number of bits in any partially added character from the queue register decomposed, are transferred from the memory (32) to the fcrnt and to the output register, Character assembly circuit (30) so that the compound characters in the correct Characters and to control the operating sequence. the control circuit in such a way that the bits in the queue register and the associated of the character composition circuit (30) only increase the circuit-forming components then the output register (40) is supplied with the total scope of the data acquisition