DE1762399A1 - Biorthogonal code generator - Google Patents

Description

Communications Satellite Corporation, Washington D.C, / USA

Biorthogonal code generator

The invention relates to phase-coherent communication links that use orthogonal or bi-orthogonal code words to reproduce separate messages with high quality, M where transmission disturbances, such as white Gaussian noise, are likely because such code words are ideally suited for exact demodulation using cross-correlation techniques are. In a group of orthogonal code words, every word differs from every other word in that it has the same number of bits as it is every other word. For example , two orthogonal code words in an 8 word group may be 01101001 and 00111010, and it should be noted that bits 2, 4, 7 and 8 are different while bits 1, 3, 5 and 8 are the same. Under this condition, the cross-correlation coefficient between any two words in a group is zero, and in this way the cross-correlation detection or decoding of transmitted messages by such words achieves a high degree of accuracy even in the presence of considerable channel interference.

This type of coding is even more interesting when the capacity of a given group of orthogonal codewords can be doubled by expanding to a biorthogonal group, which only requires the addition of the complement of each orthogonal codeword in a group. The complementary group of code words is orthogonal to each other and with respect to each code word of the true group with the exception of the word from which the complementary word was derived. The last exception raises no deodorizing problem

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on. However, because complementary words differ from each other to the maximum possible extent, i.e. one is the complete one Is the opposite of the other, the likelihood of confusion is minimal. If you take as an example the same two orthogonal code words as used before are the complements 10010110 and 11000101. These complementary ones Words differ from each other in four bit positions and are the same in four bit positions, and the same applies to the first and second complement words with respect to the second and first true words.

The usual way of practicing such a communication technique is to store or generate each of the orthogonal codewords of a group in the transmitting station. Each codeword represents a separate message, and when a specific message is intended to be sent, its corresponding codeword is sent out. In the receiver, the received code word is compared simultaneously with each code word of the entire group in a group of parallel correlators, and a decision device determines which code word or message was transmitted in accordance with the correlator output signals by selecting the correlator with the largest output signal. Because all code words * are orthogonal, the output signals of all other correlators are zero under ideal conditions.

It is therefore reasonable that such a system requires the storage or generation of each codeword of a group in both the receiver and the transmitter. In the conventional systems this has been accomplished either by storing the exact mirror image of each codeword or by providing separate encoders or generators for each word. If a group of 8 words with 8 bits each is used, the technology of permanent storage requires the storage of 64 bits and the two-fold encoder consists of a four-

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step register, modulo 2, two adders and a flip-flop for each group of god words. Such extensive hardware requirements are unsustainable not only from a cost and reliability standpoint, but where weight considerations are concerned What matters, as in guided missiles and communications satellite systems, is this need for hardware totally unacceptable.

The excessive hardware demands of the earlier mentioned above Systems are effectively avoided by the present invention that are novel orthogonal or biorthcgonal Code generator in the form of a shift register circuit connected to form a ring creates. The circuit generates all the code words of a given group simultaneously and requires a total number at levels or storage locations which is equal to the number of bits in each code word less by one. For the The above group of 8 words with 8 bits each would require a total of 7 memory locations. This saving is achieved by taking advantage of the fact that every orthogonal code word of a whole group is just a different phase is the same bit sequence, with the exception of the first bit in each word, which is always the same, and the last word, which is is a repetition of the same bit, as will be better seen later.

In a special embodiment that is used for generating a group of 8 words with 8 bits each, the initial 7-bit sequence turns into a during the first cycle time seven-step register entered in parallel. At the same time, all register output gates are blocked, which is reflected in this, that the same first bit is generated for each word. Then the gates are opened and the register is opened during each Clock time advanced in the usual way, with the output signal from the last stage in each case as an input signal for the first stage in the manner of a üml.?. rfc? s cri ^ H.i -.- ies zu-

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is fed back. After 8 clock times the whole group of orthogonal words has been generated, with each output gate supplies another code word in serial form.

In the drawings shows

Figure 1 is a block diagram of a ring-connected shift register circuit according to the invention,

Figure 2 is a timing diagram of signals appearing at certain terminals in the circuit of Figure 1, and

FIG. 3 shows the complete group of the circuit of FIG 1 generated biorthogonal code words.

Figure 3 shows a typical group of biorthogonal code words, the eight true words or pieces of information, labeled 1 to 8, and eight complementary words, labeled 9 to 16 or includes information. A consideration of Figure 3 shows the following properties of the group:

a,) Information no.9 is the complement of information no. 1, information No. 10 the complement of information No. 2, etc;

b.) The first bit position of information no. 1 to 8 is in each case zero and the first bit position of information no. 9 to 16 is always one;

c.) Information no. 8 consists only of zeros and information no. 16 consists of only ones;

d.) With the exception of the first bit in each word and the last word in each group, each piece of information has the same binary sequence like the one above her, but shifted one bit to the right; and finally

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e.) Each piece of information or each word has four bit positions in common with every other word and differs from this in four bit positions with the exception of its complement.

It should thus be apparent that if any information is combined with any other information besides its complement is related by multiplying the two pieces of information bit by bit and adding up the results the bottom line is zero if interference is excluded. This is because owing to the above Property (e.) The integration capacitor is charged positively to the same value as negatively, with the result that the remaining or final charge is zero.

In the code generator circuit of FIG. 1, the shift register 20 consists of seven stages S 1, S 2, etc., the output of stage S 7 being connected to the input of stage S 1 via lines 22. The register is advanced by a clock pulse sequence which is applied to a monostable multivibrator 24 at terminal B and fed to the register stages via line 26. The initial register input signals shown in the lower part of the figure are input to the stages in parallel via AND gate 28 in accordance with a preparation signal applied to the terminal C of the one-shot circuit JO , and the same signal is also input to the reset input of the flip-flop. Flops 32 supplied. The latter is set by a signal that is fed to terminal A and via the monostable multivibrator J> k . The states of the individual register stages are fed to separate output terminals via AND gates J> 6, which are prepared by the output signal from flip-flop 32. The output terminals are numbered 1 to 6 and correspond to the information or code words generated on them, and the complementary information occurs on terminals 9 to 16 by the corresponding true information about the

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Inverter 38 are conducted. Because information no. 8 is zero in all places, output terminal 8 is simply included Connected to ground, and by inverting the ground signal, the output terminal 16 is always raised and thus supplies in all digits ones, which corresponds to information no. 16.

In operation, the seven-bit initial sequence 1110010 is applied to AND gates 28, and when the latter are prepared by signal C of Figure 2 at the beginning of the first clock time, the sequence is entered directly into the seven register stages. In reality, the signals shown in FIG. 2 appear at the output terminals of the three monostable multivibrators 24, 30 and 34. The latter assemblies are provided in order to shape the pulses applied to terminals A, B and C in an appropriate manner. Signal C also resets flip-flop 32, the lowered output signal of which prevents output AND gates 36 from causing all zeros to appear at output terminals 1 to 8 and all ones to output terminals 9 to 16. It can be seen from Figure 3 that this is in accordance with the code word group. Near the end of the first clock time, a clock pulse from the monostable multivibrator 24, which is shown by curve B in FIG. 2, switches the register one step further, which results in the sequence 0111001. At the beginning of the second clock period, a pulse triggers the monostable multivibrator 34, whose output signal, which is shown by curve A in FIG. 2, sets the slip-flop 32, which prepares the output gates 36. The output terminal 1 is now · the one in the step S 1, the terminal 2, the one in the step S 2, etc. Near the end of the second cycle time pushes a pulse of the curve B, the register 20 again by one position to the To generate sequence 1011100, and because the Und-Oatter 36 are still prepared duroh the high potential output of the flip-flop 32, this new bit sequence is output at the output terminals. The register is incremented again at the end of each cycle time and after a full cycle of

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Each of the code words shown in FIG. 3 is 8 cycle times or information has been generated at the corresponding output terminal.

It can therefore be seen that the shift register circuit of the present invention, which uses only seven stages and associated logic circuits, is able to simultaneously generate all 16 code words in a biorthogonal group within eight clock or bit times. The hardware savings, which are achieved by this arrangement over the prior art, make this invention advantageous especially useful where cost and weight considerations are important. Although the invention is used in conjunction with a phase-coherent transceivers are explained, it is not restricted to such an application, but is equally applicable to the transmitter of such a system or in any other context where orthogonal code word groups have to be generated.

The index levels and circuit groups shown as blocks in FIG. 1 may take any suitable form known per se, but which is outside the scope of this invention. Ä

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Claims (4)

Claims 1.) Electronic circuit arrangement for the simultaneous generation of orthogonal code words in a group of η words with η bits each, characterized by a) a shift register (20) with n-1 stages, b) switching means (22) which control the output of the last stage ( Connect S 7) of the register to the input of the first stage (S l), c) a device (28, JO) for entering the last n-1 bits of an orthogonal code word into the register, d) output terminals (// 1 - & l), which are each coupled to a stage of the register, and e) a device (24, 26) for} port switching the register, whereby a different orthogonal code word is generated in series at each output terminal when the register is over a full n- Step cycle is incremented. 2.) Electronic circuit arrangement according to claim 1, characterized in that a) each output terminal arrangement comprises an AND gate (36), one input of which is connected to its associated register stage, and further characterized by b) a device (JO, 32), which is connected to the respective other input of each AND gate to disable the gate during the first step in the cycle, and 0) an additional output terminal (8) which is connected to a source Ψ of constant potential. 3.) Electronic circuit arrangement according to claim 1, characterized by in each case an inverter (38) which is connected to each output terminal arrangement to the complement of the on her generated orthogonal code words and thereby the group of η orthogonal code words to a group of 2 η to expand biorthogonal codewords. 4.) Electronic circuit arrangement naoh claim 2, characterized by an inverter (38) connected to the output 009823/1523 of each AND gate and the additional output terminal 1st to generate the complement of the code word generated on it and thereby the group of η orthogonal code words to a group of 2 η biorthogonal codewords. 009823/1523 Blank page