DE172193T1

DE172193T1 - PROGRAMMABLE READ-ONLY READING MEMORY CELL AND METHOD FOR PRODUCING THE SAME.

Info

Publication number: DE172193T1
Application number: DE1985900935
Authority: DE
Inventors: Lloyd Daniel Fort Collins Co 80524 Ellsworth; Andrew Paul Fort Collins Co 80525 Sullivan
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp
Priority date: 1984-02-09
Filing date: 1985-02-04
Publication date: 1986-07-24

Claims

EP 85900935.9

PCT / US85 / 00173

3492 / EPC

Claims

1. Electrically programmable 1 read memory cell only,
marked by

a semiconductor substrate (22, 23) of a first conductivity type, a base region (28) and a base contact region of a second conductivity type, which are formed in the substrate (22, 23), an emitter region (32) of the first conductivity type in the base region (28), a dielectric layer (29) over the base region (28) and the base contact region (21) having openings formed therethrough, a. Anti-fuse structure with an area of undoped poly (37) in contact with the emitter area (32) and a conductive layer (34) of the first conductivity type, whereby the anti-security structure has a defined periphery that extends over part of the dielectric layer (29) extends, and conductive connections (50,51) for the conductive layer (34) and the base contact area (21) are provided.

2. Memory cell according to claim 1,
marked by

a protective oxide area (39) surrounding and in contact with the periphery of the anti-fuse structure (34,37) is.

3. Memory cell according to claim 2,
characterized,

that an oxide layer (42) is arranged as an intermediate layer barrier on the conductive layer (34).

4. Memory cell according to claim 2,
characterized,

that a tungsten layer (59) on the conductive Layer (34) is arranged.

5. Memory cell according to claim 1,
characterized,

that the anti-fuse structure has a thickness of 0.5 μm owned.

6. A method for producing an electrically programmable read-only memory cell,
marked by

the steps:

Arranging a semiconductor chip (20); Form an exposed emitter region (32) of a first Conductivity type and an associated, neighboring one Base contact region (21) of a second conductivity type for a bipolar transistor in a base region (28) of the semiconductor plate (20); Providing an area of undoed polysilicon (37) on the emitter area (32); Form a conductive layer (34) of a first. Conductivity type on the area of undoped poly-silicon (37); and providing an ohmic connection (50) to the conductive layer (34), whereby a programmable anti-fuse structure (3.7,34) is formed, which is connected to the emitter region (32) of the bipolar transistor.

Method according to claim 6,

characterized,
that the semiconductor plate (20) has an epitaxial layer of the first conductivity type with a collector region (22) for the bipolar transistor and by the steps of: forming a base region (28) of the second conductivity type in the epitaxial layer and forming the emitter region (32) in the Base region (28), whereby part of the base region forms a base for the bipolar transistor.

Method according to claim 7,

characterized in that the emitter region (32) is in the base region (28) and the plate (20) containing the base contact area (21) by forming an oxide layer (29) over the lamina (20) masking oxide layer (29) with the exception of an area over an emitter region (31), etching the oxide layer (29) to expose an emitter area in the base region (28), doping the emitter surface with impurities from the first Conductivity type and heat treatment of the wafer (20) to form the emitter region (32) is formed.

Method according to claim 8,

characterized,
that the anti fuse structure (37,34) by depositing a layer of undoped polysilicon (33) over the emitter region (32) and the oxide layer (29), doping the exposed surface of the polysilicon layer (33) to form the conductive layer (34) in the polysilicon layer (33), masking the polysilicon layer (33) in one area

(36) that is above and adjacent to the emitter region (32) lies, and etching away the unmasked areas of the polysi1ilicon layer (33) is formed, whereby the anti-fuse structure (37,34) is left over the emitter region (32) and a periphery possesses, which lies over the oxide layer (29).

10. The method according to claim 9,
marked by
de η S chri 11:

Forming a layer of silicon dioxide (38) over the the anti-fuse structure (37,34) having platelets (20) and etching away the layer of silicon dioxide (38) to have a protective deposit of silicon dioxide (39) adjacent to the periphery to leave the anti-fuse structure (37,34).

11. The method according to claim 10,
marked by
the step:

Providing a contact area (43) for the base contact area (21) in the layer of silicon dioxide (38) and the provision of metal 1 contacts (50,51) over the anti-fuse structure (37,34) and the Base contact area (21) lie.