DE1614569A1 - Method for producing a protective layer consisting of silicon nitride on the surface of a semiconductor body - Google Patents

Method for producing a protective layer consisting of silicon nitride on the surface of a semiconductor body

Info

Publication number
DE1614569A1
DE1614569A1 DE19671614569 DE1614569A DE1614569A1 DE 1614569 A1 DE1614569 A1 DE 1614569A1 DE 19671614569 DE19671614569 DE 19671614569 DE 1614569 A DE1614569 A DE 1614569A DE 1614569 A1 DE1614569 A1 DE 1614569A1
Authority
DE
Germany
Prior art keywords
layer
silicon nitride
photoresist
semiconductor
reaction gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19671614569
Other languages
German (de)
Inventor
Dipl-Chem Dr Erich Pammer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of DE1614569A1 publication Critical patent/DE1614569A1/en
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)

Description

SIEMENS AKTIEFGESELLSCHAFT Berlin und MünchenSIEMENS AKTIEFGESELLSCHAFT Berlin and Munich

16H56916H569

München 2, i5bSEfi19£S Witteisbacherplatz. 2Munich 2, i5bS Efi19 £ S Witteisbacherplatz. 2

PA 67/2662PA 67/2662

Verfahren zum Herstellen einer aus Siliciumnitrid bestehenden Schutzschicht an der Oberfläche eines HaIb-Process for making a silicon nitride one Protective layer on the surface of a

leiterkörpersladder body

--..-ItV--..- ItV

Zusatz zu: Patent .-·····.<·...·«(Pat.Anm. S 108.862 VIIIc/21gj -™- PA 67/220O)0 Addition to: Patent .- ·····. <· ... · «(Pat.Anm. S 108.862 VIIIc / 21gj - ™ - PA 67 / 220O) 0

In der Hauptpatentanmeldung S 108,862 VIIIc/21g (PA 67/2200) ist ein Verfahren zum Herstellen einer teils aus Siliciumoxid, teils aus Siliciumnitrid bestehenden Schutzschicht anIn the main patent application S 108.862 VIIIc / 21g (PA 67/2200) is a process for producing a partly made of silicon oxide, partly made of silicon nitride protective layer

Ί6Η569Ί6Η569

PA 9/493/877 - 2 -- "PA 9/493/877 - 2 - "

der Oberfläche eines Halbleiterkörpers beschrieben, bei dem eine aus Siliciumoxid und eine aus Siliciumnitrid bestehende Schicht an der Oberfläche eines Halbleiterkristalls unmittelbar übereinander durch Abscheiden der Schutzschichtmaterialien aus der Gasphase angeordnet werden, welches dadurch gekennzeichnet ist, daß während des gesamten Abscheideprozesses ein zur Abscheidung von Siliciumnitrid befähigtes Reaktionsgas verwendet und diesem Reaktionsgas während eines Teils des Abscheidungsprozesses ein zur Abgabe von Sauerstoff befähigtes Reaktionsgas in einer solchen Konzentration zugemischt wird, daß neben minde-, stens einer zusammenhängenden Schicht aus Siliciumnitrid mindestens eine zusammenhängende Schicht aus Siliciumdioxid an der gleichen Stelle dev Halbleiteroberfläche abgeschieden wird.The surface of a semiconductor body is described in which a layer consisting of silicon oxide and a layer consisting of silicon nitride on the surface of a semiconductor crystal are arranged directly one above the other by deposition of the protective layer materials from the gas phase, which is characterized in that during the entire deposition process a layer capable of deposition of silicon nitride reaction gas used, and this reaction gas is mixed with a UNTRAINED for delivering oxygen reaction gas in such a concentration during part of the deposition process that least a continuous layer of silicon nitride a contiguous layer of silicon dioxide at the same point dev semiconductor surface is deposited next minde- least.

Hierzu ist im einzelnen festzustellen, daß Schichten aus Siliciumnitrid und Schichten aus Siliciumoxid die Fähigkeit haben, die Halbleiteroberfläche in elektrischer Hinsicht z. B. gegen störende Einflüsse aus der Atmosphäre wirksam zu schützen. Eine weitere Befähigung besitzen solche Schutzschichten als Diffusionsmasken bei der Herstellung von Halbleiteranordnungen, insbesondere nach der Planartechnik. Zur Durchführung eines derartigen Herstellungsprozesses wird die Halbleiteroberfläche mit einer Schicht aus Siliciumoxid (SiO?) und/oder einer Schicht aus Siliciumnitrid (Si-JT.) abgedeckt und in den SchutzschichtenTo this end, it should be noted in detail that layers of silicon nitride and layers of silicon oxide have the ability to affect the semiconductor surface in electrical terms, for. B. to protect effectively against disruptive influences from the atmosphere. Such protective layers have a further capability as diffusion masks in the production of semiconductor arrangements, in particular according to planar technology. To carry out such a manufacturing process, the semiconductor surface is covered with a layer of silicon oxide (SiO ? ) And / or a layer of silicon nitride (Si-JT.) And in the protective layers

00 9 8 44/OA 13 BAD ORIGINAL- J-00 9 8 44 / OA 13 B AD ORIGINAL- J-

.PA 9/495/877 - 3-.PA 9/495/877 - 3-

ein oder mehrere zur Halbleiteroberfläche durchgehende Fenster erzeugt oder freigelassen. Die derart präparierte Halbleiteroberfläche wird der 'Einwirkung eines dptierenden Gases, beispielsweise der.Einwirkung von Bor- oder 3?hosphordampf, ausgesetzt. Während diese Dotierungsstoffe an der freigelegten Oberfläche ohne Schwierigkeiten in das Innere des Halbleiterkörpers eindringen und dort die gewünschte Wirkung entfalten können, ist dies an den mit den besagten Schutzschichten abgedeckten Stellen der Halbleiteroberfläche unmöglich. Schichten aus Siliciumoxid SiOg} oder Siliciumnitrid vSi^lL) entfalten eine ausgesprochen heininende Wirkung auf das Eindringen des Dotierungsstoffes in die von ihnen abgedeckten Teile der Halbleiteroberfläche, selbst wenn die Dicke der Schutzschichten..nur wenige /u betrügt. Festzustellen ist dabei, daß eine Siliciumnitridschieht im allgemeinen eine stärker entwickelte Fähigkeit aufweist, Dotierungsstoffe vom Eindringen in die abgedeckte Halbleiterschicht zurückzuhalten, als dies einer Siliciumoxidschicht möglich ist. Andererseits weisen Siiiciuraoxidschichten bei der fertigen. Halbleiteranordnung eine bessere Schutswirkung auf. Aus diesem Grund ist die kombinierte Anwendung von Schutzschichten aus Siliciumoxid und Siliciumnitird durchaus zweckmäßig, wobei jedoch in aller Regel die äußere Schicht eine Siliciumoxidschicht sein wird. Nach Herstellung der Siliciumnitridschicht stellt sich jedoch jedesmal die Aufgabe, in.diese-Nitridschicht die für die Diffusion erforderlichen Fenster einzuätzen. Nun ist aber das zweckmäßig ober-one or more windows extending through to the semiconductor surface are produced or left free. The semiconductor surface prepared in this way is exposed to the action of a dptating gas, for example the action of boron or phosphorus vapor. While these dopants can penetrate without difficulty into the interior of the semiconductor body on the exposed surface and develop the desired effect there, this is impossible at the locations of the semiconductor surface covered with the said protective layers. Layers of silicon oxide or silicon nitride SiOg} v ^ Si IL) exhibit a pronounced heini effect on the penetration of the dopant in the areas covered by them parts of the semiconductor surface, even if the thickness of a few Schutzschichten..nur / u cheating. It should be noted that a silicon nitride layer generally has a more developed ability to hold back dopants from penetrating into the covered semiconductor layer than is possible for a silicon oxide layer. On the other hand, Siiiciuraoxidschichten have in the finished. Semiconductor arrangement a better protective effect. For this reason, the combined use of protective layers made of silicon oxide and silicon nitride is entirely expedient, although the outer layer will generally be a silicon oxide layer. After the silicon nitride layer has been produced, however, the task is always to etch the windows required for diffusion into this nitride layer. Now, however, this is expediently

0098U/0413 BAD ORIGINAL0098U / 0413 BAD ORIGINAL

- \ . ■ - \ '■■■ " ■■',■■■ - 4 -- \. ■ - \ '■■■ "■■', ■■■ - 4 -

16U56916U569

PA 9/493/07T - 4 -PA 9/493 / 07T - 4 -

halb von 800 0O erzeugte Siliciumnitrid nur dem Angriff derjenigen bekannten Ätzmittel zugänglich, die ihrerseits eine aus Fotolack und dergleichen bestehende Ätzmaske angreifen und zerstören. Man ist deshalb gezwungen, auf der SiliciumnitridGchicht eine weitere, aus Siliciumoxid (SiOg) bestehende Maske aufzubringen, diese Maske mit Hilfe von Fotolacktechnik herzustellen und in diese Schutzschicht bis zu der darunterliegenden IJatridschicht durchgehende Diffusionsfenster einzuätzen und dann in einem weiteren Arbeitsgang die auf diese Weise entstandene SiOp-Maske zum lokalisierten Atzen der darunterliegenden Si,I"T«-Schicht zu verwenden, v/ozu als Ätzmittel erhitzte Ortophosphorsäure dienen kann.Half of 800 0 O generated silicon nitride is only accessible to the attack of those known etchants, which in turn attack and destroy an etching mask consisting of photoresist and the like. One is therefore forced to apply a further mask made of silicon oxide (SiOg) to the silicon nitride layer, to produce this mask with the help of photoresist technology and to etch diffusion windows into this protective layer up to the underlying Ijatride layer and then in a further operation the one created in this way To use SiOp mask for localized etching of the underlying Si, I "T" layer, v / o heated orthophosphoric acid can serve as the etchant.

Die in der deutschen Patentanmeldung 9/493/874 beschriebene Technik macht die Anwendung einer SiOp-Maskierung zum Ätzen von Si^N.-Schichten entbehrlich, indem in dieser Anmeldung eine Methode aufgezeigt wird, bei der die Fenster in der Si^N.-Schicht auch unter Anwendung einer Fotolackmaskierung erzeugt werden können. Es sind jedoch Fälle denkbar, bei denen man dennoch mit einer SiÖp-Maskierung bei der Erzeugung der Diffusioncfenster in einer aus Si^N.- bestehenden Schicht arbeiten möchte. Für diesen Fall bringt die im Folgenden zu beschreibende Erfindung eine vorteilhafte Möglichkeit.The one described in German patent application 9/493/874 Technique makes the use of a SiOp mask for etching of Si ^ N. layers dispensable by in this application a method is shown in which the windows in the Si ^ N layer are also masked using a photoresist can be generated. However, there are cases conceivable when which you can still use SiÖp masking when creating the diffusion window in a layer made of Si ^ N.- want to work. The invention to be described below provides an advantageous option for this case.

Die Erfindung besieht sich auf ein Verfahren zum Herstellen einer Schutzschicht an der Oberfläche eines Halbleiterk'örpers, -bei dem eine aus Siliciumoxid und eine aus Siliciumnitrid be-The invention relates to a method of manufacture a protective layer on the surface of a semiconductor body, one made of silicon oxide and one made of silicon nitride

QQ98U/0413 BADORIGmAL QQ98U / 0413 BADORIGmAL

45694569

PA 9/493/877 - 5 - - ' *" ' ' "PA 9/493/877 - 5 - - '* "' '"

stehende Schicht an der Oberfläche eines Halbleiterkristalls unmittelbar übereinander durch Abscheiden der Sehutzschichtma'terialien aus der Gasphase gewonnen■, werden-, bei dem während des gesamten Abscheideprozesses ein zur Abscheidung von SiIi-" ciumnitrid befähigtes Reaktionsgas verwendet und diesem Reaktionsgas während eines Teils des Abscheideprozesses ein zur Abgabe von Sauerstoff befähigtes Reaktionsgas in einer solchen Konzentration zugemischt wird, daß neben mindestens einer zusammenhängenden Schicht aus Siliciumnitrid mindestens eine · zusammenhängende Schicht aus Siliciumdioxid an der gleichen Stelle der Halbleiteroberfläche abgeschieden wird, nachstanding layer on the surface of a semiconductor crystal directly on top of each other by depositing the protective layer materials obtained from the gas phase ■, be-, in which during of the entire deposition process a for the deposition of SiIi- " cium nitride enabled reaction gas is used and this reaction gas is used during part of the deposition process Release of oxygen-capable reaction gas is admixed in such a concentration that in addition to at least one coherent layer of silicon nitride at least one contiguous layer of silicon dioxide on the same Place of the semiconductor surface is deposited after

Patent . :l..... (Pat.Anm. S 108.862 VIIIe/2Tg; PA β?/2200) ,Patent. : l ..... (Pat.Anm. S 108.862 VIIIe / 2Tg; PA β? / 2200),

weiches dadurch gekennzeichnet ist, daß zunächst eine Si B.Schicht dann auf dieser eine SiOg-Schicht abgeschieden, v/ird, daß die Oberfläche der SiOp-Schicht mit Fotolack bedeckt wird, daß dieser Fotolack lokal belichtet und entwickelt wird, daß auf die hierdurch freigelegten Stellen der darunterliegenden SiOg-Schicht ein Ätzmittel zur Einwirkung gebracht ■wird,welches zur Auflösung von SiOp befähigt ist und dabei die Fotolackschicht nicht zerstört, daß nach'Freilegung der darunterliegenden Teile der Oberfläche der Si^N^-Schicht diese bis zur darunterliegenden Halbleiteroberfläche durch Einwirkung von heißer Phosphorsäure-an den durch die verbliebenen Teile der SlO^-Schicht nicht geschützten Stellen weggeätzt wird. ' . '--..;soft is characterized in that initially a Si B. layer then deposited on this a SiOg layer, v / ird, that the surface of the SiOp layer is covered with photoresist is that this photoresist is locally exposed and developed that on the thereby exposed areas of the underlying SiOg layer brought an etchant to act ■ which is capable of dissolving SiOp and thereby the photoresist layer is not destroyed that after 'exposure of the underlying parts of the surface of the Si ^ N ^ layer this to the semiconductor surface underneath by the action of hot phosphoric acid on the remaining ones Parts of the SLO ^ layer are etched away from unprotected areas will. '. '- ..;

Die auf diese Weise hergestellte Schutzschichtmaskierung wird in üblicher Weise als Diffubionsmäskiorung bei der HerstellungThe protective layer mask produced in this way is in the usual way as a Diffubionsmäskiorung in the production

Ί6Η569Ί6Η569

PA 9/493/877 - 6-PA 9/493/877 - 6-

von Richtleitern, Iransistoren und anderen Halbleiterbauelementen, insbesondere nach der Planartechnik, verwendet.of directional conductors, transistors and other semiconductor components, especially according to the planar technique.

1 Patentanspruch1 claim

" BAD ORtQiMM. 7 -"BAD LOCATION QiMM. 7 -

D-O9844/04 13-D-O9844 / 04 13-

Claims (1)

PA 9/493/877 - 7 -■PA 9/493/877 - 7 - ■ Pat e η t a η s ρ r u c hPat e η t a η s ρ r u c h Verfahren zum Herstellen einer Schutzschicht an der Oberfläche eines Halbleiterkörpers, bei dem eine aus Siliciumoxid und eine aus Siliciumnitrid bestehende Schicht an der Oberfläche eines Halbleiterkristalls unmittelbar übereinander durch Abscheiden der Sch-utzüchichtmaterialien aus der Gasphase gewonnen werden, bei dem während des gesamten Absciieidungsprozesses ein zur Abscheidung von Siliciumnitrid befähigtes Reaktionsgas verwendet und diesem Reaktionsgas während eines Teils des Abscheidungsprozesses ein zur Abgabe von Sauerstoff befähigtes Reaktionsgas in einer solchen Konzentration zugemischt wird, daß neben mindestens einer zusammenhängenden Schicht aus Siliciumnitrid mindestens eine zusammenhängende Schicht aus Siliciumoxid an der gleichen Stelle der Halbleiteroberfläche abgeschieden wird, nach Patent ......... ..Pat.Anm. S 108.862 VIIIc/21g; PA 67/2200), dadurcli gekennzeichnet, daß zunächst eine Si^K.-Schicht, dann auf dieser eine SiOp-Schicht abgeschieden wird, daß die Oberfläche der SiOp-Schicht mit Fotolack bedeckt wird, daß. dieser Fotolack lokal belichtet und entwickelt wird, daß auf die hierdurch freigelegten-"Stellen" der darunterliegenden Si0o-Schic}\t ein Ätzmittel zur Einwirkung gebracht wird, welches zur Auflösung von SiOg befähigt ist und dabei die Fotolaekschiclit nicht zerstört, daß nach Freilegung der darunterliegenden Seile der Oberfläche der Si5H*-Schicht diese bis zur darunterliegenden Hallileiteroberflache; durch Ein-Method for producing a protective layer on the surface of a semiconductor body, in which a layer consisting of silicon oxide and a layer consisting of silicon nitride on the surface of a semiconductor crystal are obtained directly one above the other by deposition of the protective layer materials from the gas phase, in which a deposition is carried out during the entire deposition process reaction gas capable of silicon nitride is used and a reaction gas capable of releasing oxygen is added to this reaction gas during part of the deposition process in such a concentration that, in addition to at least one continuous layer of silicon nitride, at least one continuous layer of silicon oxide is deposited at the same point on the semiconductor surface, according to patent ......... ..Pat.Not. S 108.862 VIIIc / 21g; PA 67/2200), characterized by the fact that first a Si ^ K. layer, then a SiOp layer is deposited on this, that the surface of the SiOp layer is covered with photoresist, that. this photoresist is locally exposed and developed so that an etchant is brought into action on the "spots" of the underlying SiO o -chic which is thereby exposed, which is capable of dissolving SiOg and thereby does not destroy the photoresist, that after exposure of the underlying ropes of the surface of the Si 5 H * layer, this up to the underlying Hall conductor surface; through a- 009844/0413009844/0413 ■■: ■"..■■-■■.-. : .■ BADOHlOfNAL -8- '■■ : ■ ".. ■■ - ■■ .-.:. ■ BADOHlOfNAL -8- ' ΡΛ 9/493/877. . - 8 -ΡΛ 9/493/877. . - 8th - wirkung τοπ heißer Phosphorsäure an den: durch die verbliebenen Teile der SiO^-Schicht nicht geschützten Stellen weggeätzt wird.effect τοπ hot phosphoric acid on the: by the remaining Parts of the SiO ^ layer not protected places is etched away. - ■ BAD ORIGINAL 0 098 kA/0413,- ■ BAD ORIGINAL 0 098 k A / 0413,
DE19671614569 1967-03-16 1967-07-26 Method for producing a protective layer consisting of silicon nitride on the surface of a semiconductor body Pending DE1614569A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1614455A DE1614455C3 (en) 1967-03-16 1967-03-16 Method for producing a protective layer consisting partly of silicon oxide and partly of silicon nitride on the surface of a semiconductor body
DES0111013 1967-07-26

Publications (1)

Publication Number Publication Date
DE1614569A1 true DE1614569A1 (en) 1970-10-29

Family

ID=25998753

Family Applications (2)

Application Number Title Priority Date Filing Date
DE1614455A Expired DE1614455C3 (en) 1967-03-16 1967-03-16 Method for producing a protective layer consisting partly of silicon oxide and partly of silicon nitride on the surface of a semiconductor body
DE19671614569 Pending DE1614569A1 (en) 1967-03-16 1967-07-26 Method for producing a protective layer consisting of silicon nitride on the surface of a semiconductor body

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE1614455A Expired DE1614455C3 (en) 1967-03-16 1967-03-16 Method for producing a protective layer consisting partly of silicon oxide and partly of silicon nitride on the surface of a semiconductor body

Country Status (6)

Country Link
AT (1) AT275610B (en)
CH (1) CH474853A (en)
DE (2) DE1614455C3 (en)
FR (1) FR1562343A (en)
GB (1) GB1164418A (en)
NL (2) NL6716606A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3590337A (en) * 1968-10-14 1971-06-29 Sperry Rand Corp Plural dielectric layered electrically alterable non-destructive readout memory element
JPS6022497B2 (en) * 1974-10-26 1985-06-03 ソニー株式会社 semiconductor equipment
JPS5193874A (en) * 1975-02-15 1976-08-17 Handotaisochino seizohoho
US4196232A (en) * 1975-12-18 1980-04-01 Rca Corporation Method of chemically vapor-depositing a low-stress glass layer
JP2004109888A (en) * 2002-09-20 2004-04-08 Yasuo Kokubu Optical waveguide and its manufacturing method
KR101793047B1 (en) * 2010-08-03 2017-11-03 삼성디스플레이 주식회사 flexible display and Method for manufacturing the same

Also Published As

Publication number Publication date
NL6716606A (en) 1968-09-17
DE1614455C3 (en) 1979-07-19
CH474853A (en) 1969-06-30
DE1614455A1 (en) 1970-03-05
NL6802821A (en) 1969-01-28
GB1164418A (en) 1969-09-17
DE1614455B2 (en) 1975-10-30
AT275610B (en) 1969-10-27
FR1562343A (en) 1969-04-04

Similar Documents

Publication Publication Date Title
DE3125054C2 (en)
DE2922791C2 (en) Process for dry etching of aluminum and aluminum alloys
DE1614999A1 (en) Method of manufacturing semiconductor devices having a dielectric layer corresponding to a predetermined surface pattern on the surface of a semiconductor body
DE2930293A1 (en) ACTION PROCESS IN PRODUCING AN OBJECT
DE2658448C3 (en) Process for etching a layer of silicon nitride applied to a semiconductor body in a gas plasma
DE1232931B (en) Process for the partial doping of semiconductor bodies
DE3627311A1 (en) METHOD FOR ETCHING SILICON
DE2213037A1 (en) Process for the production of semiconductor components using dry-etched techniques
DE3024084A1 (en) METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS
DE1544273A1 (en) Process for diffusing doping material presented from the gas phase into a semiconductor base crystal
DE2227344C3 (en)
DE2432719A1 (en) PROCESS FOR CREATING FINE STRUCTURES FROM VAPORIZABLE MATERIALS ON A BASE
DE2727788C2 (en) Method for producing a pattern in a surface layer of a disk-shaped body
DE1614569A1 (en) Method for producing a protective layer consisting of silicon nitride on the surface of a semiconductor body
EP0166893B1 (en) Dry-etching process
DE2504500A1 (en) METHOD FOR PRODUCING A PATTERN FROM ONE OR MORE LAYERS ON A SURFACE BY THE LOCAL REMOVAL OF THIS LAYER OR LAYERS BY SPUTTER ETCHING AND OBJECTS, IN PARTICULAR SEMI-CONDUCTOR ARRANGEMENTS, WHICH ARE USED THIS PROCESS
DE2100154C3 (en) Method for applying an oxide protective layer of predetermined shape to a surface of a semiconductor substrate
DE2020531C2 (en) Process for the production of silicon ultra-high frequency planar transistors
DE2900747C2 (en) Method for manufacturing a semiconductor device
DE2243011C3 (en) Method for producing a thermocompression contact
DE2307754A1 (en) Multilayer electrical conductors mfr. - by forming contacts by partial etching of coated substrate
DE1564849C3 (en) Method for producing a protective layer on a semiconductor body
DE2348779C3 (en) Process for making etched patterns
DE2804830A1 (en) Monolithic integrated semiconductor circuit prodn. - involves forming two passivating layers on chip surface, with contact windows plasma etched
DE4315435C2 (en) Method for the selective etching of insulating and buffer layers arranged on a semiconductor substrate