DE1589067C - Method for the production of a semiconductor arrangement intended in particular for use in microwave technology - Google Patents

Description

to divide that each semiconductor device a ring. The task becomes in a process of monotonous Surface area around the respective type mentioned above is solved according to the invention by contains distant surface location. The cut out that for contacting one or a few Semiconductor elements are then according to the electrode areas a compared to that in the intended use as diodes or tran- the order of magnitude of 5 μm lying diameter

3 4

the openings in the insulating layer have a thinner tip with a large number of small openings 30

of a wire unspecifically over the surface of the iso of approximately the same size, in which the SiIi-

layer is guided until it is exposed in an opening single surface. The manufacture of the

snaps. Openings 30 can be made, for example, with the aid of a

For the embodiment of the invention, proposed 5 photographic etching processes are carried out,

gen that a semiconductor wafer made of silicon use. When using silicon oxide as an insulating layer

is det and the barrier layer in the electrode 23 can be openings with a smallest diameter

range "is formed by palladium silicide ^{. achieve a knife of about 3 x 10 ~ 3} mm. The number

One possibility is that the one with that of the openings 30 is square in the case of a square The surface side provided with the insulating layer opposite the semiconductor element with the dimensions 0.5 · 0.5 mm lying surface side of the semiconductor wafer with a few hundred. In a special implementation at one Metallic connecting body over a large area for a semiconductor element consisted of the insulating bonds will. layer 23 made of silicon oxide, which has a layer thickness of

When arranged according to the method, each is approximately 0.4-10 ~ ^s mm. The openings 30 of the opening in the electrical insulating layer of an insulating layer had a diameter of countersink with a bottom metal electrode or 5 x 10 ^-3 mm and were in a mutual abutment of a metal layer that was in contact with the active layer of 20 · 10 ~ ^s mm arranged.
Zone of the element. With the help of a pointed To produce a PN barrier layer, three lead wires can be used, which can be used in one of the openings.
A substantially ohmic contact can be used. Instead of just one of the semiconductor element 21 likewise with an insulating lead wire, several lead layers can also be provided. Then the 'half wires are provided, each of which forms a connection for the conductor element for metal plating in a separate electrolyte electrode. The positioning 35 table bath used, whereby on the exposed and attachment of the lead wires, metal electrodes can be electroplated onto the silicon surface as a result of their untargeted guidance over the surface. Gold can, for example, be provided in front of the insulating layer as the electrode metal without visual monitoring. When connecting the to be taken. . Electrode metal with the semiconducting silicon surface

In the case of a semiconductor diode, each of the 30 surfaces is known to be formed on the silicon surface.

an opening of the insulating layer defining the active zone surface a P.N barrier layer of the Schottky type.

a rectifying barrier, e.g. B. a PN blocking The second method is to use the open

layer. Such layers can have a suitable gas phase in the most varied of voltages.

Can be produced in a way, e.g. by means of metal plating borrowed dopants in the semiconducting silicon

tion to form a Schottky boundary layer, diffuse through the surface and thereby create a PN

Solid diffusion or by alloy. To form the second boundary layer. For high frequency components

The electrical connection in such diodes is made by the elements generated by such diffusion

A large-area contact on the other top layer is kept extremely thin. The line type

surface side of the semiconductor wafer formed. of the dopant is the conductivity type

A special feature of the arrangement after the 40 silicon wafer opposite. After completion

Processes are spatially densely packed. Diffusion is also applied here

neteh, numerous active zones. . Metal electrodes 24 (Fig. 2) in an electrolytic

The invention is based on the bathroom in the drawing tables.

illustrated embodiment explained in more detail; 'The metal electrodes 24 can, however, be omitted,

it shows 45 when a barrier effect between metal

Fig. 1 is a plan view of the insulating layer of an electrode and the silicon surface are omitted.

• Semiconductor wafer with a large number of openings that can. This is the case, for example, when

small dimensions and the barrier layer through a ■ palladium silicide layer

F i g. 2 the cross-section of a is formed according to the invention.

according to the method produced arrangement with 50 A third method consists in the PN blocking

to form a semiconductor wafer, an insulating layer and a layer by alloying,

mechanical encapsulation. Following the manufacture of the PN blocking

The in Fig. 1, the semiconductor element 21 becomes a prefabricated element 21 is from a larger, for several half-assemblies of the one shown in FIG. 2 shown semiconductor array conductor elements common semiconductor body with 55 voltage 20 inserted into an insulating housing 29, a diameter of 12 mm, for example, or an inserted into the housing 29 is more metal cut out. The dimensions of the individual Lischer connection body 27 with that of the insulating layer square semiconductor elements 21 are in 23 opposite surface of the semiconductor element, -this Trap 0.5 · 0.5 mm .. Mentes 21 conductively connected. To improve this

In the process, a disk 22 of 60 "contact can be made on the relevant surface of the

semiconducting monocrystalline silicon assumed 'semiconductor element' in a previous

which, for example, cut a metal plating 28 by means of epitaxial growth '

will provide. Be on one surface of the silicon.

Disk 22 is initially in a first process- The connection of the very narrow, with the PN step contacted a boundary layer of the semiconductor earth 21 by means of oxidation or vapor deposition Insulating layer 23 made of silicon oxide or other metal electrodes 24 is appropriated by a sharp one Substances, for example organic substances, made of pointed wire 25, the tip of which into a upset. The insulating layer 23 of the openings 30 is then engaged in the insulating layer 23

and against the metal electrode 24 located at the bottom of the opening 30. In the above-mentioned specific exemplary embodiment, a gold wire with a diameter of 25 × 10 -4 ^{: 1} mm was used as wire 25, the end portion of which was pointed by means of an electrolytic etching process. Instead of gold, other suitable materials can also be used for the wire 25, provided that they do not have excessive rigidity and spring hardness, which could lead to an impermissibly high tip pressure.

Since a contact between a single metal electrode 24 and the to produce a diode Wire 25 is sufficient, the wire 25 with its holder 26 serving as a connection only needs in Contact division to be brought .. The tip of the wire 25 either engages directly in a any opening 30 or can be made by a slight transverse displacement on the insulating layer 23 in an opening 30 can be snapped into place. In this way it is possible to make contact with the semiconductor element 21 with the required external connections without visual aid.

Another advantage of the semiconductor arrangement produced by the method according to the invention

ία 20 results from the fact that the wire tip contact an ohmic contact with the metal electrode 24 or, in the case of a paladium silicide layer, with the semiconducting layer itself and practically does not cause any parasitic capacitances in the diode. Also the inductance of the wire arrangement used for making contact is very low.

1 sheet of drawings

• 1

Claims (3)

i 2 sistors each at the remote surface interface. single or multiple; doped and with connection. provided wires for each semiconducting layer. 1. A method for producing a particular It is also known (German patent for use in microwave technology 5 829 191), for the targeted selection of highly conductive ones certain semiconductor device, in which on surface sites of a semiconductor device in the one surface side of a semiconductor wafer concerned surface to etch a RiHennetz, the a layer of electrically insulating material Rillef with · 'an -'Isölierrhasse'-to cover and the is formed, in which a multitude of very "pre-treated" HalrjIeifera'nordnung in one metallize small openings of approximately the same size with an ip electroplating bath. The thick of the is brought so that the semiconductor surface in. the surface plate between the covered These openings are exposed and correspond to the metal layers applied to the grooves exposed surface areas of half the size of the forward resistance of the bezel Electrode areas with an identical surface point, so that the active, i.e. H. Directional barrier layer are formed, on which 15 highly conductive surface parts a substantially to produce an ohmic connection, have a thicker metal layer than the less ac connection a lead wire can be attached, tiven places. A selection of this thicker metal thereby characterized in that, for coating, it is achieved that by placing one or a few of the electrodes on the metallized surface, one or a few of the electrodes of a metal foil electrode areas (24) a compared to the in so electrical connection between these thicker the order of magnitude of 5 μπί lying through metal layers is produced. But there the metal knife of the openings (30) in the insulating film essentially parallel to the relevant one (23) thinner tip of a wire (25) unspecified surface of the. Semiconductor device is guided, - Extraordinarily strong additional capacitances arise over the surface of the insulating layer (23) until it enters one of the openings. (30) 25 an application of the known arrangement for clicks into place. ■ exclude higher frequencies. 2. The method according to claim 1, characterized in that a further method for the targeted selection of indicates that a 'semiconductor wafer (22) is active surface sites from the Canadian made of silicon is used and the barrier layer known from patent specification 605 489, in which, on the in the electrode areas (24) by palladium 3 ° related semiconductor surface a plurality of silicide is formed. Electrodes is soldered and only certain, means 3. The method according to claim 1, characterized in measurement selected electrodes with connecting wire, that the are provided with the insulating layer th. - · (23) provided surface side opposite it .. is also known (German patent, lower surface side of the semiconductor wafer (22) 35 840407), diodes for use in the microwave with a metallic connection body (27) technology (centimeter wave area) in the way is connected over a large area. form that a semiconducting disc against the pointed ■. . End of a tungsten wire is pressed, whereby __: Tungsten atoms in the semiconductor material in the area Diffuse 40 of the indented wire tip, and open 'This way a barrier is formed.' Such The invention relates to a method for tip diodes have an inductance and Production of a low-capacitance junction connection, in particular for the application, but 'is that Semiconductor dielectric strength determined in microwave technology as a result of the blocking order described, where there is relatively little formation of a layer on one surface side. Higher chip semiconductor wafer a layer of electrically insulating strength values are provided by semiconductor diodes the material is formed in which a large number of diffused PN boundary layers can be achieved, of very small openings of approximately the same size, but with such diodes there is a frequency limit is introduced so that the semiconductor surface in .- * is set by the fact that with the boundary layers or these openings is exposed, and in the case of the terminals connected to the free 50 the other active zones laid surface areas of the semiconductor wafer additional inductances and parasitic capacitances Generate electrode areas with a rectifying blocking. An avoidance of this frequency limit layer be formed on which to produce zenden phenomena at an economically unite Ohmic connection is not yet a production expense that can be stepped on for the supply line wire can be attached. "'55 successful..' ■. .. ■ It is known (ÜSA.-Patent 3 025 589) to The object of the invention is to provide a VerHerstellung a large number of semiconductor arrangements go to the production of a, in particular for the an (diodes or transistors) from a single half-one determined with use in microwave technology Silicon oxide layer coated silicon wafer to indicate conductor arrangement in which the active the silicon oxide layer on circular, the number 60 junction areas on the semiconductor surface the intended semiconductor arrangements correspond to extremely small dimensions and the Andes Surface points by etching or the like distant and then the silicon wafer are such;