DE1574528A1 - Method and device for the determination of test characters of any given number - Google Patents

Description

"Any method and device for determining test marks predetermined number ". The invention relates to a method and an apparatus for calculating check digits of any number from information data and for the control of information data secured with it, their individual characters Numbers from a residual class system mod M are permanently assigned.

The data generally consists of a sequence of characters a given set of characters (decimal digits, alphabet, etc.), which also includes the check characters can be removed. The test marks are determined in a systematic manner from the information signs, in such a way that as many errors as possible arise reveal. To do this, each character is first assigned a number from a suitable one Residual class system mod M (M prime number ": z: character set) assigned. The individual Characters can of course also be sub-coded in binary, or they can be in the case of binary data, combine several binary digits into one character. the Check marks are then weighted checksums in the selected residual class system won. With a suitable choice of weight you get an optimal protection.

A procedure has already been registered in which such test marks can be generated with a suitable weight sequence. This Procedure has however, compared to the one described here, the disadvantage is that it is a much higher rate Requires effort for the production of the test mark.

The invention is characterized in that for each check digit a memory is used that each time a character is entered, the associated Number is added to the content of the first memory Spl mod M, the resultant Content is added to the content of the next memory Sp2 mod M, etc., and that after entering and processing the last information character in the reverse processing sequence the contents of the penultimate memory are added to the contents of the third last memory becomes u.s.f. and in this first step, after the input has been completed, the content of the first Memory is set, then in a corresponding second step. The content of the second memory is determined and so on, until finally the determination of the Contents of the third from last memory, and that the last memory contents received the test marks result.

The procedure described here does not require any explicit storage of the weight sequences and comes with a single memory location for each test character the end. It therefore has the advantage of determining or testing the test mark when it is optimal To enable protection with extremely little effort.

In the following, the method of operation of the method is shown using the example of a Systems with p = 5 test characters, with which m = 7 information characters in the residual class system mod M = 11 are secured, are explained in detail. The information signs can be designated in sequence with al to a7. Before starting, the content all memories set to 0. In the first step, a1 becomes the content of the first memory Spl added, the result to the content of the second memory Sp2, etc. ' so that in the end the content a1 is in all memories.

In the second step, a2 is added to the content a1 of the first memory Spi, so that the value a1 + a2 arises in this. This content is added to the content of the second memory Sp2 and results there in the result 2a1 + a2 etc.: In this way the contents in the memories after the 2nd step result: (Spi): a1 + a2 (Sp2): 2a1 + a2 (Sp3): 3a1 + a2 (Sp4): 4a1 + a2 (Sp5): 5a1 + a2 The 3rd step results in the following status: (Spi): a1 + a2 + a3 (Sp2): 3a1 + 2a2 + a3 (Sp3): 6a1 + 3a2 + a3 (Sp4): 10a1 + 4a2 + a3 (Sp5): 15a1 + 5a2 + a3 Furthermore, after step 4 you get: (Spi): a1 + a2 + a3 + a4 (Sp2): 4a1 + 3a2 + 2a3 + a4 (sp3): loai + 6a2 + 3a3 + a4 (Sp4): 20a1 + 10a2 + 4a3 + a4 (Sp5): 35a1 + 15a2 + 5a3 + a4 after step 5: (SP1): a1 + a2 + a3 + a4 + a5 (SP2): 5a1 + 4a2 + 3a3 + 2a4 + a5 (Sp3): 15a1 + 10a2 + 6a3 + 3a4 + a5 (SP4): 35a1 + 20a2 + 10a3 + 4ad + a5 (Sp5): 70a1 + 35a2 + 15a3 + 5a4 + a5 after step 6: (Col1): - a1 + a2 + a3 + a4 + a5 + a6 (Sp2): 6a1 + - 5a2 + 4a3 + 3a4 + 2a5 + a6 (Sp3): 21a1 + 15a2 + 10a3 + 6a4 + 3a5 + a6. (SP4): 56a1 + 35a2 + 20a3 + 10a4 + 4a5 + a6 (Sp5): 126a1 + 70a2 + 35a3 + 15a4 + 5a5 + a6 after step 7: (SP1): a1 + a2 + a3 + a4 + a5 + a6 + a7 (Sp2): 7a1 + 6a2 + 5a3 + 4a4 + 3a5 + 2a6 + a7 (Sp3): 28a1 + 21a2 + 15a3 + 10a4 + 6a5 + 3a6 + a7 (SP4): 84a1 + 56a2 + 35a3 + 20a4 + 10a5 + 4a6 + a7 (Sp5): 210a1 + 126a2 + 70a3 + 35a4 + 15a5 + 5a6 + a7 or in formulas, in @ memory Spv after step / u the content: After step 7 (entering the last information character) the two test characters P4 and P5 have already been created and are available in the last two memories Sp4 and Sp5. For determination of the other test marks, the processing direction is reversed and now assumed from the penultimate memory column 4. After step 8, the following new memory entries result hold: (SP3): 112a1 + 77a2 + 50a3 + 30a4 + 16a5 + 7a6 + 2a7 (SP2): 119a1 + 83a2 + 55a3 + 34a4 + 19a5 +: - 9a6 + 3a7 -, #, (Sp1): 120a1 + 84a2 +, 56a3 + _35a4 + 20a5 + 10a6 + 4.g7 The last-mentioned memory (Sp1) thus contains the test digit chen P1. . In step 9, processing starts again from Sp4 repeated, but only up to the memory S%, in which there-. with another test mark P2. The new storage contents after step 9 are: (SP3): 196a1 + 133a2 + 85a3 + 50a4 + 26a5 + 11a6 + 3a7 (SP2): 315a1 + 216a2 + 140a3 + 84a4 + 45a5 + 20a6 + 6a7 Finally, in the last step, there is what is still missing Certification mark for: (Sp3): 280a1 + 189a2 + 120a3 + 70a4 + 36a5 + 15a6 + 4a7 In terms of formula, the Pv test marks obtained in this way can be mean by .: (v = 192 ... p) with the desired number p of test characters and with m = M +.1 - p as the number of information characters, as can be easily verified by induction conclusion: If the actual number of information characters is lower, these are supplemented by fixed characters, e.g. zeros, to the desired number . The following values are obtained as weights according to this procedure: (v = 1,2, ..., p) (ji = 1,2, ... 9 m) 0 An optimal protection is obtained, -if all determinants and sub-determinants, which can be formed from the weight matrix, from 0 are different. The shape (2) of the weights fulfills this requirement, which ensures the optimality of the protection. The drawing shows exemplary embodiments of circuit arrangements for carrying out the method FIG. 1b shows an arrangement with single switchover and buffer memory, FIG. 2 shows the use of counters connected in series. In Fig. 1a, the incoming character is stored in the recording memory Spo. Sp1 to Sp5 designate the memories for receiving the check characters, which are set to 0 at the very beginning. The memories can consist of bistable multivibrators and can be connected as shift registers, for example. In each step of the input part, first the memories Spo and Spl are applied to the input of the mod-M adder Ad by means of the switch S and the result na h $ p is stored.

nd Sp2 The content of (Sp1) '/ then arrives in a mod-M adder Ad and its result after Col2 etc. After the input has been completed, the content of the penultimate The memory (Sp4) and the third from last memory (Sp3) in Ad are added and the result stored in the latter Sp3 o The sum of the contents of (Sp3) is then and (Sp2) formed and brought to Sp2, as well as the sum of the contents of (Sp2) and (Sp1) after Sp1. The next step is the same process until it is saved Repeated in Sp2 and in the last step until it is saved in Sp3o. For the sake of simplicity of the switch S, a buffer spa can also be used temporarily stores the respective result of the adder and / or as an input memory one of the summands of the adder is used. The latter case is detailed in FIG. 1b. By means of a clock switch T, the sum of the contents of the buffer is set in clock position 1 and the memory connected via switch S1 and somewhat delayed cached in memory spa. Then takes place in clock position 2 the Restore in the connected memory, so that afterwards the sum in both Save and the switch S1 moves to the next position. Become common the check numbers are not required in parallel, but one after the other, so that the Memory must be queried one after the other. In this case it can be used that the test characters are formed in a temporal sequence and can already be used at the moment of final formation. In addition the output of the mod M adder Ad is tapped each time a final Memory content is determined. Are the memories Spl to Sp5 as mod-M counters Z1 up to Z5, the adder, along with the recording and intermediate memory, can be omitted. With a number of pulses corresponding to the incoming character a @, the counter Z1 advanced by a @ positions. The M further impulses get the Counter Z1 again in the same position, while the pulses after the 0 passage of the counter Z, also run into the counter Z2 and thus cause an addition. By M pulses into the counter Z2 and coupling of the counter Z3 after the zero crossing an addition is effected in the last counter, etc. An arrangement is corresponding here Fig. 1a with the omission of Ad and Spo with the same switch guide S possible. However, an arrangement according to FIG. 2 can also be selected. According to each arriving Character aIU get a @ + K o M pulses in the counter Z1, all pulses after the 1st zero crossing of this counter also in counter Z2, all pulses after the 1st Zero crossing of this counter also in the counter Z3 etc. K is a whole number which is either determined by the fact that at least one zero crossing of the penultimate one Counter occurs or which is chosen to be fixed at K = p r 1. After input and processing of the last information character there are already two test characters in the last two Counters. To determine the remaining test marks (not shown in FIG. 2) K # M pulses in the penultimate counter, all pulses after its zero crossing as well in the third from last counter etc. K is again an integer that goes through the requirement for a zero crossing of the first or second Counter is established or is established by K = p-2. After this step it is first test character in meter 1. To determine the second test character (in the case P.> 3) g # M pulses run into the penultimate counter and a corresponding one in the same way Part in the previous counter, but now only up to the 2nd counter. counter Z1 is now disconnected. In the next step, counter Z2 is disconnected, see above that the counter readings of counters Z1 and Z2 are no longer changed, etc. The process ends with the disconnection of the third from the last meter or immediately before. The test marks can be taken directly or from the resulting counter readings can be obtained by recoding, e.g. by forming a complement. Will only If three test marks are desired, the processing direction can also be reversed be waived. After entering and processing the last information character can . two test characters can be taken from the last two memories, as well as the third test mark in this case after a further step, which of the additional Entering a 0 corresponds to the middle memory location, the check characters are available then not available at the same time, but the middle memory contains first the second test mark and after a further step the third test mark, with which the second test mark is deleted.

Claims (2)

PATETTTANSPRÜCHE 1. Any method for calculating check digits specifiable number from information data and for the control of secured Information data, the individual characters of which are numbers from a residual class system mod M are permanently assigned, characterized in that a memory for each check digit it is used that after each input of a character the corresponding number is added to the content of the first memory Spl mod M is added, the resulting content to the content of the next memory Sp2 mod M is added and so on, and that after input and processing of the last information character, if the processing sequence is reversed, the content of the penultimate memory is added to the content of the third last memory u.s.fo and In this first step, after the input has been completed, the content of the first memory is determined, then in a corresponding second step the content of the second Memory is determined and so on, until finally to determine the content of the third from last memory, and that the last memory contents received the check characters result. 2. The method according to claim 1, characterized in that the check number / a can be derived from the memory contents, e.g. through complement formation. 3. The method according to claim 1 or 2, characterized in that the check numbers are obtained one after the other from the results of the corresponding additions which result in the final memory contents. 4. A method for determining three test characters according to claim 1 or 2, characterized in that after entering the last information character two of the test characters aua the last two memories and then the third after a wide. ren step can be obtained from the penultimate memory according to an additional input of a 0 without reversing the processing direction. 5. The method according to claims 1 to 4 for checking data groups which already contain the check characters, characterized in that the check characters are determined again from the information data and compared with the check numbers and if they do not match, an error signal or an error display is issued. 6. Arrangement for performing the method according to claims 1 to 4, characterized in that a recording memory (Spo) is provided for the successively arriving numbers assigned to the individual information characters and a switch (S) connects the output of the recording memory to the input of the first Check-character memory (Sp1) or the output of any check-character memory with the input of the respectively following or preceding check-character memory via a mod M adder (Ad). 7. Arrangement according to claim 6, characterized in that an intermediate memory (Spa) is provided which receives the respective result of the mod M adder (Ad) and / or supplies a summand for the mod M adder (Ad). 8. Arrangement for carrying out the method according to claims 1 to 4, characterized in that the test character memory (Sp1, Sp2 ...) are designed as mod M counters that the numbers assigned to the individual information characters by an equal number of pulses are shown and that a switch (S) connects the counting inputs of adjacent counters. 9. An arrangement according to claim 8, characterized in that for adding the contents of two mod M counters (e.g. Sp1, Sp2) the first mod M counter M receives counting pulses and after the zero crossing of this first counter, the counting inputs of the two mod M- Counters are connected in parallel so that the second counter receives the counting pulses that still arrive. 10. Arrangement according to claim 8 and 9, characterized in that all counters are connected in series and after the zero crossing of a mod-M counter, depending on the processing direction, either the previous one. or the following mod M counter receives the counting pulses that are still arriving, the first counter entering a number with an equal number of pulses plus an integer multiple of M pulses or the penultimate counter for calculating the check numbers after the input has been completed the penultimate counter receives integer multiple of M pulses.