DE1549758C - Arrangement for the display of information on the screen of a television periscope - Google Patents

Description

5 6

Control circuit to be transmitted to the picture tube. The lines of chalk each have 18 information symbols on the

can be displayed in one another screen in a track of the drum store.

nested spaces of two consecutively By the aspiration to a more extensive readable series of numbers, each with eight numbers, is data and information processing at Schnelleine computational arrangement, d. This means that the Foicher place arrangement also exists at these storage working speeds is part of the computer trend that a surrounding system on the display devices. more comprehensive information, d. H. a larger number by the German Auslegeschrift 1178 622 was able to be represented by characters. To be able to Process for the batch transmission of data lends many information symbols in one to the image Known in an electrical calculating machine, io screen device underweighs associated runtime memory To spend time in a larger one in coded form would be in the case of an implementation according to the beSpeicher are located and those already proposed and mentioned above for several storage locations read into a smaller memory, the arrangement requires a long delay line, with a certain loan in each cycle. However, this design has the disadvantage that Storage location in the large memory is read out. 15 the signals are attenuated and distorted. To the ver-this Data transferred to the smaller memory avoid these disadvantages has already been proposed then retrieved from this and in a gene that the runtime memory from several parallel printers or display device should exist as information displayed delay lines be asked. which are connected in a cyclic sequence to the input and output of the data known arrangement will only become input data. U.S. Patent 3,150,324 is stores, which are then known in video signals to a transit time memory, which is converted from delay and get to the display. tion lines exist, after which the Si-In of the German patent application P 15 24 436.7-53 signals can be fed back to the input (German Auslegeschrift 1524 436) was already 25 den, so that a quasi-shortened run-time memory results in an arrangement for displaying information.

on the screen of a cathode ray tube. The various known devices for the presentation, in which the position of characters on a screen in a line of the picture tube are for Information signs to be displayed (or also Da-Zeit in their structure constructively complex and ten or called character) initially in coded 30 expensive. The aforementioned GeForm mentioned as known than video signals in a block are not sufficiently flexible, and the number of first entered into a run-time memory, the characters to be represented is through the fixed characters. The information signs of a space storage are limited. Display devices in the Image line from several in the vertical direction already proposed and briefly separated above have shifted horizontal beam deflections 35 written execution with run-time memories formed, with each horizontal beam deflection also having a relatively small capacity for Inforein Block corresponds. In the cyclical repetition symbol, since the individual blocks have a The runtime memory are all blocks that have the video relatively large length and these respectively signals of the In to be displayed on the screen contain larger empty areas at the block ends, Contain formation symbols, in rows at 4 ° assigned to the horizontal beam return arranged on the other side. A picture cycle of the elec- are; there are also control and synchronization signals tronenstrahis, which is used to display the entire in- to the runtime memory, which is related to each other Formation is used and the vertical provision and to the blocks have certain distances of the ray, corresponds in time to the cycle.

It is the object of the invention to provide an improved synchronization between the running arrangement for displaying information on the time memory and the control of the electron screen of a commercially available television beam. Since the temporal length of a block equals the temporal beam cycle to create the horizontal beam cycle using a transit time memory, which is deflection with only little additional effort, which also enables the blanked beam 50, includes a much larger amount of recirculation, result in the blocks, formation characters in the run-time memory of a run-time memory at their ends, areas that admit and that cyclically contain no video signals on the screen and thus display the useless repetitively. Thereby the for-empty spaces exist. In a preferred embodiment the new arrangement to the various data processing systems proposed for information-handling systems is given that the representation shown is the temporal block length in the moving information characters are clearly visible without flickering time memory or the Cycle time to the horizontal and that the new arrangement has a simple operating beam deflection of 65 μβ, including the time of voltage possibility, low susceptibility to failure and favorable 10 μ $ for the blanked beam return or 60 hours of production and maintenance costs,
the assigned space in each block of the runtime memory. The total time for an image solves that two revolutions of the running cycle for displaying the entire information time memory, which contains the blocks in two rows nested within one another or the length or the cycle time of the transit time, are assigned to one image cycle, the memory is 4800 με, including a vertical beam reset time of 714 μ8 in the first round in succession. The characters of the blocks of the second row and a light test capacity of this already proposed arrangement of the blocks of the first row as well as the representation comprises 144 characters to be displayed, with video signals in 8 lines on one half of the screen

7 8

takes place and that in the second cycle, at the end of which has the advantage of increased accuracy and the return of the beam to the starting position gives a better image display. The interlocking, a blanking of the blocks of the first and alternating consecutive memory row and a clearing of the blocks of the second memory blocks of the runtime memory therefore require the row as well as the display of their video signals on two revolutions or cycles to completely turn off the other half of the screen. reading and presentation of information. All blocks of the runtime memory resulting from this arrangement according to the invention have the same duration; compared to the period or the application P 15 24 436.7-53 (German interpretation cycle time for a horizontal beam deflection to 1524 436) already proposed and above io the screen, including the beam return arrangement Representation of characters at rung. The result is the best possible time for an image cycle and the use of the storage capacity of the runtime memory, the same time for the cycle of the horizontal beam because all memory blocks filled with video signals can become a character deflection to write a line. First half of the capacity of 378 characters compared to 144 characters in the memory blocks, ie a row of blocks, is read out, in the case of the already proposed version. and the characters are shown in the upper half of the screen. Below are the most important features. This invention is briefly explained in the second memory cycle. Then the reading out of the other half of the memory, It is essential that the new arrangement, i.e. the second row of blocks, these characters are a runtime memory and control devices for 20 displayed in the lower part of the screen. Repeated writing of the inputted information is then reset to contain the electron mation symbol, in connection with a write beam in its starting position. This takes place commercially available television set can still be used in the second write cycle of the run-time memory and that a synchronization between the and has the consequence that there is in the blocks in this loading-run time memory and the television raster. No video signals during the second storage cycle. The cycle time or the cycle time of the run can be stored or read out. In time storage less than the time for a picture cycle, these blocks are not occupied by video signals. H. less than the recording time of an information, appropriately binary coded signals, i.e. mation written on the screen including the beam BCD information,
reset time. There is an integer relationship, 30 The transit time memory is thus in such a way that for one picture cycle two revolutions or sections of the vertical beam return each two cycle times of the transit time memory required half filled with blocks, which are video signals. for the ■ first memory cycle, and the other half of the character display on the screen with blocks with BDC information. follows in connection with the runtime memory, where- 35 The memory is thus used to the maximum,
in the synchronization of the character recording Further essential features are that the device for cyclical Ausdas the block length in the transit time memory corresponds to a device for cyclic Ausdas the block length in the transit time memory, directing the electron writing beam and that takes place. The characters to be displayed are contained in the form of access to the transit time memory in synchronism with video signals in blocks of the transit time memory 40 of the beam movement takes place depending on, the blocks in alternating rows - a grid which the characters are arranged on the image sequence. Such a block or screen assigns defined places. The character memory segment called, includes the video signals display on the screen is generated by for a writing line in the character display. The one brightness modulation of the electron beam, sequence of a memory cycle, causes the video 45 whereby these control commands for modulation in the form of signals, which are stored in the successive blocks of video signals in the blocks of the running time of a block row, on the television memory .

tubes are given to generate a part of the characters to be displayed are from a

image, e.g. B. on the screen of the upper half. Input station, e.g. B. a keyboard, as parallel

It should be noted that binary coded data signals are entered and received under the designation 50

The line information (blocks) is then transferred to two parallel-connected transducers

are to be understood which stages in a cycle (circulation). In the converter stage, the BCD video

of the runtime memory are processed. The un converter, these signals become video signals

indirectly reshaped to the first adjoining second memory, and in the other one connected in parallel

chercycle then also supplies the video signals to the 55 converter stage, which are input in parallel

the picture tube for displaying the partial image on the BCD signals converted into BCD signals in serial form

lower half of the screen. The during the delt. The video signals are divided into the blocks of the

horizontal write beam deflection generated dark transit time memory in the first and / or second memory

len and lightened parts are inscribed from the same timing cycle. The BCD signals in

length of time. The run-time memory contains an odd '60 serial form which will be in alternating. Follow into the

Number of blocks; this ensures that blocks of the runtime memory are written into the

successive blocks of the runtime memory so section in which the vertical resetting of the

can be read out that the video signals are from the first electron beam. . ' ··

The storage cycle reaches the upper half of the screen · The output of the runtime storage is with the

and that in the second storage cycle the other "65 display device is connected. All in the runtime

Block row is read out and that these video memories are input video signals after two

signals on the lower half of the screen. Memory cycles read out; this corresponds to a full

The odd number of blocks in the runtime memory len image cycle. The sum of the video signals forms

9 10

the information is used on the screen of the television tube, unless expressly the Gemation, which is displayed at the input station, e.g. B. the opposite is said. That is, the logical _t keyboard has been entered. The BCD signals in circuits, e.g. B. the AND and OR circuits in serial form on the runtime memory can also generate a positive output signal if they are read out and z. B. positive signals are applied to a data processing 5 inputs,
management system. An advantageous embodiment of a screen information message can thus be typed in, shown on the display device in the block diagram of FIG. 1 and displayed on the screen, checked and then transmitted to the data showing the interaction of the various construction processing machines. Tip groups.

Errors or other types of errors can be identified by io. From the output of a keyboard 10, the Easily recognize visual inspection and accordingly use kor characters in the form of binary coded signals rig. A cable 11 to the two converters BCD video is timed by the continuously circling memory An image display of any length enables converter 12 and the parallel-to-series converter 13 is cleared and give the quality of the image display considerably. From a bit counter 14, time-dependent improved. 15 control signals to the two converter stages 12 and 13

The transit time memory is expediently via a cable 15. In the BCD video converter 12 from four delay lines connected in parallel, the BCD signals I As a result, when the memory is circled, the four signals are converted into video signals in serial form and j times the number of grid points for information via the line 20 to the transit time memory 21. In Representation delivered as if only one delay 20 to the parallel-to-series converter 13 are the parallel management would exist. The video signals for supplied BCD signals in BCD signals in Serialdie Write lines are converted into adjacent form in the runtime memory and arrive via line 22 ' bare even- and odd-numbered blocks are also used for the runtime memory 21. A central (}, ' stores, which in a nested clock generator 23 delivers over the lines 24 pulses or alternating order. 25 on the various assemblies, including the The run-time memory 21 written in the odd-numbered blocks. A write line 25 becomes Video signals are used to display images on the positive whenever video or BCD signals are in the given upper half of the screen, and the runtime memory 21 are written. The out video signals the even-numbered blocks get on input signals of the transit time memory 21 get over the lower half of the screen. During the image generation 30 the line 30 to an AND circuit 31. This On the upper half of the screen there is an AND circuit 31 receives a positive signal Memory circulation or a memory cycle. In doing so, the line 32 is at all times, with the exception of the times from the odd-numbered blocks in which the electron beam of the tube 33 read video signals by lighting the electron beam in the horizontal or vertical direction made visible, and the representation 35 is performed. This means that through line 32 a of the video signals in the even-numbered blocks, a positive signal level is applied to the AND circuit 31, suppressed by blanking. When writing, whenever there is a brightening of the electron beam The process of the lower half of the screen, however, is to take place in the screen tube 33; while the even-numbered Blocks to take effect and allow this time the video signals get out of the running line Lightening of the electron beam, while the 40 time memory 21 via line 30 of the AND-Schal video signals in the odd-numbered blocks through the device and the line 34 to the screen tube 33. Blanking can be suppressed. During the time of the return of the beam in horizontal

It is a feature of the invention and contributes to the valley or vertical direction, a negative Si

Improvement of the image quality when the input via the line 32 to the AND circuit 31

other nested memory blocks given a default 45; this prevents the transmission of further videos

direction are synchronized, which a light deo signal to the screen tube 33 initially sub-

and blanking of the video signals in dependent groups. A control unit 54 supplies the corresponding

the storage cycle. the signals for deflecting the electron beam in

The aforementioned features and advantages of the screen tube 33. Via the line 60 are

of the invention are better demonstrated by the 50 horizontal beam deflection signals and over

the following, more detailed description of the line 61 signals for vertical beam deflection

a preferred embodiment of this invention. kung delivered. These deflection signals are temporal

The circuit diagrams serve for a better understanding. controlled by pulses from the clock 23, wel-

It shows rather via the line 24 with the control unit 54

Fig. 1 is a block diagram of an arrangement connected to the 55. The impulses for the display of light and dark characters on the screen of a keystroke pass from the control unit 54 via the method tube according to the invention, line 32 to the AND circuit 31, which through

FIGS. 2 to 8a and 8b are graphs for explaining the line 34 connected to the screen tube 33

the storage and synchronization of the system. A time pulse for bit time 6 (BT 6) is sent by

1, 60 of the control unit 54 via the line 62 to the bit

F i g. 9 supplied in detail the run-time memory and counter 14, for synchronization of the same the bit mark control stage, already shown in with the write operation. The same signal to the bit block form in FIG. 1, time 6 is also on line 62 on the

Fig. 10 shows the details of the circuit of the horizontal marker bit control stage 55, also for syn-

zontal and vertical time control, also for chronizing purposes. This marker bit control stage 55

already shown in block form in FIG. 1. also receives timed signals via

For the description that follows, the input is the lines 63, 64, 65. From the marker bit control

For the sake of simplicity, it is assumed that a positive logic stage 55 is via the line 57 control signals

11 12

for the purpose of initiating the storage process on the point sequences of the beam deflection on the screen

Bit counter 14 given when information from the BCD of the screen tube 33 is displayed. With T ₁₁ is the

Video converter 12 or the converter 13 in the first point of the first writing line, this

Runtime memory 21 are to be written. The other points follow to the right up to the last one

Control signals on line 57 are also used for point T _{1106 of} this writing line 1. A writing line

Deletion of any marking bits in the consists of 128 point times; however are

Runtime memory 21 only effective for 126 points before information is stored on the screen,

mations. The screen is vertical in 143 horizontal writing

The following are the F i g. 2 to 7 explained, divided into tracks, as shown in FIG. 5 is indicated. With regard to the temporal assignment of the processes, FIG. 6 illustrates the character format or the time of the screen display of the information according to the small size for the screen display and is shown in FIG Cycle time of the runtime memory 21 with the width and 18 character cells in height. 4960 microseconds dialed. At the end of the last sequence, the entire picture is built up from 18 horizontal writing lines to 15 horizontal writing rows with 21 characters per character row. Each ray return is dispensed with and a vertical ray character cell again consists of a matrix which initiates the return; this point is in FIG. 2 is 6 bits wide and 8 bits high and the size one is labeled 69. The total cycle time of the ticker corresponds to. 5 of the 6 horizontal bits of the time memory is 4960 microseconds and is required for the display of characters by video corresponding to the transit time of the write beam in the 20 signals, and the 6th bit serves as a marking bit. The screen tube 33 in which the writing of this marker bit is cleared when the next corresponding time of 4192 microseconds and in adjacent characters is written, thereby the beam return time, which is kept 768 microseconds, also carries a horizontal distance between. The delay line according to FIG. 2 is un- two adjacent characters. The vertical spacing is divided into memory blocks, which range from 1 to 143 and 25 between two character rows results from the fact that KB 1 to KB 12 are numbered. How to suppress the lightening of the writing trace. Fi g. 2, these blocks are interleaved. This is achieved by arranging the 8th vertical telt or alternating, that is, every other bit in each character cell is not set. On the block belongs to the same block row. This has to the screen of the tube 33 can thus 18 * 21 = result that a two-time memory circulation is required- 30 378 characters are displayed as information,
is borrowed to write the stored signals. 7 shows the temporal relationships ben or read out. During the first memory between the delay line and the raster cycle, the blocks 1 to 77 can be written-in-shaped dot sequence for image display and the or can be read out and in the second memory cycle for the horizontal deflection and the vertical blocks 78 to 143 and KB 1 to KB 12. Every 35 kale resetting of the electron beam. This time memory block contains a synchronization signal for the diagram serves as an aid to understanding the in the horizontal beam deflection (see Fig. 2). The divisions shown in FIGS. 2 to 6; In addition, the synchronization contained in the memory blocks 1 to 77 is the synchronous interaction of the electromechanical signals as shown in FIG. 2 marked tronenstrahls of the screen tube 33 with the Laufnet with H 1, and they come into effect when the 40 time memories in the F i g. 2, 4, 6 and 7 can be recognized. Blocks 78 to 143 and KB 1 to KB 12 read out. It should be noted that according to FIG. 7 which will. The memory blocks 78 to 143 and KB 1 to vertical return of the electron beam at time KB 12 contain the synchronizing 9152 microseconds marked with H 2 , that is, before the siersignale; they are required when the end of the second circulation cycle of the runtime memory blocks 1 to 78 are processed. This means that it lasts 45 and up to 9920 microseconds, whereby the end of the second circulation cycle required for processing a memory block, synchronization signals are stored in the last bit position of the runtime memory and the start of a new one in the preceding block. The video first cycle for the next working period of information is represented in digital form in the memory. The time duration of the vertical back blocks 1 to 143 stored, and the keyboard signals 50 position of the electron beam is 768 microsein BCD form are in the memory blocks KB1 to künden and includes 24 horizontal deflections to KB 12. Symbols, characters and others 32 microseconds each. The resetting of the elec- tron beam can also be displayed on the screen in the vertical direction starting at the end and are stored as video information in the 143rd writing line as the horizontal beam return memory blocks. Each memory block 1 55 leading in the last writing line is not needed until 143 according to FIG. 2 contains the video signals. For a better understanding, how the memory blocks are used for horizontal electron beam deflection, that is to say in FIG. 2 are used to represent characters, a writing line. Such a horizontal jet is referred to FIGS. 8A and 8B. The steering for block 80 in FIGS. Figures 2 and 3 show F i g. 8 A shows a section from FIG. 2 and that a block of 21 bytes plus 2 spacing bits makes up the alternately consecutive feeds. 4 shows that one byte represents 1.5 memory blocks 6, 84 and 7 over time, the block 84 corresponding to light microseconds and that one byte is keyed into 6 bits and the other two blocks 6 and 7 are subdivided. Thus, the length of time that are blanked during this memory cycle. Memory blocks 80 in FIG. 3 32 microseconds since the block 84 is read out and is therefore light; this block scans 21 bytes of 1.5 microseconds 65 each. Fig. 8B shows the sawtooth-shaped curve duration and 2 bits of 0.25 microsecond time - the deflection voltage for the horizontal deflection Licher length includes. of the electron beam in a temporal context

In FIG. 5 are the bits corresponding to the memory blocks. The horizontal jet

13 14

Steering begins at the point labeled 71 , which is used to receive the input signals

and extends up to the designated 72 lines 20, 22, 24 and 25 are connected.

Period. From point 72 to point 73, the hori- These logical circuits control the

zontal beam return. This deflection cycle brings new information into the delay line unrepeatedly running. During the horizontal 5 gen 110 to 114 of the runtime memory 21. The And-

Beam deflection to the right from point 71 to 72. Circuit 119 controls rewriting from

if the electron beam is lighted, begin- memory output of signals fed back. All one

ending from point 74 to point 75; the information to be written off is sent via the

Sections 71 to 74 and ^: 7.5 to 72, on the other hand, are dark OR circuit 120 and the downstream AND-

groped. During the light keyed section 74 io circuits 121 to 124 to the delay line

to 75 are stored in block 84 videos 110 to 114 of the runtime memory 21. Via a

Information presented on the screen. Clock pulses are sent to the counter 125 on line 24.

then the write beam goes dark again This counter is reset by a signal

probes starting from point 75 through 72, 73, 71, which appears on line 126. The counter 125

74 of the subsequent deflection cycle. Introductory marker 15 serves as a frequency divider or pulse distributor and

Information bits, .which as synchronization signals 81 and 82 produce clock pulses to the AND circuits 121 to 124

are in the last bit position of the corresponding in a recurring order. The in the

chenderi blocks 6 and 84 set; detailed individual delay lines to be written

this will be described later. signals are sent to the inputs of the AND circuits

Fig. 8B further shows a complete hori- 20 121 to 124 and are given by the above

zontal beam deflection cycle, which 64 microseconds mentioned clock pulses of the counter 125 on the

d'en lasts. During this cycle time, the individual delay lines 110 to 114 are distributed,

electron beam scanned 32 microseconds for the purpose of the extracted from the delay lines

Representation of the video signals stored in block 84 arrive at AND circuits 127 to 130

Information, the remaining 32 microseconds of the 25 and from there via the OR circuit 138 to the

Beam deflections are blanked and contain line 30, which the read out signals to the

the sections to the left and right of the image and also the AND circuit 119 returns and, on the other hand, the

the beam return. The video information, signals also to the AND circuit 31 brings and from

stores in the blocks 6 and 7, after which there are over the line 34 to the screen of the tube

End of the 2nd cycle in the following the first corresponding 30 33; in addition, the outgoing

In the corresponding cycle of the runtime memory, the signals read out again also to the marker bit control stage

read and presented; in this case the 55th

Block 84 blanked. From the above erpelten signals into the runtime memory via the and

clarification and FIG. 2 is' be appreciated that the circuit 119 is caused to a repeating

Blocks 1 to 77 and 78 to KB 12 alternate 35 characters on the screen of the tube 33

the or nested order in which takes place. The temporal interaction of the and

Delay line are located and in the delay memory circuits 121 to 124 on the input side of the

rather 21 circles. The video content of these blocks 1 to delay lines and 127 to 130 on the output

77 is entered during one cycle of the runtime memory by the counter 125 accordingly

on the screen in the upper half in the hori- 40 coordinated. This counter 125 acts in its basic

zontal writing lines 1 to 77 shown (see function as a simple shift register with a

Fig. 5). In the following second cycle of the runtime counter ring. This counter ring is through on the input side

In the memory, the blocks 78 to 143 are read out, the clock pulses of the line 24 are switched on and

and in the lower half of the screen tube causes the excitation of the connected AND-switch-

placed. It is particularly mentioned that the video lines 45 in circular order so that the from

Information in the transit time memory in signals arriving in one another in the OR circuit 120

nested blocks are stored, but that the corresponding order in the delay line

the display of the video information on the lines 110 to 114 are entered. Such

Screen in continuously successive lines. Runtime memory with rewriting are the

happens which are not nested. The 50 expert already known.

the above explanations and the F i g. 2 to 8 Before writing or saving the

show the synchronous interaction of the memory, video or BCD information in the blocks

device with the image display, which book- for synchronization purposes, introductory marking

letters, numbers, special characters and other sym bits in the last bit position of each block.

bole of information. 55 places. This is bit 128 and corresponds in time to

The in the F i g. 1 construction position shown in block form 31.75 to 32 microseconds of each groups, such. B. Keyboard 10, the BCD video Um-Block, which, as already explained, 32 microswitches 12, the parallel-to-series converter 13 and the bit-seconds length corresponds, with 31.5 Mi counters 14 are known to the person skilled in the art and microseconds for the time length of the 21 bytes have already been described in other publications. 60 are required and 0.5 microseconds for the two. The transit time memory 21 can also be made up of spacing bits. Bit 128 and consequently also the known type exist, but it is advantageous to select an introductory marking bit corresponding to bit time 2 execution, as shown in FIG. 9 shown (BT 2), in which it is also set,
represents is. 9 shows in more detail the runtime. The task of these introductory marking bits is to store 21 and the marking bit control stage 55 from 65 to write information in the following FIG. 1, which is shown there in block form. To control memory block (see Fig. 2).
The transit time memory 21 ... includes on the input side the In each memory block, which video or. BCD AND circuits 116 and 117 and an inverter containing information are sent at bit time 6 (BT 6)

15 16

Marking bits set. In addition, each AND circuit 119 is blocked, thereby preventing the re-horizontal writing line from writing a video marking bit, the marking bits being set to the runtime at bit time 6, in the last byte of the block, in memory 21 .

which video signals were written. The AND circuits 131 to 133 of the marking bit writing of the video information in the next control stage 55 are connected on the input side to the adjacent block of the delay time memory 29 following the selection line; on this dial-up line there is a powerden of the already set marking bits in front of the sensitive level whenever a key on the keyboard 10 destroys the writing of the information, and a signal as shown in FIG. 1 is actuated, otherwise a new video marking bit is set, immediately negative level on the selection line 29 and at the input after the end of the write operation at bit time 6. All OK of the AND circuits. The actuation of a key in the information written into the transit time memory 21 has the effect that the positive level on the dialing line 29 is optionally recorded in bytes of 6 bits each remains positive until the keyed character divides or in bytes with 12 bits, whereby the 6th or as video or BCD information in the runtime 12. Bit position for the marking bits is reserved, memory 21 is written, ie at least as which appear at bit time 6. Because the Markie takes a long time until two full memory cycles have expired. The AND circuits 131 and 132 received are positive written, the 6th or 12th bit position remains tive pulses at bit time 6 (BT 6) via the input preceding bytes unoccupied and dark; This transmission line 62. Signal level which gives the electrons and controls the distance between two adjacent line-beam resetting in the vertical direction, which are displayed on the screen. 20 reach the AND circuit via line 32 Whenever characters appear on the screen, 131, these signals also act on the AND circuits 132 and 155 via the In-generated marking bits to the right of the character verier 136. Cursor). This display index is during the vertical return of the beam which is of help to the operator in that it indicates negative on line 32 and prevents the output from which position the next character appears. This setting up of the AND circuit 131 positive at this point in time is useful in so far as it is on. The line 32 is positive during the time in which there would be deliberate spaces or blanks keyed in which characters were on the screen of the tube 33 . being represented. This positive signal is in the

The foregoing means that each block is converted in accordance with inverter stage 136 and is the negative of FIG. 2 is controlled only by a marker bit to a 30 signal at the input of the AND circuit 132 and determined given time. The initiation thus prevents their excitation, so that their marking bit, arranged in the last bit-positive output, is also negative at this time. On the line tion of the previous block, it is erased before 63 alternately positive and negative Si video or BCD information appear Seconds. During the time in which the signals or the last byte of a given block are bit positive, no display of character position 6 is saved. on the screen and the marking bits can

In explaining the FIG. 2 it was not pointed out by the AND circuits 131 and 132 that the blocks KB 1 to KB 12 are known because the inverter 137 supplies negative signals storing binary or binary coded decimal 40, which these AND circuits at this time information (BCD) can be used. Lock in these. However, if the signals on line 63 are blocks, the BCD information is in bytes with negative, then the video is stored every 12 bits, and the marker bit becomes signals and a screen display, the time in the block in FIG However, except for the bit position of the last byte of the vertical beam return, it is set and is written in at bit time 6. A 45 Positive signals reach the memory block via the inverter 137 and can encompass a maximum of 10 BCD bytes around the AND circuits 131 and 132 , and each byte consists of 12 bits. in a state that they erase the marker bits

The marker bit control stage 55 in FIG. 9 met. A positive two functions come via line 64. First, it clears the old Markie pulse on the AND circuit 133, during the last bits (video and BCD) before the start of a new 50th bit period of each block (see Fig. 2). This write operation and locates the BCD marking- last bit appears after the video byte 21 two bit bits during a read process. A recognized period later. Via line 65, the BCD marker bit is read in a read process, and circuit 132 sends a positive signal to all Zeidass all BCD information contained in the blocks with the exception of byte times 20 and KBl ... KBn are included, have been read out. The 55 21. At the beginning and end of the vertical beam return marker bit control stage 55 in FIG. 9 contains the lead, positive input pulses are sent to the flip-AND circuits 131 to 133, the outputs of which are applied to the flop 151 via the line 150 , and they are routed to the OR circuit 134 , the output effects of which are reset. The AND circuit 153 line is denoted by 57 and to the inverter 135 receives a positive via the line 152 each time, which leads to the AND circuit 119 in the running 60 signal when the 7th line of each row of characters is connected to the time memory. A positive output letter is generated. This AND circuit 153 receives a signal from the OR circuit 134 means that a signal has also been recognized via the write line 25 and marking bit; this causes the control signal for vertical beam return via the activation of the bit counter 14 to initiate the line 32. The output of this AND circuit of the write process and the deletion of the recognized 65 153 is via the OR circuit 154 with the input marking bits. This means that the positive side of the flip-flop 151 is connected. The AND signal on the line 57 in the inverter stage 135 to the device 155 receives signals on the input side from which a negative signal is converted, which the write line 25 and the inverted control signals

for vertical beam return from the inverter 136. The output of this AND circuit 155 is connected to the binary I input of the flip-flop 151 via the OR circuit 154 . The binary 0 output side of the flip-flop 151 is connected to the AND circuit 133 . The AND circuit 153 provides a positive output signal only during the time when video information is being displayed, and the AND circuit 155 provides a positive output signal only during the time of the vertical beam return. The outputs of the two AND circuits 153 and 155 are connected to the OR circuit 154 ; it can be seen that the OR circuit 154 sets the flip-flop 151 at a time when a character is displayed, the portion for the horizontal and vertical beam return is included in this time. Since line 64 receives a positive pulse at bit time 2, which corresponds to the end of a block, it can be seen that AND circuit 133 can only recognize lead-in marker bits for both video and BCD information. Since the line 62 only becomes positive at bit time 6 (BT 6), the AND circuits 131 and 132 can only recognize these bit marks which were automatically set when the characters were keyed in and written into the runtime memory 21 .

The line 57 from the marker bit control stage 55 to the transit time memory 21 normally has a negative signal level. This is converted into a positive signal level in the inverter 135 and applied to the AND circuit 119 . This allows all output signals to be rewritten into the transit time memory 21. If a marking bit is recognized in the marking bit control stage 55 , the level on the line 57 becomes positive and the input to the AND circuit 119 becomes negative. This signal blocks the AND circuit 119 and prevents the marking bit from being written into the runtime memory again. Of the delay lines 110 to 114, the output signals are taken periodically and pass through the OR circuit 138 and line 30 to the AND circuits 131 to 133, from there through the OR circuit 134, next to the inverter 1 35 to the AND circuit 119. At the same time, these output signals reach the AND circuit 119 directly via line 30. This circuit measure ensures that all marking bits are deleted. The space that has been taken up by these marker bits so far remains empty at first. The new information is then immediately written into the corresponding bit positions, and a new marking bit is set in the 6th bit position before the writing process is completed. If a marking bit is recognized, a positive pulse is sent via the line 57 in FIG. 9 to the bit counter 14 in FIG. 1 in order to initiate the writing of new information into the transit time memory.

In FIG. 9, a delete key 140 is shown in its normal rest position; as a result, a negative level is passed from the voltage source 141 to the inverter 142. A positive level comes from the inverter 142 to the input of the AND circuit 119, which becomes conductive and enables the information signals fed back from the output of the delay lines to be rewritten. By actuating the delete key 140 , the rewriting of the information signals is prevented because a positive level reaches the inverter 142 via the voltage source 143 , the output of which becomes negative and thereby blocks the AND circuit 119. The consequence of this is that after the end of a circulation cycle of the runtime memory, all of the information that has been written is deleted. After releasing the delete key 140 , it is possible to write new information into the runtime memory. Before new video or BCD information is written in, however, the lead-in marker bits or synchronization signals are set. It has already been mentioned earlier that the end of a writing line on the screen is identified by an introductory marking bit at the end of a block in the transit time memory 21 . These lead-in flag bits are entered by pressing key 144, which is normally open, as shown in FIG. 9 is shown. Via the line 145, the key 144, the OR circuit 120 , positive pulses with very precise timing, which correspond to the introductory marking bits, are sent to the transit time memory 21. These positive signals arriving on the line 145 are stored in the control unit 54 in the F i g. 1 generated! and appear at bit time 2 after bytes 21.

FIG. 10 shows in greater detail the control unit 54 according to FIG. 1 for the timing of the electron beam in the horizontal and vertical directions. From the block diagram of FIG. 10 it can be seen that the control pulses for the movement of the electron beam are generated in the control unit 54 essentially as a function of time. The clock generator 23 in FIG. 10 has a frequency of 4 MHz and continuously supplies pulses with a duration of 0.25 microseconds. These clock pulses arrive via a line 24 to a sub-stage bit ring counter 200, which acts like a normal 6-stage shift register and generates the bit times (BT) 1 to 6 at its output in a continuously rotating sequence. The pulses at bit time 6 from each cycle of the bit ring counter 200 reach the input of a byte ring counter 201, a counting ring with 21 levels. Pulses at bit time 2 arrive from the bit ring counter 200 via the line

202 to the AND circuit 203. This AND circuit

At byte time 21, 203 also receives a pulse from byte ring counter 201 via line 204. The output of the AND circuit 203 is connected to a bistable multivibrator 206 through the line 64 . The positive signals on the line 64 cause the flip-flop 206 to switch alternately from one stable state to the other. This switching of the bistable flip-flop 206 takes place every 32 microseconds and corresponds to the time required by the byte ring counter 201 to count 21 bytes and the bit ring counter 200 to count 2 bits. The output signals of the bistable multivibrator 206 are a series of reciprocal + pulses corresponding to the pulse representation 207. The output signals from the AND circuit 203 on the line 64 are required to reset the bit ring counter 200 and the byte ring counter 201 after 21 bytes plus 2 bits were counted. To generate the in FIG. 5 raster points shown are also supplied by the bit ring counter 200 pulses in accordance with the clock frequency. The byte ring counter 201 counts the number of bytes, which also correspond to the number of characters that can be displayed in a horizontal writing line.

19 20

The bistable flip-flop is screen device (television set) via line 215. The picture tube 33 in 206 is connected to a line counter 216 , this FIG. 1 receives over the lines 32, 60 and 61 line counter is an eight-stage counting ring, and one of the control unit 54 the control signals for the full count up to eight corresponds to the writing lines required for the formation of beam return in the horizontal and vertical of a character in the Dar- S direction. The display device according to FIG. 1 is the position of the character on the screen. The expediently a television set one of the han-F i g. 6 shows that eight horizontal writing lines are commercially available types. On such a device this will be necessary in order to display a complete character- the above-mentioned composite signal on the display. After counting eight pulses, the line 253 gives at the point entered into the device, line counter 216 at its output via the line where the output of the detector leads normally to the video line 217 a positive pulse to the input of the amplifier, it is useful , the detector character string counter 218; this is an eighteen-step cut-off beforehand, as a precautionary measure to avoid the ring counter. The full count to 18 gives sen to protect. Likewise, the controls are to be set to ensure that the maximum possible number of characters - horizontal and vertical picture sizes - which can be displayed on the screen are correspondingly pure. There may be a change that has been reached. When the character row counter 218 17 speaking potentiometer is required.
Has counted character strings, it generates at its output in the composite signal on the line output on the line 219 a positive signal, which is also 253 contained video information, this is applied to the AND circuit 230 and, if these video signals If the line counter 216 then counts 7 lines 20 to the resistor 242 and the diode 252 on the Leihat from the transit time memory 21, this also transmits a device253 via the line 152 and from there to the video-positive signal to the AND circuit 230, which is stronger . From the O-output side of the flip-flop 231 then becomes conductive and a positive (Fig. 10) arrive via the line 220 via the line 61 signals to the tive signal to the OR circuit 281 and from there resistor 241, these signals consist of negati on line 150 to the O input side of the flip-ve 25 and positive pulses, the temporal flops 151 in FIG. 9 brings. In addition, the duration of the negative pulses 768 microseconds and the positive signal of the AND circuit 230 sets the flip-flop the duration of the positive pulses 4192 microseconds 231 to the binary I status. This has the effect that the is equal to (see in this respect the binary 0 output of the flip-flop 231 , which is shown on the right in FIG. 10, becomes negative pulse shape 254). From the 0 output side and that this negative level via line 61 30 of flip-flop 260 is also applied to resistor 241 via line 60 . From the binary resistor 240 horizontal synchronization signals geren I output side of the flip-flop 231 arrives a supplies. These are positive and negative pulses, with a positive signal via line 234 and the or- with the negative pulse 10 microseconds long, circuit 233 to an inverter 221 comes from and the positive pulse lasts 54 microseconds, there as a negative level via line 32 on 35 A curve of this waveform 261 is also shown in AND circuit 31 in FIG. 1, which is shown in FIG. 10 (top right),
blocks and the flow of video signals to the image The signals for setting the lead-in marker screen tube 33 interrupts. In addition, a bit gets into the blocks of the transit time memory 21 , a positive signal from the flip-flop 231 via the line from the AND circuit 262 in FIG. 10 via 234 to AND circuit 235, this becomes conductive 40 line 145 to button 144 in FIG. 9 delivered. This and allows via the line 24 clock pulses has already registered these signals arrive earlier erauf the vertical feedback counter 236th To purify. These marking pulses are positive and if a delay time of 768 microseconds is generated for each block (see Fig. 2) or received for each, this counter must count 3072 clock pulses (see Fig. 6), with the exception of the len. The vertical feedback counter 236 is thus an eighth line of writing of each character, and it is an abnormal counter and not a counting ring. A positive seem at the last bit time of each writing line. Or output pulse is given more specifically by the vertical feedback counter, line counter 216 in FIG. 10 supplies 236 via line 237 to the binary 0 input a positive signal level via line 263 to flip-flop 231 , and this causes And -Circuit 262 at all times except for its reset. This ultimately has the consequence that 50 of the time in which the 8th line is written. A positive signal arises on the line 32 and it has already been mentioned that the 8th line of writing remains dark after the end of the vertical beam return and thereby the AND circuit 31 opens the distance between two verrung and thus represents a vertical symbol. The AND circuit 203 new image write cycle for displaying video also supplies a positive signal via the information line. By positive 55 64 to AND circuit 262 during the last bit output of vertical feedback counter 236 period of each write line. The marking bit in is further transmitted via line 237 and the OR switch to a block as shown in FIG. 2 is recognized and for device 281 and the line 150 of the flip-flop 151 in synchronization purposes of the following block by F i g. 9 reset, i.e. after the end of the verti- required. An initiation mark bit set at the end of the return of the electron beam. 60 of a 32 microsecond block in Fig. 8a

The arrangement (according to FIG. 10 on the right) also includes three resistors 240 to 242 at the beginning of the subsequent 32-micro, to these are the seconds blocks, this is illustrated by the three diodes 250 to 252 connected, which synchronize or synchronize pulses 81 and 82 in FIG. 8 b. if connected to line 253 . The bit ring counter 200 delivers at bit time 2 via zontal and vertical synchronization signals and the 65 line 270 a positive signal for the AND-switch video signals are combined with one another and result in 271 (FIG. 10). Likewise, the byte ring length provides a composite signal via the counter 201 at the character or byte time 7 a positive line 253 to a video amplifier of the image signal via the line 273 to the AND circuit 271.

21 22

This becomes conductive and causes a positive set signal that the BCD-video converter 12 sends the viauf to the binary I input of the flip-flop 260. Data information for writing in the running time becomes the I output of the flip-flop 260 positive, memory 21 supplies. The positive pulse on the line and this level is transmitted via line 272 to device 57 in FIG. 1 to initiate a write operation AND circuit 276 , as a result of which the and 5ion becomes conductive through the AND circuit 133 in the Mar circuit 276 and enables the through bit control stage 55 to be generated (see FIG. 9). . The input of clock pulses arriving on the line gears of this AND circuit are described in more detail below 24 to the horizontal feedback counter 274. This is a described.

Ring counter with 40 levels. After this horizon- The election line 29 in FIG. 9 is positive, tale return counter 270 has received 40 pulses, io whenever a key on keyboard 10 is pressed, it gives a positive output signal on the line from the transit time memory 21 via line 30 275 and causes the resetting of the flip-flop 260 synchronization signals according to the introductory marin the binary O status. This has the consequence that the marking bits for the AND circuit 133 at byte time 21, line 272 becomes negative and the AND circuit 276 and bit time 2 are supplied, and in FIG Feed of 15 shown before the first write operation. This prevents clock pulses. The resetting of the flip initiation marking bit or the synchronization signals flop 260 also causes the line 60 to be cleared for each block, whenever a signal becomes positive and this potential is passed to the resistor 240 Information in the associated block of the run time. The horizontal sync signals which memory is written to. It is assumed that the flip-flop 260 generates and the resistor 20 that no write operation has yet taken place and that 240 is present, positive and negative have already generated the introductory marking bits and in level, the negative pulse has a length from each block of the runtime memory 21 have been set. 10 microseconds and the positive impulse one. The writing now takes place in such a way that from a duration of 54 microseconds. A corresponding run-time memory 21 positive signals of the lead-Mar-curve 261 is shown in FIG. 10 above ones shown, kierungs 25 bits and represents the right-circuit via the line 30 to the. These horizontal synchronizing signals are 133 received . Through each block in the transit time memory with the vertical synchronization signals and the Vi, the line 64 deosignalen is combined at byte time 21 and bit time 2 and arrive, as already shown in FIG. 9 assigned a positive pulse. This was mentioned, via the line 253 to the video positive impulse is stronger with each block of the transit time in the screen device. 30 memory 21 is generated, regardless of whether a writing has taken place or not. The line 63 in FIG. 9 is described in more detail for the display of characters on the screen of a tube 33 occupied with a sequence of positive pulses. After switching the operating voltages on, each with a duration of 32 microseconds, the button 140 will have the. If this line 63 is positive, then one in FIG. 9 is actuated. This causes a deletion of the display on the screen of the tube 33 under signals which may still be stored in the transit time by blanking. In this connection 21 in the delay lines 1 to 4, it is pointed out that the positive signals are the. Then the key 144 is in the on line 63 in FIG. 10 by the OR-F i g. 9 is actuated, and initiation marking bits or circuit 233 passes to the inverter 221 , which synchronization signals are set in the transit time memory 21 40 a negative signal via the line 32 to the and every 32 microseconds. These signals identify circuit 31 in FIG. 1 delivers. The control signal draws the blocks in the run-time memory (see on line 63 in FIG. 9 to ensure that the in-fi g each block, which is the byte time 21 and blocks during the first round trip cycle of the run is the bit time 2 of each block. If then the 45 time memory 21 takes place and that the remaining first character key of the keyboard 10 is pressed, and intermediate blocks during the binary signals arrive in parallel over the following cycle of the time memory bed the cable 11 to the two converters, the BCD is written . The flip-flop 151 is switched to its 0 status 13 in FIG. 1 by a video converter 12 and the parallel-to-series converter positive signal on the line 150. It has already been mentioned that 50 is reset. This has the effect that, when a key is pressed, the selection line 29, a positive signal on the AND circuit 133 becomes positive from its 0-off and ultimately causes the electric to be given. On the line 150 positive nenstrahl get in the vertical direction to its output signals at the beginning and end of a vertical position is returned. The election line 29 is beam return.

thus positive at the beginning of block 66 in FIG. 55. These positive signals arise in FIG. 2 when a key is pressed. The video signals beam return and in the vertical return counter coming from the circuit 230 of FIG. 10 at the beginning of the vertical BCD video converter 12 comprise 7 bytes with 6 bits each, which are entered in the first 236 (FIG. 10) after the end of the vertical beam return. Byte position of blocks 1 to 7 according to FIG. 2 introduction. Both signals are sent via the OR switch and are saved. This video information is 60 device 281 (FIG. 10) on line 150. If all are thus represented in the first byte position of the lines at the input of AND circuit 133, positive write lines 1 to 7 (see FIG. 5 ), and the sign, tive, is produced at the output of a positive signal, represented by such video information, which appears via the OR circuit 134 in the 5-to-7 matrix in the upper left Line 57 and from there to the bit counter 14 in FIG. 1 corner of the screen (see Fig. 6). As soon as received from the 65, which initiates a write operation. The marking bit control stage 55 in FIG. 1 an introductory Mar- writing of information into the transit time storage bit is detected, the write power 25 is more positive and acts on 57 a positive pulse to the bit counter 14, which the two AND circuits 153 and 155 in the

23 24

F i g. 9 a. The writing of the information is stopped, changes on the selection line 29, which happens in such a way that the first video byte in block 1 signal level changes from positive to negative. This has to be put in the first byte position, and the second consequence that the AND circuits 131 to 133 block up to the seventh video byte is also in the first byte and that thereby the recognition of the marking position of the blocks 2 up to 7 are written in (see 5 bits are suppressed until another key, Fig. 2). Before writing the video informa- is pressed. After entering the first character in a block, the block that was at the end of the previous block is shown repetitively on the screen of the tube at byte time 21 and bit time 2 in every image cycle,
set introductory marking bit at the same time after keying in a second character or the AND circuit 133 recognized, e.g. B. also the blocks io of further information by means of the keyboard takes place 78 to 84. This has the consequence that the write operation, the writing of the video or BCD information tion for the blocks 2 to 7 is initiated before the same As already described above, the respective lead-in marker bit is cleared. This has been done, with the exception that the marker write operation causes a new marker bit, which was saved at bit time 6 of the last video or bit at bit time 6 (BT 6) in each video byte of the 15th BCD bytes appear, blocks described by the AND circuits being stored. These fronts 131 and 132 can be recognized in FIG. The process is repeated: when the video circuit 131 is written in, it recognizes the video marking bits, information in the individual blocks. Before the input which at bit time 6 in the last video byte of a write of the block 64 will appear. The introductory mark block will appear, and the AND circuit 132 errungs-Bit recognized in block 141, and before the input 20 knows the marking bits in the last byte of the BCD writing of block 4, the introductory marking blocks are also at bit time 6. The video marking bits are recognized in block 81 and after the introduction ^: bits are recognized by the and -Circuit 131 only erased the write-in process, etc. "recognized when their input lines 29, 30, 32, 62 The BCD information is in the corresponding and the output from the inverter 137 at the same time positive KB designated blocks of the runtime memory 25. The and- Circuit 132 recognizes BCD-Marein written (see Fig. 2). The actuation of the first marking bits, if at the same time positive signals on the character key, causes this BCD information in their input lines 29, 30, 62, 65 and the Verden first block with the designation KB 1 feed lines to the inverters 136 and 137 are leaked. The BCD bytes comprise 12 bits, each gen. The positive output pulses of the And-Schalzwei BCD bytes 1 and 2 are in a .KB block 30 lines 131 and 132 that old video Mardes runtime memory 21 is written. Each BCD marking bit, which is still in the runtime memory byte, has a marker in its bit position 12, and the introduction of an information bit, this appears at bit time 6. All new write operations begin. If characters are typed in one after the other at the byte time 21 keyboard, then bit time 2 of block 66 becomes positive (see 35 these successively as video and BDC Fig. 2). . From the output of the AND circuit 133, a positive signal enters the runtime memory 21 via the OR circuit 134 and the line 57 is again placed on the screen as a character for the purpose of initiating a BCD, also in a running sequence, starting with the write operation in the position of the first and two bytes of the block KBl at the top of the first row of characters from left to right. The introduction of the BCD-4 ° (see Fig. 6). If 21 characters are typed in, the write operation causes the write line 25 to be stored and displayed, the 1st character is positive and thus the input of the And row is also fully written, and the next 22nd character circuit 155. While the vertical beam is behind In the first character position of the second character guide, the output of the inverter 136 is also series according to FIG. 6. The video information for this is positive. This positive level is also at the input 45 22nd character is in the first byte position the output of the AND circuit 155, of whose output blocks 9 to 15 are stored (see Fig. 2). In the case of a positive signal via the OR circuit 154 for keying further characters, these are then entered into the input of the flip-flop 151 and bring it into the set position from left to right in the second row of characters. As a result, the bi- is shown. It should be noted that the secondary 0 output of the flip-flop 151 becomes negative and 5 ° blocks KB 1 to KB 12 do not have the same information as a result of the AND circuit 133 being blocked. The amount of data can be stored in BCD bytes, as a result of which further BCD information is written into the video bytes of blocks 1 to 143, which data in the runtime memory contain the video information during this. It can be prevented with cycle (see Fig. 9). With a video keyboard up to 120 characters are entered, the write operation, the output of the AND switch 55 which is then shown as video and BCD signals in the course of 153 is positive when the introductory marking bit is written in time memory and on the screen is recognized in the 7th writing line, the line 152 of the tube 33 can be displayed as a character. The rest is also positive at this time. The positive loan storage capacity of the runtime memory is filled with the output signal of the AND circuit 153 comes via the video information which is sent from other, OR circuit 154 to the input of the flip-flop 60, not shown, e.g. B. from data-151, which is set. This will deliver its processing systems. The BCD-O output negative. This potential blocks the AND information, which is stored in blocks KB1 to KB 12 circuit 133, thereby further writing, can be read out in time, ben of video information in this cycle in which the electron beam in vertical Direction of the runtime memory prevented. After 65 is reset by loading. This BCD information can be activated on the keyboard, the input of the information is also in data processing systems or is finished and this is further processed in coded form as video devices,
and BCD information in the runtime memory. From the previous description it can be seen

that an arrangement for displaying fonts and other characters on the screen of a television tube 33 was created, with the video information for each writing line of an image display is written in blocks of a run-time memory and that the blocks of this run-time memory are nested. The video signals that make up the characters in the upper part of the screen always come into effect in the first cycle of the runtime memory, and the video signals for the The characters displayed in the lower part of the screen tube are then displayed in the second Runtime memory cycle read out. When displaying the video signals is in horizontal Direction the dark time is equal to the duration of the light key time. These times are equal to the running time of a Block in the runtime memory (see FIGS. 8A and 8B). Therefore, while a block z. B. the first Block row is read out and displayed, the

neighboring blocks of the other block row in this cycle are not read out because they have been blanked are.

Video information that is not displayed in the first cycle of the runtime memory is located in the blanked part of the horizontal writing cycle of the electron beam and appear as visible Characters in the lower part of the screen when the second cycle of the runtime memory is running. It is

ίο thus a maximum utilization of the available Storage capacity of the runtime memory given, since all information written into the runtime memory in the first or second cycle or pass on the screen, with the exception of half the area which is provided for the vertical return of the electron beam. This area is used to store data entered through the keyboard in the form of binary digital signals.

For this purpose 2 sheets of drawings

Claims (17)

Patent claims: 1. Arrangement for displaying information on the screen of a cathode ray tube in the manner of television reproduction in a repeating image cycle through a line-by-line scanning beam deflection with a transit time memory in which the information is stored as video signals and in another coded form (BCD signals), controlled by synchronizing signals, can be written in and read out cyclically repetitive in blocks, the number of blocks corresponding to at least the number of write lines and in which the video signals of a block are read out in a beam-line cycle, characterized in that two revolutions of the transit time memory (21) are made in one image cycle. , which contains the blocks (1 to 143, KB 1 to KB 12) in two nested rows, are assigned that in the first cycle one after the other a blanking of the blocks of the second row and a bright keying of the blocks of the first row as well as the display of their video signals one half of the screen succeeded lgt and that in the second cycle, at the end of which the beam is returned to the starting position, the blocks in the first row are blanked and the blocks in the second row are blanked and their video signals are displayed on the other half of the screen. 2. Arrangement according to claim 1, characterized in that in a horizontal deflection cycle for the recording of a line by the electron beam, whose light-scanning time is the same the blanking time and that these times are each identical to the time length of a block so that two block times correspond to one beam line cycle (FIG. 8 A). 3. Arrangement according to one of claims 1 and 2, characterized in that with a horizontal beam deflection cycle in addition to the blanked beam return and the beam advance at the beginning and end each have a short blanked area that these blanked areas are two blocks of the row of blocks not read out in this circulation cycle are assigned that one of these blocks is arranged immediately in front of and behind a block to be read in the other row of blocks and that synchronization signals (H ₁ , 81, 82) provided at the end of each block control the area scanning (FIG. 8 B). 4. Arrangement according to one of claims 1 to 3, characterized in that there is an area in the transit time memory, the length of which is equal to the vertical beam reset time after the end of an image cycle, that in this area in the first row of blocks (66 to 77) video signals and in the second, interleaved block row (KBl to KB12) binary coded signals (BCD) are contained, the latter corresponding to the keyed in information characters, and that a readout of these binary coded signals (KB) at the end of the second cycle during the vertical beam reset time and their transmission to other data processing systems. 5. Arrangement according to one of claims 1 to 4, characterized in that the transit time memory contains an odd number of blocks. 6. Arrangement according to one of claims 1 to 3, characterized in that each .Informationszeichen to be represented consists of a number of grid points corresponding to the video signals, which on the screen of the tube (33) is assigned a fixed place that this grid also is contained in the transit time memory that a write line corresponds to a block read out and a block is divided into a number of bytes, one byte corresponding to a character width, that a byte is divided into a number of bits that correspond to the raster points, that the last bit position in a Byte forms the distance between two adjacent characters on the screen and that on the screen the characters are formed in the vertical direction by several lines, the last of these lines being blanked by a signal from a line counter (216) and serving as the vertical distance between two rows of characters . 7. Arrangement according to one of the preceding claims 1 to 6, characterized in that the lines are written consecutively from top to bottom and that in the first circulation cycle the upper half and the lower half in the second cycle of the runtime memory of the screen. 8. Arrangement according to one of claims 1 and 7, characterized in that for the first at the display space (T ₁₁ , T _{1 6} to T ₇₁ , T _{7 e} ) to be displayed information characters, the video signals in each case in the first bytes of blocks 1 to η of first row of blocks are stored, where η is the number of writing lines for the character height (Fig. 5). 9. Arrangement according to one of claims 1 to 7, characterized in that the transit time memory is completely filled with nested blocks of the first and second row, that the end of each block by introductory marking bits set before the information is stored is set, which control the storage process and which are used as synchronization signals in the Serve character representation. 10. Arrangement according to one of claims 1, 3 or 6, characterized in that when the information is stored in each byte of a block in the last bit position, a marking bit identifying the end of the information character (BT 6) is set and that when the next is displayed This marking bit is deleted when the character is displayed on the screen. 11. Arrangement according to one of the preceding claims, characterized in that it contains a keyboard (10) for entering information characters, which is connected on the output side to a video converter (12) and to a BCD converter (13), the output signals of which of a clock (23) and a bit counter (14) controlled logic gate circuits (116, 117, 120) which are connected to the input of the transit time memory (21) that the 3 4 Keyboard when pressed, a signal for an AND (10) entered and generated in the runtime memory as a circuit (19) through which these the repe video signal and are stored as a BCD signal, animal rewriting of memory signals and that the remaining 258 from another interrupts and the aforementioned gate circuits input device originating characters only as for rewriting, and that between 5 video signals are contained in the transit time memory, the input of this AND circuit and the output (138) of the transit time memory a marker bit control stage recognizing the marker bits (BT6) (55) is arranged. 12. Arrangement according to one of claims 1, io 3, 4, 5 or 9 to 11, characterized in that
that the bit mark control stage (55) the introductory mark bits in an AND circuit (133) and the marking bits (BT 6) of the last bit. This invention relates to an arrangement for displaying a byte in two AND circuits (131, 15 position of information on the screen of a 132) recognizes and that it recognizes the storage of new cathode ray tubes according to Art the television re-information in video and binary coded would be in a repeating picture cycle, by a signal form as well as the repetitive writing line by line rasterized beam deflection with one of the video runtime memory read from the runtime memory, in which the information as video and binary encoded signals and the deletion 20 signals and in another coded form (BCD), from 5.T. 6 signals. controls through synchronization signals, cyclically repetitive 13. Arrangement according to one of claims 1 rend in blocks can be written and read, wherein and 11, characterized in that the run- the number of blocks at least the number of time memory (21) from several parallel-wired write lines and in which the readout ten delay lines (110 to 114) consists of 25 of the video signals of a block in a beam and that this is done by a frequency divider line cycle. (125) in cyclic order when storing. This invention aims at a very important one and readout can be controlled. Improvement of an already in the German patent 14. Arrangement according to one of claims 1 registration P 15 24 436.7-53 (German Auslegebis 5 or 9 to 12, characterized in that 30 script 1524 436) proposed cathode ray for Formation of the temporal block lengths from the display device or a display device Clock (23) fed bit ring counter (200) and for information display to the extent that by a a byte counter (201) is provided which, with little additional effort, the amount of information line direction consecutive bits and characters in the runtime memory and in the screen bytes count and the last predetermined 35 representation is considerably enlarged, whereby Bit of a line via an AND circuit (203) a larger character capacity of the display device emit a signal from which the Enileit marking results. Information bits are derived, and one such display devices are preferred stable flip-flop (206) tips over, its output as peripheral devices for input and output of information output signals the temporal block length and the brightness 40 used in data processing systems, Form dark tactile impulses. where the information to be entered is usually by means of 15. Arrangement according to one of claims 1, keyed in a keyboard, stored and on the 4, 8 and 10, characterized in that the device is displayed on the screen. It is there Vertical offset of the writing lines one line possible, any necessary corrections counter (216) and a character row counter 45 to make. The one shown on the screen (218) it is provided that the line counter for information is then either on the one in the vicinity instalein all the lines used to form characters or at a greater distance Signal emits and no signal transmitted in the last, lierte data processing system, and the distance between two rows of characters is then shown on the end of the picture Empty line, and that the line row counter is displayed on the screen. There are already a number of different devices together with the character counter AND circuit (230) at the end of the last line for displaying fonts and other characters generates a signal that guides the vertical beam return on the screen of a cathode ray tube and reading out the binary coded. These screen devices are for visual information triggers in the runtime memory. 55 display of information the lines to be displayed 16. Arrangement according to one of claims 1, either fixed in masks or in a memory 11, characterized in that the representation of characters contained in the character form to be displayed is related to the character matrix a commercially available television set. The stored character can be used in memory is and that its video amplifier is divided into elements, which coordinates and analog the video signals as well as the horizontal and deflection voltages are assigned to the electrical synchronizing signals (261 and 254) via nenstrahl for character display accordingly Line (253) are supplied. to steer. 17. Arrangement according to one of the preceding In the USA. Patent 2 866 177 is a Com-Claims, characterized in that described on the computer readout system in which the dardem Screen of the television tube (33) in steadily 65 delivering information characters on the screen repeating image cycle in 18 character rows from individually light-keyed segments are formed, (each with 21 characters) 378 characters can be displayed, the electrical values of which are determined by two segment discs, with up to 120 characters through a keyboard rotating with a drum memory, via a