DE1544310C3 - Process for diffusing dopants into compound semiconductor bodies - Google Patents

Description

1 2

The invention relates to a method for diffusion. Another advantage of the diffusion according to the invention of dopants in connection halfway consists in the fact that through the silicon conductor body, the surface of the semiconductor oxide layer not just the surface concentration body covered by a silicon oxide layer of the dopants, but also the diffusion and an atmospheric profile containing the dopants in the semiconductor body can be better controlled. Sphere is suspended. Furthermore, the diffusion process can not only be seen in

Such a method is already known in a closed system, but for example (German Auslegeschrift 1 086 512), in which also carry out in a one-sided open pipe, the surface of a silicon crystal during the The method according to the invention is therefore suitable Diffusion process protected by a silicon oxide layer especially for the diffusion of doping will. In the known method, the fabrics are applied to selected areas of the surface thin silicon oxide layer before the diffusion process, particularly temperature-sensitive III-V connection to apply the silicon wafer or one leaves training semiconductors, in particular of gallium arsenide. they grow during the diffusion process. This in contrast to the previously mentioned Oxide layer serves as a barrier for all impurities 15 process in which the oxide layer in one with the exception of gallium, which is deliberately an oxidizing atmosphere from the material of the penetrates the oxide layer and produces the semiconductor body itself in the surface, can be a top Silicon plate diffused. One type of surface oxide layer in a compound semiconductor Manufacture of the silicon oxide layer in the case of the known does not produce it in this way, because one of its com processes is that one sublimates the silicon plate 20 components faster than the other and deschen into an oxidizing one. Brings atmosphere in which half the surface of the crystal is unusable then the oxide layer would become from the top layers of the. It is therefore particularly recommended Plate arises by itself. the silicon oxide layer on the semiconductor body. It is also known that compound semiconductors, spray and the spray time as a function of in particular semiconducting substances made of compound to the desired thickness of the silicon oxide layer fertilizing a Group III element with a control; An elek element has proven to be particularly useful of Group V of the Periodic Table proved to be a static spray method in which (so-called III-V compounds) have the property of using a silicon cathode and in an acidic manner that at least one component is geirbeitet in those atmospheres containing substances. Temperatures at which the dopants in the 30 Further Features and Details of the Invention Semiconductors are diffused in, is highly volatile; result from the following description, the this applies in particular to gallium arsenide, indium - serves to explain the drawing; it shows arsenide and lead telluride too. The surface areas F i g. 1 schematically a device for Hereines Such a semiconductor body are so during the position of a silicon oxide layer on a connection Diffusion process destroyed. 35 semiconductors,

Finally, it has already been proposed FIG. 2 schematically a; Device for electrical

(German Auslegeschrift 1 277 827), see to avoid spraying a silicon oxide layer on one

such undesirable changes in the upper compound semiconductor that is thick enough to

surface areas of compound semiconductor bodies which close the semiconductor surface during diffusion

protect the entire semiconductor surface with a coherent 40,

to cover the evenly distributed silicon oxide layer. F i g. 3 a partially with a silicon oxide protection

The invention is now concerned with such a layer overde: ktes semiconductor wafer that one for

compound semiconductors, and it is her task to diffuse a dopant into the semiconductor

reasons, the impoverishment of the suitable atmosphere was exposed during the diffusion process,

Compound semiconductor on one of its components 45 F i g. 4 schematically a section through a front

to prevent due to the high temperatures, finishing with a closed pipe for implementation

however, to enable selective doping at the same time. the diffusion process,

On the basis of a method of FIG. 5 schematically a device with open:

mentioned type, this object is according to the invention for the diffusion of dopants through a tube

solved in that for diffusing the doping 50 silicon oxide layer through into a connection

substances only in selected areas of the upper semiconductors,

surface of the semiconductor body a silicon oxide layer Fig. 6, 7, 8, 9 typical diffusion curves for a

different thickness is applied, which is via compound semiconductors with and without silicon oxide

the selected areas are so thin that they have a protective layer,

the dopants during the diffusion through 55 Fig. 10 schematically the diffusion for a plane

is penetrated, and over the other places the p-n junction using a silicon oxide

The surface of the semiconductor body is so thick that layer with different thickness ranges,

no dopants can diffuse through. 'In Fig. 1 is a schematic representation of a device

Even in its thin places, the SiIi- prevents. represents, by means of which a silicon oxide layer on a:

ziumoxidschicht an evaporation of one of the composite 60 compound semiconductor substrate is produced

components of the compound semiconductor. As opposed to can. In the case of the vapor flow method shown

the known method is used in the invention in each case by a deposition tube 2 from a single-zone furnace.

but the oxide layer is not considered to be a selective filter. The tube 2 can be made of quartz or other

correct dopants, but it should exist in its suitable metarial. In the tube 2 be

thin areas of all existing doping 65 there is a boat or a support 3, which you

Let substances through while it holds a semiconductor substrate 4 at all points, which with silicon oxk

Destruction of the surface of the semiconductor body is to be coated. At one end of the tube 2 is

due to the high temperatures. a suction cap 6 attached, consumed by the

3 4

Reagents and their products are discharged (shown) chamber attached, which can be a controller. At the other end of the pipe 2 is the ambient conditions permitted
an inlet part 7. In a container 8 there is a typical working condition for electrical liquid 9, e.g. B. tetraethoxysilane or any spray of a silicon dioxide layer with a thickness of other suitable organic oxysilane. A controllable amount of a carrier gas is achieved under the following conditions 9 through a 5 of about 1000 ÄE per hour on a compound semi-carrier gas inlet 10 below the surface of the liquid conductor plate: as an environment for the spraying process, e.g. oxygen, is introduced into the container 8 and if a gas pressure of 60μ oxygen is maintained, the liquid 9 is carried along with it. Hold on to the outlet pipe 11. The silicon cathode 50 is a highly crystalline are an inlet tube 12 for supplying oxygen io slice of about. 10 cm diameter with a valve 13 for the dilution of the carrier gas and an inlet specific resistance of less than 0.01 ohm-cm for supplying pure nitrogen or one (doped with arsenic). The distance between the upper other inert gases connected to the system. ■ area of the silicon cathode and the underside of the

The device for the vapor flow deposition of the sample holder is approximately 3.2 cm.
Silicon oxide according to FIG. 1 works like this: Liquid 15 In .F ig. 3 is a schematic of a compound semi-tetraethoxysilane is shown under normal space conductor plates 80 that maintain silicon oxide conditions. Layer 81 passes through the carrier inlet 10, which by electrical spraying of oxygen at a flow rate of silicon dioxide or by means of other methods 14.15 1 / hour. (under normal conditions), it tears in the process and only part of the plate 80 is covered with tetraethoxysilane and goes into the outlet pipe 11.20. If a dopant is allowed to diffuse into the platelet, an oxygen dilution is allowed to diffuse into it, under 28.3 1 oxygen per hour (in the normal area of the platelet that is not protected by the protective gaps) Pipe 11 is covered by the inlet pipe 12 layer 81, a non-uniform diffusion retention. The nitrogen flow is switched off (during the transition 82, while initial heating under the protective layer 81) and therefore the reagents formed in the gaseous plane diffusion transition 83 are introduced into the quartz tube 2. Before will. From this it can be seen that the silicon oxide is a boat 3 made of quartz with the platelets 4 layer 81 during the diffusion, the surface of the compound semiconductor material, which protects the coated semiconductor and the development of a non-uniform, is brought into the reaction zone, in which the moderately formed diffusion transition is prevented. they are then exposed to the reaction stream. 3 ° of the through loss of the volatile component from a reaction temperature of 603 ⁰ C main- surface of the compound semiconductor condition caused, so per hour 2300 AEE be Siliziümoxid is.

formed on the platelets. The consumed gas flow in the following is the diffusion of dopants

is discharged via the suction cap 6. into a compound semiconductor die in an open one

In Fig. 2 is a preferred embodiment 35 and in a closed tube on the basis of the in the for a device for depositing silicon F i g. 4 and 5 described the devices illustrated by electrical spraying (cathode disintegration and the characteristics of the diffused doping dust) onto a compound semiconductor wafer with reference to FIGS. 6 to 9 shown,
placed. The device contains a silicon cathode. The device for diffusion with closed 50 with a projection 51. The cathode is on a 40 or sealed tube according to FIG. 4 consists of an insulating support 52 mounted in such a way that the quartz ampoule or a tube 109 with a ver projection 51 into an opening in the insulating constriction 102. At 103, after the half-support 52 has been inserted, it engages. The insulating substrate 52, the small conductor plate 104 with the silicon oxide layer 105, is held in a solid position against the material 106 containing foreign matter by means of any suitable device. Melted just above the cathode 50 45. The tube 100 has a break-off is a sample holder 53, which is at its lower end tip 107, which is attached to an evacuation system side, a series of clamps 54 for holding a for reducing the pressure in the tube 103 on a support 55 made of a compound semiconductor material 10 ~ ^e Torr connected. Thereafter, the tube 103 is shown. The sample holder 53 is closed in a circular shape. In this state, the tube 103 plate, which is attached to a rotatable shaft 56, can be inserted into a furnace in order to remove the dopants, which in turn are stored in the housing 57 and supported from the material 105 in the plate 104. The shaft 56 carries a gear 58, which diffuse with it. Each common chain drive (not shown) is attacked by the furnace uniformly at the desired diffusion temperature in which it can be brought. The housing 57 is maintained by means of the entire pipe 100. The silicon oxide of the support arm 59 attached to a 55 (not shown) layer 105 protects the surface of the die and appropriate supports so that the bond enables a uniform interdiffusion die adjustable in various solid layers such as that at 83 in FIG. 3 denoted even at distances from the cathode 50 and maintained zen diffusion temperatures, which can be trated just below the. The positive side of a high melting point of the compound semiconductor plate voltage source 61 is on the support arm 59 and on earth. 60 lie.

One on the negative side of the high voltage device for the diffusion tube with open source 61 external high voltage supply line 62 has to F i g. 5 consists of a reaction tube 120 and a clamp 63 which is fastened to the projection 51 made of quartz with a suction cap 121 and a single-silicon cathode 50. The high-voltage leakage cap 122. The diffusion area in the pipe 120 supply line 62 is shielded by a metal screen 64, which is 65 through a furnace 125 (shown schematically) and has an earth connection 66 . Since the opening defines the diffusion, which is carried out to spray part of the tube in an oxygen atmosphere, encloses 120. A furnace 126 for controlling the gas is the device preferably in a (non-pressure enclosing another part of the tube 120,

I 544 310

so that an area with controllable dopant vapor pressure is formed there. In the diffusion area of the tube 120 there is a quartz boat 123 which carries the semiconductor wafers 124 during the diffusion. A boat for dopants 127 is located in the part of the tube 120 with controlled vapor pressure and carries a dopant source 128. In order to obtain a controllable dopant vapor flow in the diffusion region of the tube 120 , an inert or forming gas atmosphere is generated. The gas source 129 is connected to a flow meter 132 via a valve 130 and a pipe 131 . The gas from the source 129 flows through the tube 133 from the flow meter 132 into the reaction tube 120.

In the F i g. 6 to 9 show the concentrations of zinc as a dopant as a function of the penetration depths in gallium arsenide ^{platelets that were exposed to diffusion at ICCO 0} C in a closed tube over various periods of time, some of which have a sprayed-on silicon oxide protective layer of 65C0 produced by the method described above Ae thickness and, others had no protective layer. In Fig. 6, curves A and B show the zinc concentrations generated by 2 and 4 hour diffusion at a zinc vapor pressure of 0.1 atm. In FIG. 7, the curves C and D respectively represent the 18-hour atm by diffusion in a zinc vapor pressure of 0.01 Zinc concentrations are generated in a covered by a Siliziumdioxidschutzschicht or in a non-protected Galliumarsenidplättchen. The curves E and F of the F i g. 8 and G and H of FIG. 9 are used to compare those generated in gallium arsenide under different diffusion conditions

ίο Zinc concentrations, with curves F and H applying to platelets not protected by silica.

In Table I are the various dates for the

Semiconductor crystals and the protective layers on them are indicated as they are during diffusion of zinc in gallium arsenide or other substances in a closed tube. With some of these examples, the compound semiconductor was not sprayed on or otherwise fabricated Protected silicon dioxide layer. The examples

ao partly correspond to curves A to H in FIG. 6 to 9. In the immediately following table II the diffusion conditions and the results achieved by the diffusion for the samples according to table I are given.

Curve material Table I. Line type Protective layer material Thickness in ÄE sample in Fig. 6 to 9 GaAs Semiconductor crystal η SiO ₂ 6500 No. A. GaAs Dopant
concentration per cm * η SiO ₂ 6500 1 B. GaAs 1 x 10 " η SiO ₂ 6500 2 C. GaAs 1 x 10 " η none 3 D. GaAs 1 · 10 » ⁷ η SiO ₂ 6500 4th E. GaAs 1 · 10 » ⁷ η none - 5 F. GaAs 1 x 10 " η SiO ₂ 6500 6th G GaAs 1 x 10 " η none - 7th H GaAs 1 x 10 " η SiO ₂ 6500 8th - GaAs 1 · 10 » ⁷ η none 9 InAs 1 x 10 " η SiO ₂ 4000 10 PbTe 1 -10 " η SiO ₂ 4500 11th - PbTe 1 x 10 " η SiO ₂ 4500 12th - - 13th -

Table II

Diffusing Zn Zinc printing
in atm diffusion time
in hours Result of the diffusion Depth of Carrier density sample Dopant Zn 0.1 2 Transitional
in μ on the surface
per cm * No. Art l7oZn ») 0.1 temperature
in ⁰ C 4th Surface image 40 3 · 10 ¹⁹ τ-Ι l7oZn ») 0.01 1000 18th no decay 54 3 · 10 » ⁹ 2 047oZn ») 0.01 1000 18th no decay 10 3 · 10 » ⁸ 3 0.17oZn>) 0.001 1000 18th no decay 47 1.5 · 10 » ⁹ 4th 0.01% Zn ») 0.001 1000 18th Decay ■ 3.5 5 · 10 » ⁷ 5 · 0.01% Zn ») 0.0001 1000 18th no decay 14th 2.5 · 10 »' 6th Zn 0.0001 1000 18th Decay 0 10 " 7th Zn 0.1 1000 18th no decay 11th 10 ¹⁸ 8th Zn 0.1 1000 18th Decay - 3 · 10 » ⁹ 9 no 1000 1 no decay - 10 Foreign matter 1000 Decay 5.1 • 11th Fe 50 mg - ■ 800 1 no decay 12th - 1 - 800 no expiry ⁸ ) . 3 _ - 13th 800 no expiry ¹ ) ³ )

Remarks:

^l ) atomic percent of zinc in a gallium zinc alloy. ·) Unprotected areas showed severe deterioration. ') A diffusion layer was obtained.

In the following Table III data are given for diffusion processes with open stirrer, with the protective layer either by silicon oxide vapor flow. Tetraethoxysilane deposit or by spraying on silicon dioxide. As the carrier gas during the diffusion in an open tube forming gas was (5 to 10 ° ₀ H ₂ in N ₂₎ 'is used with a flow rate of 5OOcm ³ min. In all the examples given, the diffusion was carried out in gallium arsenide as a compound semiconductor. As a source of foreign matter, 10 g of zinc with a free molten surface of about 10 cm ^{2 were} used to maintain a constant zinc vapor pressure in the diffusion tube. In the examples given, the diffusion was carried out for 2 hours under the various specified conditions.

Table III

1 10 " Protective layer Art Diffusion conditions ; temperature diffusion Status sample Γ 10 " thickness
inÄE SiOx * temperature I of the diffusion
; area
i in ¹ C Deep in
10 "'mm after No. n-lyp-
Dopant 10 " 500 SiO ₁ the dopant
source
in ⁰ C i 900 16 diffusion
Surfaces-
nature 1 concentration
per cm ¹ 10 " 500 SiOx 650 : 700 10 Good 2 5 · 10 ^IS 500 SiOx 700 800 52 Good 3 5 · 10 " 500 SiO _x 700 800 63.5 Good • 4 5 · 1O ^1S 500 SiOx 800 900 88.4 Good 5 5 · 10 " 500 SiOx 800 1000 80 Good 6th 5 · 10 ¹⁶ 500 SiO ₁ 800 900 80 Poorly 7th 5 · 10 ^Ιβ 500 SiO ₂ ** 900 1000 96 Good 8th 5 · 10 ^1β 1500 SiO ₂ 900 800 10 Poorly 9 5 · 10 " 1500 SiO ₂ 800 900 12th Good 10 5 · 10 ¹⁶ 1500 SiO ₂ 800 1000 28 Good 11th 5 · 10 " 1500 SiO ₂ 800 800 4th Poorly 12th 5 · 10 " 1500 SiO ₂ 900 900 8.1 Good 13th 5- 10 " 1500 SiOx 900 1000 28 Good 14th 5- 10 " 500 SiOx 900 900 40 Poorly 15th 5 · 10 " 500 SiOx 650 800 52 Good 16 5 - 10 " 500 SiOx 700 900 72. Good 17th 5 · 10 ¹⁷ 500 SiOx 700 800 56 Poorly 18th 5 · 10 ¹⁷ 500 SiOx 800 900 76 Good 19th 5 · 10 ¹⁷ 1100 SiOx 800 700 1Ό Good 20th 5 · ΙΟ ¹⁷ 1100 SiO ₁ 700 800 10 Good 21 1 - 10 " 1100 SiOx 700 900 24 Good 22nd 1 · ΙΟ ¹⁷ 1100 SiOx 700 1000 64 Good 23 1 · 10 ¹⁷ 1100 SiOx 700 900 24 Poorly 24 1 · 10 ¹⁷ 1100 SiOx 800 1000 48 Good 25th 1 · 10 ¹⁷ 1100 SiOx 800 700 10 Poorly 26th 1 · '500 SiOx 700 900 52.4 Good 27 1 · 500 800 900 40 Good 28 1 · 900 Good 1 ·

Remarks:

* The SiO. _t can be SiU ₂ or another silicon oxide. ** The SiO. Layer was sprayed on electrically (cathode sputtering). *** Due to the irregular formation of the surface, an exact measurement of the diffusion depth was not possible.

The technique for generating planar diffusions in compound semiconductors is described with reference to FIG. 10. A compound semiconductor substrate 190 is covered with a silicon oxide layer 191. e.g. B. a silicon dioxide layer generated by electrical spraying, which is so thick that diffusion through it is not possible. The layer 191 , however, has a region 192 which is so thin that diffusion can take place through it. A diffusion region 193 forms a planar transition. Other planar arrangements can also be produced by diffusion processes using different areas for the windows or openings in the silicon oxide layer for masking and for surface protection during diffusion, which must be sufficiently thin for diffusion and sufficiently thick for surface protection. Various arrangements have been made in which a silicon oxide layer with different thickness ranges was used, one thickness range covering against diffusion and another thickness range permitting diffusion, but both areas protecting the surface.

For the production of planar or other compound semiconductor arrangements produced by selective diffusion, the silicon oxide layer must be different Have thickness ranges, so that under given diffusion conditions in some areas of the semiconductor substrate a diffusion transition occurs, but not in other areas. For given diffusion velocities, the thickness of the silicon oxide layer is which does not allow diffusion and protects the surface of the compound semiconductor between about 10,000 and about 20,000 AU, while the thickness

409 609/239

the silicon oxide layer, which allows diffusion and protects the compound semiconductor, can be about 500 to 10000 Ae. The cover against Diffusion through silicon oxide layer areas is caused by the fact that the period of time it takes for diffusion the foreign matter is required through these areas. is greater than that during which the Diffusion is made. As a result, by using silicon oxide topcoats with different thickness ranges both a cover against diffusion and a formation of Diffusion regions can be achieved in compound semiconductors without their surface deteriorating.

The following are examples of gallium arsenide using, (by electrical spraying under the previously conditions described) silicon dioxide layers with different thickness ranges cited.

example 1

A gallium arsenide plate with 1 × 1 ^IT atoms of tin per cm ³ was covered with a silicon dioxide layer which was 5000 ÄE thick in the diffusion area and 25,000 ÄE thick in the area to be covered against diffusion. The diffusion was carried out (as described) in a fused ampoule using 1 atomic percent zinc in a gallium-zinc alloy as the dopant source. The diffusion at 1000 ° C. for 30 minutes formed a planar pn junction at a distance of 2 μ under the gallium arsenide surface. The 25000 ÄE thick silicon oxide layer completely covered the gallium arsenide under it from the diffusing foreign matter.

Example 11

A second GaAs platelet with 1 · 10 ^1T atoms of tin per cm ³ was provided with a silicon dioxide layer 1000 Å thick over the diffusion area and 13,000 Å thick over the area to be covered. The diffusion was carried out (as described) in a fused ampoule using 30 percent by weight manganese in a manganese-gallium alloy as a source of foreign matter. One-hour diffusion at 1000 ^: C formed a planar pn junction at a distance of 1.58 μ under the GaHium arsenide surface. The 13,000 Ali thick silicon dioxide layer completely covered the GaAs beneath it against diffusion.
The invention also represents a diffusion process that can be carried out advantageously in an open tube for various compound semiconductors. The silicon oxide protective layer provided according to the invention enables very precise control of the various diffusion processes that can be used,

ίο without the compound semiconductor and in particular its surface is damaged.

Instead of the IH-V and II-V compound semiconductors described other compound semiconductors consisting of two or more elements can also be used be treated according to the invention.

Claims (4)

Patent claims: 1. Method for diffusing in doping substances in compound semiconductor body, the surface of the semiconductor body through covered a silicon oxide layer and exposed to an atmosphere containing the dopants is characterized by that for diffusion of the dopants only into selected areas of the surface of the semiconductor body, a silicon oxide layer of different thickness is applied over the selected areas is so thin. that they are from the dopants during diffusion is penetrated, and over the other places on the surface of the semiconductor body so is thick. that no dopants can diffuse through. 2. The method according to claim 1, characterized in that that the silicon oxide layer is sprayed onto the semiconductor body and the spraying time is controlled depending on the desired thickness of the silicon oxide layer. 3. The method according to claim 2, characterized in that the silicon oxide is sprayed on electrostatically will. 4. The method according to claim 3, characterized in that a silicon cathode for spraying used and worked in an oxygen-containing atmosphere. For this purpose 2 sheets of drawings