DE1537949A1 - Circuit arrangement for the encryption and decryption of messages transmitted in pulses - Google Patents

Description

IBM Germany International Büro-Matthinen Gesellschaft mbH

Boeblingen, Jan. 23, 1968 ker-se

Applicant: International Business Machines

Corporation, Armonk, N.Y-. 10504

Official File number: New registration

Applicant's file number: Docket PR 967 50I

Circuit arrangement for encryption and decryption messages transmitted in pulses

The invention relates to a circuit arrangement for encryption and deciphering pulsed messages, in which the plaintext pulse sequence to be transmitted on the transmit side Modulo-2 addition with a key! Pulse train to an encrypted Pulse sequence is mixed and transmitted and at the receiving end this encrypted pulse train also by modulo-2 addition is mixed with the same key pulse sequence as on the transmission side to recover the original plaintext pulse sequence, the same key pulse sequences on the sending and receiving sides by key generators of the same type with variable initial conditions determined by agreement between the sending and receiving sides generated and used and the two provided

ÖD9Ö87 / Ö659

Key generators each contain at least one shift register, whose output is connected to its input.

To transmit encrypted messages, it is possible to combine one pulse sequence representing the message with another, so-called Key pulse train to mix. Such a conclusion! should be as irregular as possible. On the receiving side If a suitable encryption method is selected, the decryption can be carried out in such a way that the received, encrypted Pulse sequence is mixed again with the same key pulse sequence that was used for encryption on the transmission side.

• ■

To ensure that encrypted messages cannot be decrypted by unauthorized eavesdroppers, the Key pulse sequences given certain rules. A key pulse sequence should not be periodic or at least must be have as long a repetition period as possible. One conclusion ! The pulse train should be as irregular as possible, but it must be possible to reproduce it on the receiving end so that the receiving station the transmitted message is actually back in plain text can work out · As an example, let us specify that a plain text message to be transmitted is carried out on the sending side by means of a Modulo-2 addition mixed with a generated key pulse sequence will. The decryption on the receiving side also takes place by a modulo-2 «* addition with the same, but on the Reception side synchronously generated key pulse sequence «

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Docket PR 967 501

■. '■■■:'. . BAD cniCih'AL

"The main problem for such an encrypted transmission is now the transmission and receiving side creation» selimpulsfolgen appropriate Schltis- that the aforementioned rules as well as possible match "The German Patent 1 2JK 790 is an arrangement for the production of such a suitable pulse train to. As Schlüsselimpülsgenerator a counting chain continuously updated by pulses and at least one mixing circuit controlled by it with several inputs is used, at the output of which a reproducible key pulse program occurs depending on the state of all its inputs, characterized in that the number of links in the counting chain is equal to the number of Inputs of the mixing circuit and the outputs of the individual members of the counting chain are each connected to an input of the mixing circuit and that the individual successive members of the counting chain are coupled to one another via logic circuits in such a way that from counting step to counting lstep the switching state changes on average at least half of all the links in the counting chain and that in a manner known per se ■ the counting chain only returns to its initial state after it has passed through all possible combinations of positions «

A second possibility is given by the patent specification 1,237,366 for the generation of suitable key pulse sequences. According to her Key pulse sequences are generated by a key pulse generator, the program is determined by its initial state is characterized in that this initial state is dependent on the result of mixing a first with a second,

1537149

State information is set, the first state information both the sending and the receiving side in stored Form is present and the second status information preferably on the transmission side generated by means of a random generator and transmitted unencrypted to the receiving end.

The French patent 1 J547 J5J58 mentions a third possibility for a key pulse generator. This key pulse generator uses at least one shift register and one binary Counting element chain, the outputs of which by means of mixing devices again are fed back to the inputs of the shift register. Included the respective content of the counting element chain is mixed with the content of the shift register and the result as a key pulse sequence, used.

All key pulse generators in accordance with the stated status Technique use rather elaborate and complicated circuits.

A key pulse sequence that is at least as good can be passed through generate a key generator with a much simpler basic circuit. To specify one is the task of the present one Invention,

The object is achieved according to the invention with a Schltieselgenerator with at least one shift register, the output of which with its. Input is connected, characterized in that the output

Doccet FR 967 50! »« «87/0 * 6.« V. "

of the shift register is connected to the second input of at least one modulo-2 adder, which is connected to his / her first Input and output is / are inserted between each two successive stages of the shift register, so that each of the Shift register available via its output pulse sequence because of the passage through the modulo-2 adder (s) of a continuous, is subject to lawful change β

The further embodiment of the invention is indicated by naming the circuit arrangements of key generators, which a or use several such shift register basic circuits. In addition, there are some ways to increase the variance called the generated key pulse train.

Docket FR 967 50I

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1537349

Some embodiments of the invention are shown in the drawings and are described in more detail below. Show it ·

1 shows an encryption and decryption arrangement according to the invention,

Pig. 2a shows the schematic representation of a modulo-2 addition,

Pig. 2b shows a circuit arrangement for the execution of dfeser Modulo-2 addition,

3 shows an application of modulo-2 addition for a cipher Transmission system,

Pig. 4a, consisting of a pseudo-periodic pulse train generator from a shift register and a modulo-2 adder,

4b shows the symbolic one used in the following figures Representation of a register arrangement according to FIG. 4a,

Fig. 5a shows the schematic representation of an inventive Key generator with one register,

5b shows a modification of such a key generator according to Pig. 5a,

Fig. 5c, d two pulse trains as they are at the output of such Key generator,

6a shows a key generator according to the invention with two Registers,

Fig. 6b shows a pulse train which is generated at the output of such a key

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iMAL inspected "

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generator with two registers is delivered,

Pig. 7a a key generator according to the invention with three registers,

Pig · 7b is a pulse train that is generated at the output of such a key generator is submitted with three registers,

Pig 8a a key generator according to the invention with four registers,

Pig. 8b is a pulse train which at the output of such a key

selgenerators with 4 registers. i

1 shows the encryption principle used schematically shown «in a transmission system with encrypted message transmission is used. One comes to the sending side. Transmitting plain text message at 1. She is with key impulses, which are fed via a line 2 from a key generator Ql, combined in a modulo-2 adder Ml. the The resulting pulse train represents the encrypted message that Transmitted from the transmitting side via a channel 3 to the receiving side

I will. There, a key generator G2 identical to the key generator Gl and aynohronlaufentier leads key pulses via a line 4 zn. These key pulses on the receiving end are added modulo-2 SU to the latptilsen, which are entered into a Modub-2 adder 112 via channel 3. The resulting pulse train via a line 5, the decoded message back to plain text is ·

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Docket PR 967 501

The principle of modulo-2 addition is shown in FIGS. 2a and 2b. Yes, according to the information entered on lines 6a and 6b * Information you get the following results:

G «1 = 1

1 € Ο = 1

0 «0 = 0

1 € 1 = 0

The circled plus sign means modulo-2 addition. In the circuit arrangement according to FIG. 2b, Ja and Jb are two inverters, 8a, 8b are two ANDs and 9 are an OR circuit. 6a and 6b are the input lines and LIG is the output line for the modulo-2 linked results.

In FIG.> A, the encryption is shown on the left, in which the messages arriving in plain text via the line 11a are modulo-2-added with the pulses generated by the key generator and supplied via the line 12a; over the line Y $ &. the encrypted message expires. To the right of it, on the deciphering side, an encrypted message arriving via line 13b is also modulo-2-added with the key pulses supplied via line 12b in order to make the transmitted message available in plain text again via line lib.

Fig. Jb gives two pulse trains at the top and in the middle, one Message in plain text as well as those generated by a key generator G. Encryption impulses again »Below are the

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modulo-2-obtained pulses of the encrypted message. In

This example clearly shows that with a modulo-2 link of the top and middle row the bottom 'is won that on the other hand but from the lower and middle row duroh modulo-2 connection the upper row of the original hard text pulses results.

An example of a pseudo-periodic pulse train generator and the pulse train emitted at its output is shown in FIG. 4a. This pulse train generator consists essentially of one six-stage shift register. The delivered via line 15 Output pulses are transmitted via lines 16 and 1? to the shift register input 20 returned and also fed to the second input of the modulo-2 adder 19 via the line 18. All of them Binary values shown in this shift register are undershot

encoder

Control of a clock (not shown). The one to the right The pulse sequence shown gives the first eight binary pulses at the output of this pulse train generator which can be used for a key generator again. Knowledge of a discrete number of successive binary values output by such a key generator is necessary 4ö4t, with the help of which an encrypted message can be deciphered again to be able to.

In the following FIGS. 5 to 8 they are used as pulse train generators used register arrangements as elongated rectangles

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shown as they are designated in FIGS. 4b and 5a and 5b rait R. For the sake of simplicity, they are intended in the following text as a register.

Fig. 5a shows a key generator with such a register, R. This supplies a pulse sequence which is fed via a line 21 to a key register 22a. A test circuit 29 compares the content of this key register 22a with that of an auxiliary register 22b, which in the present example is a predetermined one Number contains 010. If the register states in the key register 22a and in the auxiliary register 2Sb are identical, the test circuit 29 outputs a Impulse "output blocked" via lines 25 and 26 from. Via the line 26 and an OR circuit 27 back to the register R a further shift is effected in this. The second input of the OR circuit 27 receives pulses from a clock H a line 28. Sin output lock switch 24 leaves the from Key register 22a pulses coming only to the output S of the considered key generator get as long as from the test circuit 29 via line 25 no. "Output blocked" impulse given will. The key pulses appearing at the output S of the key generator under consideration are included in the Mod.ulo-2 adder ^ O added to the message pulses to be encrypted and so as Transmit encrypted message.

This cipher arrangement with the pulse train coming from the register R. made possible with any eavesdropping deciphering device

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due to the lack of knowledge of the initial conditions of the sending

"Side inferences! Generator hardly deciphered.

By means of the clock pulses emanating from the OR circuit 27 both those in register R and those in key register 22a contained binary values. Every pulse on one of the two inputs of the OR circuit 2? shifts the binary values in the registers one place further. However, it should be noted that that during a pulse from the test circuit 29 the curfew holder 24 is blocked and no pulse from line 23 over the Output S can reach the modulo-2 adder 30. The one arriving there Key pulse train contains the original key pulse train therefore only to one «! Part.

5b shows further details of a key generator with only one register R. The test circuit here consists of a key register Jl, an inverter 32 and an AND circuit 33. The selected key word is "lO ^tt * Whenever this key word is currently in Register 31 stands, a 'signal appears on line 34 and on line 36 · This fulfills the AND circuit 33 * in turn emits a pulse via an inverter 37, thus blocking an AND circuit 38 and, on the other hand, emits a pulse to an OR circuit 39. A two-digit counter 40 is at ^tt ll "in the idle state. An AND circuit 41 is thus fulfilled and sends a signal to an inverter 42 and thus no signal via a line 43 to a subsequent AND circuit 44. This AND circuit

Docket PR ₉ 6r 501 909887/0659

INSPECTED

device 44 is thus blocked for a clock pulse coming from the clock generator H via a line. When the counter 40 receives a clock pulse, it goes to "00" and thus blocks the AND circuit. No signal at the input of the inverter 42 causes a signal at its output via the line 4j5 to the AND circuit 44. Thus, the AND circuit is 44 is opened for the next clock pulse via the line 45 and allows this to reach the counter input of the counter 40 via the upper input of the OR-So hold 39. This moves from "00" to "O1". Thus, the counter 40 counts to "10" with the next clock pulse and again to "11" with the next but one clock pulse Counter 40 remains with the counter reading "1.1" During the cycle of the counter 40 that has elapsed, the OR circuit 39 receives three clock pulses one after the other The shifting clock pulses arrive from the clock generator H via the line 45 * the AND circuit and the OR circuit 49 always dam * to the register R and the key register 31 when a clock quarter divider 47 to be described is currently blocked .

A line transmits from the output of this clock quarter divider 47 only every fourth clock pulse of the clock generator H and thus switches the register R and the key register; 51 by one step It should be noted that this quarter-cycle divider 47 corresponds to

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ORiGJMAL [NSPECTED

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. "is selected with the mode of operation of the counter 40, general

In my opinion, an n-digit counter 40 should have a clock divider l / n are provided. The from register R via the key register 31 running pulses switch an AND circuit 38 on and are passed on via output S when the AND circuit 33 is currently blocked. This condition is always fulfilled when the key register 3I has one of "1O" contains different value.

In summary, the method of operation of the key generator is shown in Fig. 5b explained as follows: At the beginning the counter 4o is "11" and the AND circuit 44 is disabled. The key register 3I stands on "OO", the And- »Se attitude 33 is locked and at the same time the AND circuit 38 is open. Four clock pulses switch the content of the register R and the key register 3I each by one step continue, and, as long as the key register does not contain "10", leaves the AND circuit 38 that passed by the key register 3I Impulses through. When the contents of the key register 31 assumes the value "10", the AND circuit 33 is opened. Included the AND circuit 38 is blocked and on the other hand a pulse given on the counter 4o. As already explained, the eaer Counter 4o successively the positions' W, "01" and "10" and finally "11" again. This corresponds to a quick shift of the values in register R and in key register 3I by three places. Since the AND circuit 38 is blocked, the three binary pulses resulting from this shift become

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not passed on. At the next clock pulse, the content of the key register 31 again ^{differs from tt} 10 ^w , and whenever this is the case, the AND circuit 38 is fulfilled and the binary pulses coming from the key register Jl are output via the S output.

Pig, 5c shows how pulses are emitted via the S output. The series of numbers labeled G is the one that comes from register R. Every time "IG" appears in the key register J> 1 , there is a three-digit omission and the Pig at output S. 5b only appear in the Pig. 5c with a vertical arrow provided binary values, which are given in accordance with the sequence indicated in row S1.

The key generator described is only an explanatory example; there are still possible other variations, namely, for example, with a keyword that is not tonstant, but changes continuously periodically This is illustrated in Fig. 5d, in which the two-digit binary number y the AND circuit in the previously considered example $ intervened , one after the other assumes the numerical values "00", ¹¹ Ol ", ^rt 10 ^w and" ll ^w. The omitted register shift is still three places, the number of omitted places could also be changed cyclically,

For a key generator with two registers, you can use

. Boccet FH 967 5OX 909887/0653

the pig. 1, 2 and jj explained general basic cipher, sentences are used and a modulo-2 addition of two pulse trains carried out from the two registers.

but
Advantageously, work is not carried out synchronously. Such an arrangement is shown in FIG. 6a. The outputs of two registers P and G, the details of which are Pig. k & and 4b correspond to the two inputs of an AND circuit 50. Its output S emits the key generator pulses. The output of the register P is also fed to the input of an inverter 51. Its output in turn leads to an input of an OR circuit 52. The other input of this OR circuit 52 is fed with clock pulses from the Talctgeber H.

This key generator works as follows: For each of the The clock pulse emitted by clock H becomes the content of the boiden register P and G shifted one place. If a binary 1-pulse air. The output of the register P appears, which the inverter receives, no signal is given to the upper input of the OR circuit 52. The AND circuit 50 leaves the register G run through the delivered binary pulse. If there is a wrong pulse at the output

eat

of the register P appears, the AND circuit 50 is blocked and the inverter 51 outputs a signal to the upper input of the OR circuit 52. This creates an additional shift of the two Register P and G causes. Since the AND circuit 50 is blocked, no pulse is emitted at the output S during this period. After this additional shift, there is again a 0 at the output

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of the register P appears, another shift is running, controlled via the inverter 5I, down until a binary 1 at the output of register P appears. This makes the AND circuit 50 conductive and the pulse coming from register G can reach output S.

The impulse sequence is shown in FIG. 6b. Two of them Pulse sequences coming to registers P and G are denoted by Pl and Gl. The pulse train emitted at the output S of the key generator is denoted rait Sl. Only the pulses of the sequence Gl that are accompanied by a 1 in the sequence Pl are passed on. Just these can pass through the AND circuit 50 and form the Follow Sl contribute. They are indicated by arrows between the pulse series Pl and Gl.

A key generator with three registers can be used as a combination can be viewed by two key generators with two registers each. Such an arrangement is shown in Fig. 7a. One register P works as a master register and two registers GO and Gl as generator registers. The pulses coming from the master register P run on the one hand to two AND circuits 55 and 58 and on the other hand via an inverter 53 to two AND circuits 54 and 57. The second The input signal for the AND circuits 57 and 58 is formed by the Clock H incoming clock pulse. The two generator registers GO and Gl supply the respective second input pulses to the AND circuits 54 and 55. The output signals of the two Ünd circuits 54 and 55 form the key pulses of the key generator, "

Doocet PR 967 501 »09887/088?

after they have passed through the OR circuit 56. The postponement the content of the routing register P is controlled directly by the clock pulses from the clock generator H. The shift in the content of the Generator registers GO and Gl are made by pulses coming from the AND circuits 57 ° of the 58.

Each clock pulse from the clock Ή shifts the content of the ladder range
registers P by one place and the two AND circuits 57 and 58 -ei ». If the value output by the master register P is a binary 1, the AND circuit 55 is switched on and the content of the generator register Gl is shifted by one place via the AND circuit 56. The binary value coming from the generator register Gl passes through the AND circuit 55 and is emitted as an output pulse at the output S after it has passed through the OR circuit 56. If, on the other hand, the number coming from the master register P is a binary 0, a switch-on pulse is given to the AND circuit 54 by means of the inverter 53, and the contents of the generator register GO are shifted by one place via the AND circuit 57. »Thus, according to the stipulation of the master register P, its zeros shift the generator register GO and ones the generator register Gl by one place. The principle of high variance is further perfected here with three registers. The shift between the generator registers GO and Eq. changes continuously according to the respective instantaneous values of the sequence in the master register P. The result is shown schematically in the Pig. Jb shown. The pulse sequence coming from the master register P is with P ¹ and the one from the generator

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socket FR 967 501 _{BAD onmmL}

1537341

registers GO and Gl coming poles labeled with GO 'and Gl'. The pulse sequence obtained at the output S of the key generator is denoted by S '. The figure shows that each 1 of the sequence P ¹ controls a position in the sequence Gl ¹ and that each 0 controls a position of the sequence GO ¹ . The control relationships are indicated schematically by arrows. The resulting pulse sequence S ¹ is a mixture of the two sequences GO 'and Gl%, which are separated from one another by a meander-shaped line C for better understanding. || All points in the sequence GO ¹ are above the meandering line C that corresponds to the sequence Gl ^! underneath.

Another example of a key generator with four registers is illustrated schematically in FIG ha.. Depicted. The four registers R1, R2, R5 and R4 are coupled to one another in pairs. Thus, the outputs of the two registers R1 and R2 lead to the inputs of an and circuit βθ and the tr outputs of the registers R3 and R4 to the inputs of an AND circuit 61. The output signals of these two AND circuits 60 and 61 are passed to an OR circuit 62 via two lines 63 and 64. Their output forms the output S of the overall arrangement. The shift functions within these four registers are controlled by the H clock. With each clock pulse the content of the four registers Rl to Rk is shifted by one place »

If the binary values running out of the registers R1 and R2 Both are 1, the AND circuit 60 is turned on

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and a signal runs over the line 65. If both outputs do not give a 1, but one place a 0 or both places a 0, the AND circuit 60 remains blocked and no signal is given over the line 65. The same applies to the two registers R3 and R4 in connection with the AND circuit 61 and the line 64. A pulse appears at the output S every time at least one of the two lines 63 and 64 transmits a signal, ie every time when at least two ones appear simultaneously in one of the two groups R1 and R2 or RJ and R4. The result is shown in Fig. 8b. The pulse trains emitted from registers H to R4 are identified by Rl *, R2 ^f , RJ 'and R4 ^! designated. The pulse sequence resulting at output S is represented by the series S *. It can be seen that this last sequence only contains ones if at least one of the two groups Rl ¹ and R2 ¹ or RjS ¹ and R4 ¹ simultaneously contains ones.

The versions described so far only serve as examples for key generators that are expanded by changing the circuit arrangement or the number of registers used can. A simple case is indicated: the one shown in FIG Circuit arrangement of the two AND circuits 60 and and the OR circuit 62 could ^ be exchanged, i.e. the outputs of the two registers R1 and R2 were switched to one. Or circuit given; likewise the outputs of registers RJ and R4. The outputs of these two OR circuits were in an AND circuit summarized, which emits the key pulse sequence via the output S.

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Only the key generator arrangements were used in the illustrated examples explained on the sending side. In a complete transmission system, however, two such generators are required, ' one on the sending side and one on the receiving side. The decrypted message then emerges on the receiving side a modulo-2 addition with the key generator on the Receiving key pulses obtained, as in the Pig. I, 2 and j5 has already been explained.

An advantageous increase in the variance of the key pulse sequences obtained can be otherwise except through others or extended Groupings of registers e.g. by the provision of more than two groups according to Fig. 8a ^ also by a changed one Arrangement of the modulo-2 adder 19 or even several within achieve the register arrangement in extension of Fig. 4a.

Docket FR 967 501

'BAD ORIGINAL - "*'.

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Claims (1)

- 21 - 1537349 Claims 1> Circuit arrangement for encryption and decryption in pulse form transmitted messages, in which the plaintext pulse sequence to be transmitted is added by modulo-2 addition on the sending side a key pulse train is mixed to an encrypted pulse train and transmitted and encrypted on the receiving side Pulse train also by modulo-2 addition with the same key pulse train as on the transmission side for recovery the original plaintext pulse sequence is mixed, whereby, send- andj the same key pulse sequences on the receiving side Similar key generators with variable initial conditions determined by agreement between the sending and receiving sides generated and used and the two provided key generators at least one shift register each included, the output of which is connected to its input, characterized in that in each case the output (A) of the shift register (Fig. 4a) is connected to the second input (E2) of at least one modulo-2 adder (19), which with his / her the first input (El) and output is / are inserted between two consecutive stages of the shift register (Pig.4a), so that each at the shift register (4a) via its output (A) available pulse train due to the passage through the Mo » dulo-2 adder (19) of constant, regular change is subject. Docket FR $ m 501 9 0 98 Ö 7 / Oil S δ 2. Circuit arrangement according to claim 1 with a shift register, characterized in that a test circuit (29) for determining the correspondence of a limited part of the data from the shift register (R in Fig. 5a) outgoing, as a key pulse train * usable pulse sequence with a comparative binary sequence is provided that the output of this test circuit (29) is routed to the switching input (K) of an output lock switch (2h) and that the pulse train emanating from the shift register (R) is routed via this output lock switch (24), so that only if the monitored, limited part of the pulse train is not the same, pulses from the shift register R are emitted as key pulses for enciphering or deciphering the messages to be processed modulo-2, 3. Circuit arrangement according to claim 1 with a shift register, characterized in that a test circuit arrangement (31, 32, «53i 37) ^for determining the correspondence of a limited part of the from the shift register (R in Fig, 5b) outgoing, usable as a key-key pulse sequence with a Comparative binary sequence is provided that the output of this test «circuit arrangement (31, 32, 33, 37) is led to the first input of an AND circuit (38) and that the pulses from the shift register (R) via the second input of this AND circuit (38) are carried out, so that only if the monitored, limited part of the pulse train is inequality with the comparison bin sequence pulses from the shift register R as the key Baths * R 967 501 909887/0659 pulse for encryption or decryption of the modulo-2 * · Pending messages will be submitted » 4. Circuit arrangement according to claim 2 or 3, characterized in that that the comparison binary sequence used is constant. 5 circuit arrangement according to claim 2 or J5 # characterized in that that the comparison binary sequence used is a variation according to a given regularity that is the same in the transmitter and receiver is subject. 6. Circuit arrangement according to claim 1 with two shift registers, characterized in that the outputs of the two shift registers (P, G) with the two inputs of an AND circuit (50) ' are connected that this AND circuit (50) forms the output (S) for the key pulse sequence to be issued, that clock pulses from Output of a clock (H) to the shift clock inputs of the two shift registers (P, G) used and that additionally the output of one of the two sliding | register (P) directly or via an inverter (51) to the shift clock inputs the two shift registers (P, G) is performed. 7 · Circuit arrangement according to Claim 1 with three shift registers, characterized in that clock pulses from the output of a clock generator (H) the shift clock input of one of the three used Shift register (P) directly and the shift clock inputs Docket FE 967 501 of the other two shift registers (GO, Gl) indirectly via the .. first input to a first and second AND circuit (58, 57) that the second input of the first AND circuit (58) before the shift clock input of one of the two indirectly controlled shift registers (Gl) is connected to the output of the directly controlled shift register (P) that the output of this directly controlled shift register (P) via an inverter (53) to the second input of the second AND circuit (57) before the shift clock input of the other indirectly controlled shift register (GO), that the output of the inverter (53) is also connected to the first input of a third AND circuit (54), that the input of the inverter (53) on the other hand also to the first input of a fourth AND Circuit (55) is connected so that "the outputs of the two shift registers (GO, Gl) indirectly controlled via the first and second AND circuits (58, 57) with the second inputs of the third th and fourth AND circuit (54, 55) connected and that the outputs of the third and fourth AND circuit (54, 55) via the two inputs of an OR circuit (56) as an output (S) for the key! are summarized, 8. Circuit arrangement according to claim 1 with four shift registers, characterized in that from the output of a clock (H) Clock pulses are fed to the shift clock inputs of all four shift registers used (Rl, R2, R3, R4) that the outputs one pair each (Rl, R2j R3, R4) of the shift registers (Rl to R4) - Bt 9W Sbl. ' 909887/0659 ; · ■■ "■ '' ■ * 25 - ■. * ■ are combined with an AND circuit (6o, 6l) and .that the outputs of these two AND circuits (60, oil) as Output (S) for the key pulse sequence to be issued by means of a OR circuit (62) are combined. 9. Circuit arrangement according to claim 1 with four shift registers, characterized in that from the output of a clock (H) tact
Clock pulses are fed to the shift inputs of all four shift registers used (Rl, R2, R ^, R4) * that the outputs each of a pair (Rl, R2; R3, -R4) of the shift registers (Rl to R4). . ' are combined with an OR circuit each and that the outputs of these two OR circuits are combined as output (S) for the key pulse sequence to be issued by means of an AND circuit, 10. Circuit arrangement according to claim 1 with η shift registers, characterized in that the outputs of a part m of this η shift registers can be used to generate additional clock pulses, ~ which, in addition to the clock pulses from a central clock generator (H) to the shift clock inputs of the η shift register or at least a part of them are given, 11. Circuit arrangement according to claim 1 with χ shift registers, characterized in that the shift clock inputs of all these χ shift registers receive clock pulses from a central clock "(H), that the outputs of these χ shift registers *. · D _Q oket m 967 501 ■ 90 «*« 7 / .065 #, in groups (in pairs, threes or similar), each with a parent And circuit (or circuit) are combined and that the outputs of all these AND circuits (OR circuits) for the purpose of being combined to form the overall output for the one to be output with Key pulse train / an OR circuit (AND circuit) merged are. 12 »Circuit arrangement according to one of the preceding claims, characterized characterized in that the arrangement of the modulo-2 adder (s) within the shift register (s) used different and / or according to agreement between the sender «and Receiving side is variable *. 15. Circuit arrangement according to one of the preceding claims, characterized characterized that according to agreement between the sending » and receiving side the length of the shift registers used and / or their grouping is variable. Docket FB §6? 501 -9-09687 / 065-9