DE1524134C - Multiple data processing system - Google Patents

Description

The invention relates to a data processing multiple system in which a plurality of data-processing devices have access to a storage unit in order to store them through Process items of common data marked with codes, with registers for storing the code and comparison circuits for deriving signals controlling the processing of the stored data.

It is known to belong to groups or items To assign data to a specific code and to use this code for processing to control this data, namely to interrupt a certain program when the Code assigned to groups or items of data corresponds to a code stored in a register. In this case, a control signal is derived with the aid of a comparison circuit that the program is interrupted and replaced by a subroutine belonging to the code. In this known system, however, only one data processing device is assigned to the memory, and it the program is influenced with the help of the code identifying the data posts, according to which this Data are processed.

In contrast, the invention is concerned with data processing multiple systems that the Have the purpose of having relatively high computing speed,

to achieve such things as B. in real-time data processing systems or in other systems where it is desired to have a maximum amount of data in a given period of time is processed. When using a common memory, every data processing device is able to call memory. If several of the data processing cndcn Devices have access, there is

3 4

drive, that the same data simultaneously instead of after- F i g. 3 and 4 two examples of programmed one below the other processed, with the result that programs that explain the principles of the the effect of the operation served by one of the data modes of the present invention, processing devices is carried out by the F i g. 5 is a block diagram of a portion of each of the FIGS Operation nullified by the other 5 F i g. 1 shown data processing devices with the ren data processing device is running. Ahn- more specifically shown lock registers, Problems arise in the case of data processing. in which each data processing device follows each of the data processing devices Device is suitable for any of a plurality of Fig. 1,

Perform functions, and in which it is desired io F i g. 7 a partial circuit diagram of the program control

is, and that any given function is to be called each of the data processing devices,

at any given time only by one single F i g. 8 and 9 are timing charts for explaining FIG

umpteen data processing device is running. Operation of the locking device according to the invention

Accordingly, the object of the invention is to

reasons, an improved data processing system. 15 Fig. 10 is a circuit diagram of an embodiment

Create specialist system that contains a large number of data - one shown in the previous figures

processing devices that lead to a gene NAND gate,

common memory, in which common data is Fig. 11 a block diagram of an embodiment

are stored, have access, but in a counter-form to one shown in the preceding figures

other are locked so that at any one time 20 flip-flops,

only one data processing device the common Fig. 12 is a block diagram of execution data Bring it up to date or in the form of a gate to perform the complement can process it in a different way, so that no one gives way to the exclusive OR function that is in the Vertigen Data can be lost. equivalent circuit according to FIG. 6 is used,

This task will be based on the initially shown 45 Fig. 13 an overview of the complement of the mentioned data processing multiple system according to the exclusive OR function and solved the invention in that in each of the F i g. 14 is a simplified block diagram showing two data-processing devices a register and a data-processing device shows that with a meh comparison circuit it is provided that the memories comprising other banks are connected. · Each device is connected in the same way as in the associated 3 ° Fig. 1 shows the block diagram of two data networks Register entered code in each case with the processing devices Pl and P 2, which with a Compares codes that are linked in the registers of the other memory unit 20 that has a memory data processing devices are included, and a 21, an address register 22 and a data register 23 Comparison signal generated that contains a certain value. Although only two data processing devices assumes that if data is shown in someone else's register, it goes without saying that any processor Device already has the same code pre-number of data processing devices with the memory hand is, and that in each of the data processing unit 20 can be connected. The data processing devices Means for program control provided tend device P2 is the data processing device Pl are identical to that generated in the respective device and have the same reference symbols for the same EIe comparison signal address and transfer the 40 mente. The data processing device Pl contains a Item of common data entered by the buffer register (B register) 31, a command register Register of this device identified code entered (C-Register) 32 and a program counter (P-counting is to read from the memory unit to the device) 33. In general, it is the function of registers 31 disable when the comparison signal is the determined and 32, data from the data register 23 of the Has value so that only one of the 45 storage units 20 can be received at any given time, and it is less data-processing Devices one by one, at least part of the data that is received from the command register Correct code marked items common 32 are received, decoded in a decoder 34, Able to process data. to provide decoded program control signals which,

The invention therefore uses a locked one, as is known to the person skilled in the art, for this purpose

data processing multiple system created in which 5 °, various processes in the data processing

to control shared data in a storage unit, which also has a clock

are chert, to which each of the data processing encoders includes 35 for the delivery of clock signals,

rate has access, but in which the data on each addition includes the data processing device P1

any time only from one of the data processing a parallel adder 38, which together with a

the devices are brought up to date 55 flip-flop 39 with means for program control, namely

can, while each other of the data processing lent a program control unit 40, is connected,

the devices that have the same function during this time are described in detail below

shared data is needed in a kind of waiting position. How the circuit layout works

ment is held until the up-to-date construction of the data processing device Pl, which was previously

The shared data brought to the memory ⁶ ° can best be related

have been returned. be explained with Fig. 2a, which is a scheme of a

In the following, an embodiment of the Er command word 45 is shown, which is from the memory 21

Finding described on the basis of the drawing. It points via register 23 to registers 31 and 32 of

1 shows a general block diagram of an er-PI can be called up. As it is for the understands the inventive data processing multiple expert 65, the command word 45 is thereby

plant, obtains that the address register 22 with the signal

Fig.:2a and 2b Schemes of command words that are excited in the program counter 33, which is a type used in the system according to the invention, address, such as X, of that command word.

represents that desired by the data processing device P1 will. As FIG. 2a shows, word 45 comprises 18 bits, of which the first 5 bits are used to form an operation code can be used. Bits 5 to 8 define a first λ field which, together with the operation code is transferred to the command register, while bits 9 to 17 are an F field which is transferred to the buffer register.

The code in bits 0 through 4 is decoded in decoder 34 to. To deliver control signals that. to control the processing of the data in the fields Y and R, which are stored in the registers 31 and 32, in connection with other data which are stored in shift registers, accumulators and / or other circuit parts of the data processing device, not shown, by the data processing device Serve device. Techniques for decoding an operation code to control the processing of data received from a memory by a data processing device are well known and therefore will not be described in detail. In addition to the decoding of the operation code, the decoder 34 also supplies a signal which is fed to the program control unit 40. The function of this signal is to cause the program counter 33 to apply its contents, ie, X, to the parallel adder 38 and set the flip-flop 39, which can be considered a source of a +1 value, so that a +1 is also transmitted to the adder 38. As a result, its output signal is X + 1, which is transferred to the program counter 33 after the processing of the last command word has been completed, in order to request the next command word from the memory, which is located at the address X + 1.

In accordance with the teachings of the present invention, each of the data processing devices P1 and P 2 includes an interlock circuit 50 which prevents the two data processing devices from running at the same time retrieve and update a post of shared data. In short, that includes Latch circuit 50, which will be described in detail hereinafter, a lock register (L register) 51, which is based on data in the B register 31 and the C register 32 and on decoded signals from responds to the decoder 34 to set the L register 51 and store therein data, the one Represent code number assigned to a specific item of common data. The output signal of the L register 51 of the one device 51, together with the output signal of the L register 51 of the Another data processing device P 2 is supplied to a comparison circuit 52. The output of the comparison circuit 52 is connected to the program control unit 40 and a circuit 53 for resetting the Lock register connected, which resets the lock register 51 when activated accordingly. "'.'

F i g. 2 shows the scheme of a locking code number command word 55. As can be seen, it contains an operation code in the first five bits, as is also contained in word 45 (FIG. 2a). However, instead of the R and Y fields in bits 4 to 8 and 12 to 17, word 55 contains iV fields and bits 9 to 11 an incrementing code, which instead of a normal command word to buffer register 31 to the Command register 32 is transferred. The / V fields define the code number of a particular item of common data. Whenever an item of common data is to be brought up to date in PI, a command word, such as word55, is transferred to the B and C registers of the data processing device PI. Bits 0-4 and 8-11 are decoded in decoder 34 indicating that the command word is a lock code number word. As a result, the decoder 34 sets the lock register 51 in the state, the

ίο Bits 5 to 8 of the C register 32 and bits 12 to 17 of the B register 31, which represent the code number contained therein. '

This code number is then compared with each code number in the register 51 of the data processing Device P 2 may be stored. If this comparison is positive, i.e. if the lock register 51 of P 2 contains the identical code indicating that P 2 is the specified item of common data processed, the reset circuit 53 of PI is energized to reset the register 51 of PI. Furthermore, the comparison circuit causes the unit 40 to call up the next instruction word of the program. The next word can be a retransmission command, stating that the code of the previous, the word representing the command code number was not reached, and the transfer command can then move the control and cause the delayed command again from the Storage unit is received. This process can continue until the lock register 51 of P 2 is free, so that when the code number is stored again in the lock register of Pl will result in a negative comparison. In this case, the reset circuit 53 is stopped so that the code number remains stored in the lock register 51. In addition, the output signal causes the Comparison circuit 52, the program control unit 40 to skip the retransmission command and the Continue processing of the common data in the data processing device P1, as it did afterwards will be described in more detail using a special example.

It goes without saying that the command following the lock code number command follows, may be other than, a retransmission command. For example, at Presence of a positive comparison indicating that the other data processing device is the specific one Post common data processed, the next command the data processing device another feed programmed subroutine until the particular item has common data from the other data processing device is brought up to date and returned to the storage unit.

For the purpose of explanation, it is assumed that an item of common data D is stored in the memory unit at an address X and that the data D is assigned a code number C _D. In any subroutine in which data D occurs at address X and in which it is desired that the data D be processed by only one of the data processing devices at a given time, the instruction to transfer the data then goes according to the teachings of the invention D in the data processing device two commands ahead. 3 and 4, subroutines for the data processing devices P1 and P 2 are illustrated. The subroutine according to FIG. 3 for PI is to add a one (1) to data D.

add, while the subroutine according to FIG. 4 is to subtract a two (2) from the X data.

In each of FIGS. 3 and 4, the first column represents the instruction number or the address in the memory unit at which an instruction word having the structure shown in column 2 is present. The third column shows the value of the fields in each command word, while the fourth column contains information about the type of command. Except for the first and the last, the instruction words in each of the subroutines have a structure like the instruction word 45 of FIG. 2a, which is common in the art. The first five bits are dedicated to an operation code, while the other 13 bits are divided between the two fields R and Y. The first and last instructions in each of the subroutines relate to locking and unlocking the code number in the lock register. Therefore, each of the lock command words has a format like the command word 55 of FIG. 2 B. Bits 0 to 4 and 9 to 11 are dedicated to the operation code and the incrementing code, respectively, while bits 5 to 8 and 12 to 15 are dedicated to the N field , which represents a code number of the particular data item.

It is assumed that at some point during its operation, the data processing GerätPl has run subroutine shown in Fig. 3, which implies that the g at the address X in the memory unit 20 according to F i. 1 stored data a "1" should be added. In order to execute the subroutine, the data processing device P1 is first caused to request the command word with the address W from the memory unit. As can be seen from FIG. 3, the word represents the command to lock the code number C ₀ , which is assigned to the data at address X , in a lock register of P1. This is because the field N of the command word at the address W is equal to C ₀ . If this locked command word in the buffer register and. is received in the PI command register, bits 0-4 and 9-11 are decoded in decoder 34 to provide a signal to lock register 51 which enables register 51 stored in the B and C registers Record and save N-field. Then the output signal of the lock register 51 is compared by the comparison circuit 52 with the output signal of the lock register 51 of the other data processing device P2.

If a positive comparison results, ie if the lock register 51 of P 2 contains the code number C ₀ and thereby indicates that the data processing device P 2 is acting on the data stored at address X , a signal is fed to the reset circuit 53 to cause a reset of the lock register 51 in PI. The data-processing device P1 thus increases the content of the program counter 33 during its normal operation, so that the next command word stored at an address W +. '1 is requested. When the last-mentioned command word is received and stored in the B and C registers of the device P1, the code 00 of the command word, which is present in the first five bits of the word, is decoded in order to send a command back to the previous one Deliver to address W. Namely, the instruction to lock the code number C ₀ in the lock register 51 of P1 is repeated.

These operations are repeated until the lock register 51 of the data processing device P 2 is not locked, so that when the code number C ₀ is stored in the lock register 51 of P1 and a comparison is made by the comparison circuit 52, a negative result is obtained. If so, the reset circuit 53 is shut down, that is, it will not reset the lock register. Therefore, the code number C _{0 will be} stored and retained in the register 51 of P1. The negative comparison will also cause the program control unit 40 to skip the command word in the address W + 1. This means that the value in the program counter 33 is increased by "2" if a negative comparison is made, so that after the command word has been received from the address W, the command word from the address W + 2 is next requested and the Transfer command that is present at address W + 1 is skipped.

Thereafter, the data processing device P1 operates in a conventional manner by receiving the command present at address W + 2 which is a fill command for transferring the data from address X. After this data has been transferred to PI and temporarily used in any conventional circuit, such as e.g. B. have been stored in an accumulator or other (not shown) registers, a command is given to the data processing device with a command. to supply a word that is located at address W + 3. As shown in FIG. 3, this command word has an operation code, which is represented by number 22, which may indicate that a "1" is to be added to the data previously transferred to PI, i.e. to the data transferred to PI from address X. are. After the next command, the command word is to be requested from the address W + 4, which has a code 26, which means that the data formed in Pl are to be stored in the memory at an address which is determined by the sum of the fields R and Y des Command word is defined and, as can be seen from column 3, is equal to X. The formed value D + 1 is therefore transferred to the address X. After this command, the conventional subroutine is ended because the data D previously stored at address X has been updated by adding a "1" and the value D + 1 at address X has been stored again.

However, code number C _{0 is} still stored in lock register 51 in accordance with the teachings of the present invention. Therefore, an additional instruction is included in the subroutine to enable PI's lock register. This is achieved in that a further command word is provided which is stored at an address W + 5. This command word can have a code number 14 in bits 0 to 4, which indicates that it is either a blocking command or a release command. However, the incrementing code in bits 9 to 11 is a "0" so that when it is decoded in the decoder 34 it is indicated that it is an enable command. The fields of bits 5 to 8 and 12 to 17 are also "0", which also indicates that the IK'-

209 643-11

9 10

The wrong word is a release command. As a result, device Pl returns the number "2" must be subtracted, D -f- 1, and

the decoder of the reset circuit 53 sends a signal, it carries out the processing of this value in the data

so that the lock register 51 of PI reset processing device P 2 to the value D - 1, the

or is released. the data processing device P 2 back to the

Thereafter, the data processing device P1 is stored in 5 address X after it has executed the subroutine stored by the subroutine which is capable of any other programmed address Z + 4. When the command to be determined has been carried out.
leading, subsequent subroutine also includes a. From the foregoing it can be seen that, if items include common data, an operating process is repeated, although both data processing devices are independent. That is, first connected to one another with the memory unit 20 a lock command for locking the code number which are and both have access to the memory in order to receive data from an item of common data, and to process them which are received is to determine whether any processing device do, ch associated with means other of the data processing devices are these items, which ensure that any common data is processed. If other data processing devices are only processing such data at a given time, a common data item will be received up to date of the transmission command, which causes status to be received. And only when this one data processing device Pl so long the processing device ends its operations and returns the lock code number command until the other has returned the data to its address or its place in the data processing device its operations on the 20 memory, another can Has finished posting shared data. data processing device that is up to date

As seen from Fig. 4, the command words stand accommodated items common data empin the two sub-programs are very similar off, catching, to subject it further operations, as seen from the fourth instruction word shown in FIG. 3 ¹ Thus accumulative errors, the data transmitted by more than one data processing device, while in FIG. 4 the command consists in this, can be avoided.

a number from the data in the data processing FIG. Figure 5 shows the block diagram of a special subtracting device. According to the foregoing, practically implemented exemplary embodiment, it goes without saying that when the data processing device P 2 tries to lock a code number in the lock register, the in-FIG. 4 illustrates 51 executing the present subroutine in accordance with the teachings discussed above while practicing the invention. As shown in FIG. 5, the data processing device P1 comprises the data register 23 of the memory unit 20, which is shown in FIG first nine bits 0 to 8 of the command register of the address Z received and the code number C _D in are connected, according to F i g. 5 comprises 12 bits, the lock register 51 of which is entered, the further bits 12 to 17 of the data register are the same in its comparison circuit are positive 23 with bits 12 to 17 of the buffer register 31 and therefore the data processing device P2 den which, according to FIG. 5, comprises 18 bits, of which the command is received to receive the next command word, but only bits 9 to 17 actually used, which are and are present at address Z + 1. Bits 9, 10 and 11 of data register 23 which cause data processing device P2 to return with bits 9, 10 and 11 of the command to the command word at the register as well as with bits 9, 10 and 11 of the address Z is present and in which the command buffer register 31 is connected. Such an arrangement is included, the code numbers C ₀ , which is necessary to lock the code numbers C 0, because bits 9, 10 and 11 of the data address X stored items of common data register 23 are sometimes assigned to the B register. when the data it contains is a part

If the command at address Z is the R field, as previously explained in connection with the word from the data processing device P2, while in other cases the bits are caught after the data processing device 5 ° 9 to 11 of the data register 23 the Er-Pl brought the data up to date and contain elevation code, as it was described in connection with the command to release its lock register issued Fig. 2b. Therefore, the comparison is negative. As a result, bits 9, 10 and 11 of data register 23 with the command-speaking bits present at address Z + 1 will be skipped in both registers 31 and 32, and the data-processing link will be bound. The outputs of bits 0 to 4, 9, 10 guessP2 are then free, the command series stored at addresses Z + 2 to and 11 of the C register 32 can be received and connected to the decoder 34 Z + 5.

while executing the subroutine which consists in assuming that one of the registers is to subtract the value 2 from the data 31 and 32 previously received by the data register 23 from the address X. 60 command word is a lock code number command word as it are. However, it should be noted that, for example, in the first line of FIG. 3 shows the data that the data processing device P 2 represents. It can be seen that such a word received in does not have the value D , but rather bits 0 to 4 have a code number 14 and bits 9, the value DI 1, which is assigned to the address X of the 10 and 11 a code number 4 contains. When the data processing device P1 was transmitted, it executed the command as 65 output signals of bits 0 to 4 and 9, 10 and 11, which is represented by the address W + 4 present in the command register to the decoder 34. Deliver.es on its output line 61 a blocking So is the value of which the data processing signal MYC 29. As before with reference to Fig. 2b,

11 12

3 and 4, the code number of the men is the output of the flip-flop 38, on a first

Post of common data through which N-fields will be in level representing a binary "zero",

the lock code number command word, which occurs during the output of the flip-flop 88, the

in bits 5 to 8 of the command register and the bits of the number 4 correspond to! on a second level

12 to 17 of the buffer register. 5, which represents a binary "one". In

As can be seen from Fig. 5, the lock contains Fig. 5 are the outputs of the flip-flops 81 to 90

Register 51 ten NAND gates 71 through 80, one of which is designated as L01.4 through L10A . The number denotes

for the sake of simplicity only the first and. the last the flip-flop, while the letter A indicates that

both are shown. The register also contains the signal from the lock register 51 of the device P1

the 10 flip-flops 81 to 90, from which only the io comes.

The first and the last two shown in Fig. 5 "The output signals L 01 A to LWA of the flips are. All NAND gates operate as AND gates, flops 81 to 90 are fed to the comparison circuit 52 because only if all of their input signals are" true " which is shown in Fig. 6. As can be seen from Fig. 6, the gate provides a "false" output signal, each of the outputs LOIA is set and cleared during each of the flip-flops until L10A becomes another one of gates 101-110 . Specific a spe control terminal C is supplied, is true essential embodiment of a; as a function of the signal fed to an input each of these gates performs the complement clamp / is supplied when the signal of an exclusive-OR function by. of such a gate, embodiments of one operating as an AND gate will be described in detail hereinafter, another one of the NAND gate and one as previously described is output from gates 101 to 110 of FIG each operating flip-flops are subsequently treated in detail with a different flip-flop of the lock register 51 of the. Supplied to other data processing device P 2,

As shown in FIG. 5 shows the control terminals, the last letter B indicating that the signals

of the flip-flops 81 to 90 with the outputs of one originate from the lock register 51 of P 2. To the

NAND gate 53 connected, the previously on hand 25 gate 101 is accordingly the output signal LOlA

Fig. 1 forms the reset circuit described. That of the flip-flop 81 of the lock register 51 of P1 and

Gate 53 performs an OR function in that it continues to output signal L 01 B of the same

an output signal "true" always supplies when flip-flops in the lock register 51 of P2 are

any of its input signals is "false". leads.

One of the input terminals of the NAND gate 53. 30 In the same way, each of the other gates is connected to the decoder 34 and receives a "false" signal OMYC 29 via the comparison circuit 52 with the output signals, always from a different one of the flip-flops Lock register 51 when the decoder 34 supplies the devices P1 and P2 on the output line. The function of a 61 supplies the lock code number signal MYC 29. In each of the gates 101 to 110 there is a following one denotes the letter O, which one can only deliver "true" output signal when preceded by any signal designation, a "false" one - the two signals fed to them either at both levels . The signal MYC 29 thus represents a "true" - binary zeros or binary ones are. The AusSignal represents, while OMYC 29 represents a "false" signal output signals of the gates 101 to 110 represent. The lock code number signal MYC 29 is per input signals of a NAND gate 112, which acts as an input of all NAND gates 71 to 80 and 4 ° AND gate, so that only if all leads, while the other input of each of the Gate Output signals of gates 101 to 110 and thus with the output of another bit of either the. all input signals of the NAND gate 112 "true" command register 32 or the buffer register 31 are gone, thereby indicating that the numbers that are bound. in the two lock registers 51 of the two data

As shown in FIG. 5, the gates 71 and 45 processing devices are stored, 72 are identical to bits 5 and 6, respectively, of the command register 32, an output signal is "false". The output is tied, while the gates 79 and 80 with the bits of the NAND gate 112 are connected to the input of a 16 and 17 of the buffer register 31. NAND gate 114 connected, which acts as an inverter. Correspondingly, bits 7 and 8 of the command and a "true" output signal are provided when number registers and bits 12 to 15 of buffer register 50 in the two registers are identical with the NAND gates 73 to 79 connected. When the output of gate 114 is used as the output of bits 0 through 4 and 9, 10 and 11 input to a NAND gate 116, instruction register 32 is decoded and therein acts as an AND gate. The other input, the codes 14 and 4 are determined, supplies the signal of the NAND gate 116 is supplied by the decoder 34 to decoder 34 a lock code number signal MYC 29 and 55 and forms a comparison readiness of its complement OMYC ■. 29 to the gates 71 signal CEl, which the decoder 34 delivers simultaneously with the to 80 or to the gate 53. As a result, the lock code signal MYC 29 is delivered. If two contents of bits 5 to 8 of command register 32 and numbers in two registers are identical, bits 12 to 17 of buffer register 31 are NAND gates 71 to 80 in flip-flops 81 via the two input signals of NAND gate 116 up to 90 6 ° "true", and as a result its initial value is stored. ■ OLKR signal »wrong«. However, if during the

Let it be Assume, for example, that the code number has a lock code number period, i. H. at the time that

Has the value 4 and the output signal of the flip-flop 81 signal CEl is fed to the NAND gate 116,

the most significant bit and the output of the two numbers in the lock registers 51 of the

Flip-flops 90 represents the last digit. It understands 65 data processing devices Pl and P2 not identical

then it is clear to the expert that after the table is one of the input signals of the NAND-

write the code number 4 in the lock register 51, gate 112 "wrong" and therefore the output signal

the outputs of all flip-flops 81 to 90, with the exception of NAND gate 112, are "true". As a result is

13 ¹⁴

the output signal of the negator 114 "false" and tive comparison between the two code numbers, the output signal of the NAND gate 123 acting as an AND gate, a "true" output signal of the NAND gate 116 "true". If, therefore, during supplies, which is denoted by MYC 161 in FIG. 7. the lock code number period of the output signal of the The last-mentioned signal is the information

NAND gate 116 is "false", it indicates that the 5 inputs of flip-flops 124 and 125 are supplied. the Both numbers in the two lock registers are identical. The function of the flip-flop Ji24 is to generate a signal are table while a "true" output signal is to be supplied to energize the flip-flop 39 (see FIG. 1) End of this period means that the two numbers and a +1 value are sent to the parallel adder 38 differ from each other. transferred to. The function of the flip-flop 124 is in

As can be seen from FIG. 5, the reset io FIG. 7 is represented by the number +1, which is entered in brackets in the block 124 in a round circuit formed by the NAND gate 53. Similarly, which works as an OR gate, with the output, the flip-flop 125 has the function of supplying a control signal output signal of the NAND gate 116, that is to say supplying the program counter 33 with the content of the signal OLKR to one of its inputs Zug- the program counter 33 leads to the parallel adder 38. Whenever the numbers in the two 15 feed. The function of the flip-flop 125 is identical in lock registers 51, the signal F i g is. 7 by the symbol Ρ- * _Σ OLKR in brackets »wrong« and thus the starting point is illustrated.

signal of the NAND gate 53 "true". As a result, the NAND gate 123, which acts as an OR gate

all flip-flops 81 to 90 are cleared, so that the. works, is still with further input signals Code number that was previously supplied to you by bits 5 to 8 of 20. One of the input signals is from the C register 32 and bits 12 to 17 of the B register output signal of a NAND gate 126, sters31 was supplied, is deleted. that works as an AND gate. As shown, has

The output signal of the comparison circuit 52, the gate 126 having two input terminals, to which the gate 116 fed by the output signal OLKR of the NAND- decoded signal from the decoder 34 is represented, will also be the pro-25 which is designated as K 5-1 and OTRY denotes wergram control unit 40 supplied to the program. Essentially, the function of the sequence of the data processing device P1 in relation to NAND gate 126 is to control NAND gate 123 so that the necessary subsequent command is supplied with a "false" signal in order to determine the number of the word, as dealt with above, is requested. If the program counter 33 in the parallel adder 38 indicates that the output signal OLKR of the comparison 30 is increased by "1" whenever a command circuit 52 is "true" and a negative word is decoded by the decoder, indicates an excepted comparison, If the command word causes an over-device, the data processing menu represents one of the command words, namely transfer command, which is characterized by the code 00 to skip the return transfer command (see FIGS. 3 and 4). If one is to be able to receive its function with the recording 35 transmission command, that of posting common data is thus to continue. If the signal OLRY, which is fed to the NAND gate 126, but the output signal OLKR is "false" and becomes "false," and it is therefore that of which thereby indicates a positive comparison, the NAND gate 126 is supplied input signal for the data processing The device is controlled in such a way that its NAND gate 123 is "true", so that the function signal is "false" with the request for the next command 40 MYC 161 and is prevented from continuing the word which is an over- Flip-flops 124 and 125 act to execute their enttragüngsbefehls, so that the data processing-speaking functions to initiate. As can be seen from the device in a certain sense in a loop Fig. 7, the NAND gate 123 is trapped, which causes it to be supplied with the locking code further input signals, which, if the number command is supplied until a negative 45 they are "false" have the effect that the NAND gate tive comparison in the comparison circuit 52 to 123 delivers a "true" output signal MYC 161, which comes up. an increase in the content of the program counter 33

For a better explanation of the way that "1" causes the next command word, Control of the program control unit 40 is requested from the next address of the memory 7 referenced, which is a simplified block circuit 5 °.

Figure of a portion of the program control unit 40 shows the portion of the program control unit 40 that is shown at

as is necessary to practicing the teachings of the present invention disclosed herein. As can be seen, the circuit comprises manure, a NAND gate also contains a NAND gate 122, one input of which is the 128, which operates as an inverter. The input of the comparison ready signal CEl is fed to 55 gate 128 is connected to the output of the NAND gate while another input of the NAND gate 116 (FIG. 6). The output signal of the 122, the output signal OLKR of the comparison gate 128 is used as an input signal for a NAND device 52 is supplied. The NAND gate 122 gate 132 which functions as an AND gate. The other works as an AND gate, so that during the inhibit input signal of the NAND gate 132 can be of code time period when the signal MYC 29 is available. 6 ° is supplied to the data processing device P1, only if the two code numbers in and the priority of the operations of P1 with respect to the two lock registers 51. are different and therefore the signal OLKR is "true" on the priorities of the other data processing devices. is to display the output signal devices. Assuming that the opera of NAND gate 122 is "false". This _; ^: Ausrations of the data processing device; / '2 the output signal · is supplied as one of the input signals ^' to a 65 priority over the operations of the data processing NAND gate 23, which has the device P1 as an OR gate, this is with OFO 7 designated arbeilet so that if the output of the input of NAND gate 132 is "true". Because NAND. Gate 122 is false, that is to say if there is a negative as described above, if a positive is present

15 16

Comparison, ie if the code numbers are equal in ', the outputs of which are connected to the information input two lock registers, the signal OLKR "false" and to the flip-flops 81 to 90. Therefore, when the output signal LKR of the NAND gate is at the same time, the decoder 34 on the line 62 delivers 128 "true", in this case both input signals are signals of the NAND gate 132, denoted OMYC 29 in FIG "True" and therefore 5, so that the NAND gate 53 has a "true" -out output signal "false". The output signal output signal to each of the control terminals of the flip-flops of gate 132 is fed to a NAND gate 134, which supplies 81 to 90 and thereby enables them to operate in Überais OR gates, as one of the input matches with the output signals of their designals, see above that when the output-speaking NAND gate is set, the signal of the gate 132 is "false", the output signal of the gate 134 advertised as MYC 162 io during the initial part of the clock interval i _{4 is} "true", therefore the flip-flops 81 bis 90 that is blocked. This output signal is used as one of the input registers 51, in correspondence with the output signals for the information input terminal binary content of bits 5 to 9 of the C register 32 of the flip-flop 125. Therefore, bits 12 to 17 of the B register 31 are always set if the output signal MYC 162 is "true" F i g. 8 illustrated by the positively increasing counter 33 (FIG. 1) causing its contents on curve 154.

the parallel adder 38 to transmit. The Purpose Assume that the comparison of the

this measure is 'when starting' the memory output signal of the lock register 51 of the data processing cycle a delay of one clock pulse time to 20 beitenden device Pl with the output signal of the Achieve so that the code number in the data processing lock register 51 of the data processing device Bending device P 2 can be blocked, the P 2 is positive. It is then from the previous priority has. This feature of the invention will be described in the description of the comparison circuit 52 described in detail below. . F i g. 6 understandable that in this case the NAND

In order to comply with the new teachings of the present invention, 25 gate 116 provides a "false" output signal which is indicated by OLKR in FIG. 6 after a large number of data processors. This signal devices is blocked in such a way that, at a given time, the reset circuit 53 (FIG. 5) only has one data processing device carrying out an item to clear the flip-flops 81 to 90. Bringing the shared data up to date, clearing the flip-flops has resulted in the clearing of the code number being able to make it more understandable, will result in the 30 that was previously stored in it. The F i g. 8 and 9, the timing diagrams depicting the "false" output signal OLKR of the NAND gate useful in explaining the 116 is previously described in FIG. 8 by the positive pulse 155 blocking functions. In the F i g. 8 and 9 designated.

lines 141 to 148 denote the beginning of How from FIG. 8, the comparative

Clock intervals J ₁ to i ₈ . These clock intervals are 35 ready signal CEl, which is defined by the curve 153 X by clock pulses generated by the clock. is reproduced, generated by the decoder at the beginning 35 (see FIG. 1) in a known manner. the clock period f _{3 is} generated. This signal will then

It is assumed that before time I ₁ the device P1 processing the data to the NAND gate 122 of the program control unit, which is supplied to 40 in FIG. 3, is initiated. During the period t ₃ , namely before executing the shown subroutine. As a result 40 the code number in the lock register 51 is locked, so that at the beginning of the time ^ ₁ (line 141) the data processing device Pl that is to be compared in the comparison circuit 52 and the signal OLKR at address W is "true" . Accordingly, the existing command word are to be requested. This request two input signals of the NAND gate 122 becomes "true" on the memory unit 20 during (FIG. 7), and as a result its off period t _{2 is} transmitted, as indicated by the positive 45 output signal "false". Therefore, the output signal rising curve 151 is displayed, so that at the NAND gate 123, which works as an OR gate at the beginning of the clock interval / ₃ (line 143) the instruction is "true", which has the consequence that at the beginning word from the address W to the buffer register and the clock interval t _a, a program control signal is transferred to the command register from PI, as MYC 161 is generated. This signal is represented in FIG. 8 by the positively rising curve 152, which is represented by a positively rising pulse 156. The content of bits 0 to 4 and 9, 10 and 11 are set. As can be seen from Fig. 7, the signal of the command word is, as previously described, fed to the flip-flops 124 and 125 on MYC 161, so the C register 32 is transferred and from this that at the beginning of the next clock interval i ₄ , the decoder 34 to decode the content. through the line. 144 is displayed, the two FHp-As can be seen from Fig. 3, the code in these 55 represents flops to be set. The function of the flip-flop bit is a lock code number contained in the field labeled N 124 to identify flip-flop 39 (Fig. 1). Therefore, we start adding the value +1 to the parallel adder 38 at a point during the clock interval t _{3 of} the. This function will deliver the lock code signal in FIG. 8 to decoder 34, which was indicated above by the positive rising pulse 157, designated MYC29. This locking code 60 continues the function of the flip-flop 125 signal is shown in FIG. 8 by the positive pulse 153 in it, the program counter 33 reproduces a control signal. . to feed its content to the parallel adder 38

As can be seen from Fig. 5, the lock code is supplied. This function is shown in Fig. 8 by signal MYC29 to each of the NAND gates 71 to 80, the positive rising pulse 158 is applied, so that at the beginning of the next clock interval 65 As an effect of the .Program control signal MYC 161 valls /, (line 144) the content of bits 5 to 8 of the is supplied to the NAND gates 71 to 80 during the clock interval t _t, the content of C register 32 and bits 12 to 17 of the B register of the program counter 33 and an additional value stM 31 - | -1 is transferred to the parallel adder 38.

This process takes place independently of the comparison of the code number in the lock register

51 is stored and is compared in the comparison circuit 52. The technique of controlling the transfer of the contents of a register to a parallel adder as well as adding values such as e.g. B. +1 to the adder to augment the contents of the program register is well known in the art and therefore need not be described in detail here. At the beginning of the clock interval t _s , the content of the parallel adder, which now represents the previous content of the program counter 33 plus the value +1, is transferred back to the program counter, as shown in FIG. 8 is indicated by the level change 159, so that during the beginning of a following clock interval, such as. B. t ₆ , the next command word, ie W + 1, is requested in accordance with the content of the program counter 33.

When the instruction word is at address W stored + 1, is received by the data-processing device Pl and decoded, it shows, as shown in FIG. 4 can be seen in that a transfer instruction to the address is to effect the retransmission W, which further causes that the locking code number command to be stored or the locking code number C _{0 is} repeated. The code number is again stored in a lock register 51, and a comparison is then carried out. If the memory register of any other data processing device, such as data processing device P2, stores a code number C ₀ , a positive comparison, as represented by pulse 155 in FIG Device Pl the following command word is received from address W + 1. It is apparent to a person skilled in the art that the data processing device P1 remains blocked in a certain sense and processes the command words at the addresses W ₃ -WfI, W, W + 1, etc. one after the other. This is because the data processing device is prevented from proceeding to receive the next command word from the address W + 2 , which is a command to transfer an item of common data stored at the address X to the data processing device P1.

It is now shown on FIG. 9, in which elements that are the same as elements in the previous figures are denoted by the same reference numerals. For the purpose of explanation it is assumed that after the blocking or writing of the code number C ₀ in the blocking register 51 is blocked and the comparison is carried out in the comparison circuit

52 a negative comparison signal is generated, which is indicated by the dashed line 155./! is reproduced and indicates that none of the lock registers of the other data processing devices contain a code number which is the same as the code number C ₀ stored in the lock register 51 of P1. Then it will be understood from the foregoing that the output signal of the NAND gate 116 (Fig. 6) is "true". The signal OLKR at the end of the comparison period is namely "true". If so, the NAND gate 122 (Fig. 7) is again energized with two "true" inputs so that its output is "false", resulting in a positive program control signal MYC 161 which is generated by the NAND gate 123 is generated. The last-mentioned signal is shown in FIG. 9 represented by the pulse 156 A.

The additional program control signal MYC 161 acts again on the flip-flops 124 and 125, which cause the flip-flop 39 or the program counter 33 to transfer their content to the parallel adder 38. While in the clock interval Z ₄ the flip-flop 39 supplies the parallel adder with the value f 1, which after adding to the content of the

ίο program counter 33, which represents the value of the address W , leads to a total output signal of the parallel adder W + 1 , therefore, because of the additional program control signal MYC 161, which is represented by the pulse 156vl, the FHpflop 39 provides an additional value + 1, which is represented by the pulse 157 A , so that the addition in the parallel adder 38 at the end of the clock interval t. gives the total value W + 2. This total value, illustrated by the pulse 159.4

ao is light, is transferred to the program counter 33 at the beginning of the time interval t ₆ , so that the command word from the address W + 2 is requested by the data processing device at the beginning of a subsequent clock interval.

As can be seen from Fig. 3, the command word present at address W + 2 represents a command for transferring or inputting the item of common data stored at address X to the data processing device. Therefore the item of common data is transferred to the data processing device and, similarly, each subsequent command word stored at one of the addresses W + 3 to W + 5 is fed to the data processing device until the subroutine is completed Command word in address W + 5 is a release command for the lock register. This results from code 14 in bits O to 4 and from the O code in bits 9 to 11 of the command word and O, are fed to the decoder 34 via the command register 32, the decoder delivers a "false" enable signal OMYC 30 on an output line 63, which excites the NAND gate 53, operating as an OR gate, to a "true" output ssignal and thereby all flip-flops 81 to 90 of the lock register 51 (Fig. 5) to delete. The data processing device is then ready to start another subroutine that is to be executed by it.

It will be understood from the foregoing description that if in any subsequent subroutine that is to be executed by the data processing device, one of the Command words of this subroutine have a common data item on the data processing device should be transmitted so that this data is processed and brought up to date, this special command word can be preceded by two command words that block the code number, the such Data is assigned to control in the data processing device. One of them can be the lock order for the code number, such as B. the first word in Figures 3 and 4, and the other may be the retransmission command represent, such as B. the one in the second line of FIG. Word shown 3 and 4. To a comparison is made to the locking of the code of the special item of common data. When a positive comparison signal is generated.

19 20

d. That is, if another of the data processing level has access to the memory. For the better

rate has this code number in its lock register, understanding the technique used to do that

the data processing device becomes the next priority data processing device

fail over, which is the back-over-empowering to first post the common data post.

order will act. If, however, no calls are made, the system reverts to FIG. 7 and 8

nem of the other data processing devices that pointed and pay special attention to the

special code number is blocked, a negative three lower lines of FIG.

tive comparison generated signal that, how clarify the operation of the program control unit

As described above, the program control unit 40 40 serve in that data processing device,

(Fig. 1) excited in such a way that two on- io that is not the priority or a lower degree of

consecutive values +1 from the flip-flop 39 has priority. As shown in FIG. 7 shows that

are fed to the parallel adder 38, so that NAND gate 132 has an input signal OFO 7 which,

the command stored at the next address as previously explained in the data processing device

word is skipped and the data processing with the lower priority level is "true". Continue-

Device continues with the next command word - 15 another input signal of the NAND

can take the command for the transmission of gate 132 from the output signal of the NAND

of the entry of common data on the device gate 128, which acts as a negator for its from

contains. the comparison circuit 52 supplied input

Although it was previously assumed that signal OLKR always works. As before in connection with

then when a common data item is written to the 20 of Figs. 8 and 9, the signal causes

data processing device is to be transmitted, CEl that the program counter 33 to its content

he transmits command words for blocking the parallel adder 38 assigned to him, as the im-

Code in the data processing device fore-pulse 158 indicates.

go, it goes without saying that the arithmetic program If the two data processing devices subroutines for the transmission of items simultaneously try to store or block the same code number regardless of the fact, the output signal OLKR is that other data processing devices precisely these of the comparison circuit, as described above, can process and contain data, that is, subpro- "false". As a result, the output of the gram to bypass latch inverter 128 (FIG. 7) is "true". Also in the date. It is sufficient if these subroutines are the processing device, which does not have priority, is the wrong word, which refers to the code numbers of such data - signal OFO 7 is also "true" and is therefore not included. output signal of the NAND operating as an AND gate

There is a possibility that two data processing gates 132 are "false". Because the output signal of the processing devices, such as P1 and P2, are simultaneously fed to gate 132 as an input signal to a NAND gate, two subroutines such as the one that operates as an OR gate, which are shown in FIGS Figures 3 and 4 illustrate the output of gate 134 being two. This is because the device P1 can generate a command word of the program control signal MYC 162, "true", request from the address W at the same time if the output of the gate 132 is "false". As the device P2 uses the command word from FIG. 7, the second control signal AdresseZ is requested. As the information input of the flip-flop clear from FIGS. 3 and 4 ER- 40 MYC 162, the instruction words on the two addressed 125 are supplied as so that when the second Steuersen (W and Z) are the same. The two data processing signal MYC 162 is present, the flip-flop 125 devices will simultaneously try to set one and the program counter 33 causes code number C _D in their corresponding lock register to lock its contents back to the parallel adder 51 . As a result, the 45 38 transfer will take place. This additional transmission is equalization circuit 52 of each of the two data processing devices, which result in a positive comparison signal in FIG. 9 due to the positive pulse 158.4. indicates.

which, as previously described, every data processing device is caused to advise the next one, which has priority, the signal OFO 7 "false", command word at the next address of its corresponding 5 "and it will Therefore, to proceed in this device during the corresponding subroutine, at the time interval f ₅ the content of the program counter 33 is a retransmission instruction not transferred back to the parallel adder- (see the second lines of FIGS. 3 and 4) The return, so that the content of the parallel adder in transmission will again cause the two data processing devices having the priority during the device to move simultaneously to the first 55 clock interval f ₅ to the program counter 33 via the command word in each subroutine react, will carry to this device at the beginning of the clock, which is a blocking command for the code number. So interval / _e can enable the next e Command word to request the two data processing devices in one. In the data processing device, the closed loop in which it does not have priority, the transmission causes each other only to process the first and second instruction ^{60 of} the contents of the program counter 33 to the corresponding subroutines. allele adder 38 during clock interval i ₅ , the

To prevent such an inhibition from being illustrated in FIG. 4 by pulse 158 B , one

a closed loop occurs, the invention sees a time delay of one clock interval. Consequently

dung additional circuitry before, which may have a which the data processing device that is not the priority having data processing unit loading has ⁶ 5 priority, until the beginning of the next Taktfähigt to call the memory and a post overall interval / _7, by the Line 147 is shown to process common data before a data request the next command word,

processing device with a lower priority - From the above it can be seen

that the data processing device having the priority is able to request the next command word at the beginning of the clock interval f ₆ , while the data processing device that does not have the priority is delayed by one clock interval and the next command word only at the beginning of the following clock interval. valls f ₇ can request. Such an arrangement prevents the two data processing devices from remaining locked in a closed loop arrangement. It enables the primary data processing device to request the next command word before the data processing device with the lower priority level can request. Therefore, the primary device is able to block the code number assigned to the post of common data and to process this data. On the other hand, the data-processing device which has the lower priority level must wait until the higher-priority device has finished processing the item of common data and returns this item to the memory. Let it be B. assumed that the data processing device P1 has a higher degree of priority than the data processing device P 2 and that the two data processing devices simultaneously with the execution of the F i g. 3 and 4 begin. It is then understood from the foregoing that the data processing device P1 will be the first to receive the item of common data present at address X in order to update it by adding a "1". Only after the updated item of common data has been returned to the memory and the lock register 51 of the data processing device P1 has been released in accordance with the command word stored at address W + 5, the data processing device can P 2 receives the updated item of common data from address X in order to subtract the number "2" from it according to the command word stored at address Z + 3 (see FIG. 4).

Briefly summarized, it can be seen from the foregoing description that, in accordance with the teachings of the present invention, a plurality of data processing devices P1 and P 2 are interlocked so that at any one time an item of common data contained in memory unit 20 is closed which each of the data processing devices has access, can only be updated or processed by one of these data processing devices. If a data processing device needs the shared data to execute a subroutine with them while another of the data processing devices is working with this common data, this later data processing device is prevented from continuing its subroutine until the other data processing device is up to date Has brought back the item of common data that has been brought back into the storage unit. The determination of which of the data processing devices is processing an item of common data and brings it up to date is made possible by the fact that each item of common data in an operating system is assigned a code number which is transmitted to the data processing device and stored in its lock register before this item of common data is fed to the data processing device. A comparison is then made in which the contents of all lock registers are compared to be sure that none of the lock registers of the other data processing devices contain the code number of interest, thereby indicating that none of the other data processing devices have the item in common Data processed.

Reference is now made to FIG. 10 to explain a NAND gate which can be used in the system according to the invention. Several input terminals 210 and 212 are connected via the cathode-anode paths of corresponding diodes 214 and 216 to the conductor 220 , which in turn is connected via a resistor 122 to a +15 volt terminal 224 . The conductor 220 is also connected to a conductor 228 via a resistor 226 and this conductor is connected to a -15 volt terminal 232 via a resistor 230 . Conductor 228 is also connected to the base of an NPN transistor 234 , the emitter of which is connected to ground and

as whose collector is connected to a +5 volt terminal 238 via a resistor 236. A capacitor 240 may be connected in parallel with resistor 226 to decrease the rise time of the transistor when it is driven into the conductive state. An output terminal 242 of the gate is connected to the collector of transistor 234 .

During operation caused a "false" signal from

0 volts applied to either or both input terminals 210 and 212 causes current to flow from terminal 224 through resistor 222 and through one or both of the diodes so that transistor 234 is maintained in a non-conductive state. Therefore is at the output terminal 242

■ a +5 VoIt or “true” signal. However, if both of the inputs to input terminals 210 and 212 are "true" or at 5VoIt, diodes 214 and 216 will be biased so that they will no longer conduct and a positive voltage will be maintained at the base of transistor 234 . The transistor is therefore switched to the conductive state, so that essentially OVoIt or a "false" signal is present at the output terminal 242 . The NAND gate of Fig. 10 acts as an AND gate because it provides a "false" output signal only when all input signals change from the "false" level to the "true" level.

If the signals at all input terminals are normally held at the "true" level in order to generate a "false" signal at output terminal 234 , the gate acts as an OR gate because the gate at output terminal 242 has a ■ » delivers true "signal if only one of the input signals assumes the" false "level. If the gate acts as an inverter for an input signal changing in the positive direction, ie if the output terminal is normally at the "true" level, all unused input terminals of the gate according to FIG. 10 can be connected to 4-5 volts. The input signal applied to the only active input terminal then causes the output signal at output terminal 242 to be "false". This operation of the NAND gate

according to Fig. 10 is the same as that which executes it, if it works as an AND gate, apart from the fact that only one of the Input terminals is used as the active input terminal.

When the NAND gate of FIG. 10 acts as an negator for an input signal changing in the negative direction, with its output signal normally being "false", all unused input terminals are connected to a +5 volt level, and the only active input terminal going to the "false" level causes the output to go "true", which is similar to the operation of the gate when used as an OR gate. Depending on whether the gate according to FIG. 10 normally has a "true" output or a "false" output, the symbols used in the illustrated system are accordingly those of an AND function (a gate symbol with a straight input edge) or an OR function (a gate symbol with a concave entrance edge). Those NAND gates that work as AND gates are also denoted by the letter N with the index A (N _A ) , while those NAND gates that work as OR gates are denoted by the letter N with the index O ( N ₀ ) are designated. The NAND gates, which work as inverters, are denoted by an N with the index 1 (N ₁ ) . It is understood that the NAND gate of FIG. 10 can have any number of input terminals, although only two inputs are shown in FIG. Further, it should be understood that the gate shown in Figure 10 is shown for purposes of explanation only and that any other gate circuit capable of performing the AND, OR and invert functions may be used.

A flip-flop which can be used in the system according to the invention will now be described with reference to FIG. It comprises two NAND gates 246 and 248 which function as OR gates. The output terminal of gate 246 is connected both to the "false" output terminal 249 of the flip-flop and to an input terminal of gate 248 . The output terminal of the gate 248 is connected to the "true" output terminal 250 of the flip-flop and also to an input terminal of the gate 246 . The flipping of gates 246 and 248 is controlled by NAND gates 252 and 254 , which act as OR gates and are connected to input terminals of the corresponding NAND gates 246 and 248 via delay lines 256 and 258, respectively. The output terminal of NAND gate 252 is connected to an input terminal of NAND gate 254 by conductors 259 and 260 .

The gates 252 and 254 are supplied with clock pulses at a terminal 262 and control pulses C at a terminal 264. The information inputs / are provided to gate 252 through conductors such as 266 and 268 . A capacitor 270 is connected between ground and an input terminal of gate 254 in order to produce a time shift between the information signals fed to conductor 260 and the clock signal. Unused input terminals of gate 252 are tied to the "true" or constant +5 volt level.

The flip-flop of Fig. 11 operates with informational input signals / on conductors such as 266 and 268 which are normally "true" so that when clock and control signals are present, the signal on conductor 260 is "false". The information input ladder, such as 266 and 268, in the absence of a coincidence condition on NAND gates (not shown) coupled to them, are normally at the "true" level. The signal on

ίο the conductor 259 is always "true", except at the clock time at which it becomes "false" in order to set the flip-flop to the "false" state when all information input signals and also the control signal or the control input pulse are "true" .

However, if any of the input signals is "false" at clock time, the signal on conductor 259 is "true" and the flip-flop is set to the "true" state or remains in the "true" state.

If z. B. the flip-flop is in the "false" state

ao and a "true" or +5 volt level at terminal 249 , the input signals of gate 248 are both "true", so that gate 246 receives a "false" signal from terminal 250 together with the ' normally the "true" signal is supplied on conductor 259. If any of the information input signals on conductors such as 266 and 268 are "false" at clock time, the signal on conductor 259 will remain "true". As a result, a "false" signal is generated by gate 254 , so that gate 248 provides a "true" output signal. Gate 246 therefore forms a "false" signal which causes gate 248 to continue to deliver a "true" signal. The signal on conductor 259 remains "true" after the clock time, so a "false" output is maintained by gate 246 and a "true" output is maintained by gate 248 so that a stable "one" is maintained. or the "set" state of the flip-flop results. The flip-flop works the same way when it does

had previously stored a "true" state and the information and control signals at the clock time are all "true" in order to bring the gate 246 into a state in which it supplies a positive or "true" output signal, which corresponds to a stored " Corresponds to zero "or the" deleted "state. The delay lines 256 and 258 cause a delay in the input signals, so that the information can be interrogated in a reliable manner from the terminals 249 and 250 at the beginning of the clock period and new information can be written into the flip-flop during the same clock period. It should be noted that the signal at control input terminal 264 must be "true" at clock time for the flip-flop to change state.

55 'If the signal at control input terminal 264 is "false" at clock time, the flip-flop remains disabled in its previous state because the signal on conductor 259 remains "true" and so does the signal generated by gate 254 the "true" level remains. Further, when the signal is held, or at the control input terminal 264 on the "true" level brought to this level, the flip-flop at clock time in the "wrong" state is brought (deleted), where it acts as Vcrzögerungs flip-flop when all Information input signals are at the "true" level.

Reference is now made to Figure 12 which is a block diagram shows one of the Gattcran orders,

209643 / ΊΠ

like ζ. B. the gate 101 shown in Fig. 6, the complement of the exclusive OR function of two input signals LOlA and LOlB . Fig. 13 is a function table for the exclusive OR function and its complement of two input signals. The exclusive OR function is denoted by Θ , while its complement is denoted by Θ. As can be seen from Fig. 13, the output signal of a gate circuit which provides the complement of an exclusive OR function is only a "one" or "true" if its two input signals are the same, ie if either both input signals are "zeros" or Are "false" or if both input signals are "ones" or "true".

In the present invention, the input signal LOIA of the gate circuit 101 is the "true" output signal of the flip-flop 81 of the lock register 51 of the data processing device P1, while the output signal LOIB is the output signal of the flip-flop 81 of the lock register 51 of the data processing device P 2 . The input signal LOIA is fed directly as an input to a NAND gate 301 which acts as an OR gate and a NAND gate 302 which acts as an inverter. The output signal of the NAND gate 302 is fed as an input signal to a NAND gate 303, which operates as an OR gate. Correspondingly, the input signal LOIS is fed to the other input of the NAND gate 303 and to a NAND gate 304, which operates as an inverter and whose output signal is fed to the NAND gate 301 as a second input signal. The outputs of gates 301 and 303 are connected together at a point 305 which is connected by line 306 to one of the inputs of NAND gate 112 (FIG. 6) which forms part of the comparison circuit discussed above.

From the above it can be seen that if the two signals LOIA and LOIB are the same, regardless of whether "true" or "false", the negation of the NAND gates 302 and 304 results in an input signal of each of the gates 301 and 303 being "false" is. Therefore, each of gates 301 and 303 provides a "true" output so that the signal at junction 305 is "true". However, if LOIA differs from LOIB, the input of either gate 301 or 303 is "true" and therefore the output of that gate is "false". Thereafter, point 305 is at the "false" level which is then fed to NAND gate 112 (FIG. 6) and causes gate 112 to provide a "true" output indicating that at least one of the flip-flops 81 to 90 stores a bit in the lock register 51 which differs from the bit which is stored in the corresponding flip-flop of the lock register of the other data processing device. Only if all the properties of the NAND gate 112 (FIG. 6) are "true" does the gate supply a "false" output signal, which indicates that the code in register 51 of a data processing device supplies a positive comparison with the code, which is stored in the lock register of the other data processing device.

Briefly summarized, the invention creates a locked data-processing multiple system in which each data-processing device has access to a common memory unit in order to connect with it for the execution of various subroutines. Some of these subroutines may include command words such as B. the words that are stored at addresses W + 2 and Z + 2 (Fig. 3 and 4), which cause each data processing device to be an item of common data D, such as. B. the item stored at address X , to bring this item up to date.

ίο In order to prevent more than one data processing device from bringing the common data D up to date at the same time, each subroutine contains two command words, the. precede the command to transfer the common data D to the data processing device. One word commands the data processing device to block a code C ₀ , which is assigned to the data D , while the following word commands the data processing device to return to the address.

ao to be transmitted on which the code is stored. These command words are used together with the locking circuit in each data processing device to ensure that at any time the code C ₀ can only be locked in the lock register of one of the data processing devices, so that only this data processing device call the memory unit receive common data D and update it as part of the execution of its subroutine. At the end of the subroutine, the updated common data are saved again in their address, and the lock register is cleared in order to enable any other data processing device to lock the code C ₀ in its memory register and in the continue to receive the updated common data and complete its own subroutine.

To explain the connection between several data processing devices, such as P1 and P 2 and the memory unit 20, refer to the simplified circuit diagram according to FIG. 14 referenced. In the illustrated system, the memory unit 20 comprises two memory banks 20 ^ 4 and 20B, each of which contains an address register 22, a memory 21 and a data register 23. The letters Λ and B are each of the elements of the banks 2OA and 20 B mutatis mutandis assigned. In addition, each bank contains a selection circuit 24, a control circuit 25 and a data selection stage 26. The function of the latter stage is to connect the data register 23 to a plurality of data lines 351 to 354. The lines 351 and 352 are used to connect the data processing device P1 to the data selection stages. The line 351 is used to feed data from the data processing device P1 via the data selection stage 26 to the data register 23 so that they are stored in the memory 21. So z. B. updated data of an item of common data is transferred to the memory via line 351. On the other hand, the line 352 is used to transfer data from the memory to the data processing device P1. Correspondingly, the lines 353 and 354 are used to receive data from a data processing device P 2 and to transmit data to this device. Lines 356 to 359 are also used for

27 28

det, the data processing devices Pl and P 2 with can. The lines 356 and 358, via the

the selection circuit 24 and the address register 22 signals have been supplied to the selection circuits 24,

of each of the memory banks 2 <L4 and 20 B can comprise more than one conductor, so that the

tie. Lines 356 and 357 will be supplied with one or more bits for this purpose.

used, signals from the data processing 5 den can to the called up memory bank

Feed device P1 while the lines 358 control. For example, the selection circuit 24

and 359 can be used to convert signals from the to 1 or 2 bits of a complete 15 bit.

data processing device P 2 feed. address full address word in order to

As in Fig. 14, a request becomes the target memory bank to which the request is directed

to the memory of Pl as a signal on the line io is to be selected. For this purpose, the address

356 while the memory location or the sensor register of the memory bank called up is being

Address of the information to be processed by the. The data selection stage 26 of each memory bank can

agile device Pl is desired or which on the comprise a variety of gates that of the

Memory is to be transferred, on line 357 control circuit 25 is controlled in such a way that

is fed. The last signals are also sent to the 15 that data from each of the memory banks (2OA,

Address register 22 supplied. In corresponding 20B) on each of the data processing devices Pl

Lines 358 and 359 are supplied to this and P 2 as well as from each of the data processing units

applies, which transmit the signals from the data processing device to each of the two memory banks

To feed device P 2, the signals on the line can be.

processing 358 a request to the memory from the ao The special gate arrangements for controlling

display data processing device P 2 and the access of a variety of data processing

Signals on line 359 the called devices address to one or more memory banks

describe. The selector circuit is with the control are not shown because how. for the professional

circuit 25 connected to provide access to the can be seen the implementation of these arrangements of

Memory bank and the correct transfer depends on the 45 specific purpose. It ver

formations from either. the data processor is also aware that any of the opposing

Device to the memory or from the memory to currently known gate and signal control techniques

to control the data processing device. can be used to provide the necessary

The data lines 351 to 354 and the address links are used to create a large number of

Lines 357 and 359 comprise a plurality of data processing devices with the memory unit

individual conductors, so that 20 comprising several bits can be connected which, as previously described,

Words or data as well as multi-bit benches, one or more memory banks

Addresses can be fed through these lines.

See S sheet drawings

Claims (4)

Patent claims: 1. Data processing multiple system in which a large number of data processing devices Has access to a storage unit to items identified by codes stored therein common data to be processed, with registers for storing the codes and comparison circuits for deriving signals controlling the processing of the stored data, thereby characterized in that in each of the data processing devices (Pl and P 2) a register (51) and a comparison circuit (52) are provided that the comparison circuit (52) of each device (e.g. Pl) the code entered in the assigned register (51) with the Compares codes that are in the registers (51) of the other data processing devices (e.g. P2) are included, and a comparison signal is generated which assumes a certain value when in the register (51) of another data processing device (P 2) already contain the same code is, and that in each of the data processing devices (P1 and P 2) means for program control (40) are provided which are based on the comparison signal generated in the respective device (P 1) address and the transfer of the post of common data by the in the register (51) of this device (Pl) entered code is identified from the memory unit (20) lock the device (Pl) when the comparison signal has the specific value, so that to at any time only one of the data processing devices (Pl or P2) one through a certain one Is able to process items of common data marked with a code. 2. System according to claim 1, characterized in that the register is formed by a lock register (51) for storing the code, that the comparison circuit (52) supplies a first comparison signal when the code that is in the lock register ( 51) is different from the codes stored in the lock registers (51) of the other data processing devices, and a second comparison signal if the code stored in the lock register (51) with the Code matches which is contained in the lock register (51) of another data processing device, and that the means for program control (40) on the first comparison signal transmit the item of common data to the data processing device (P1 or P2) and to the second comparison signal prevent the transmission of an item of common data to the data processing device (Pl or Pl). 3. Installation according to claim 2, characterized in that the means for program control (40) a reset circuit (53), responsive to the second comparison signal, to the To delete lock register (51) in the clatenveraibeilenden device (PI or P 2), and from the Storage unit (20) requests a retransmission command to the data processing device (Pl or P 2) to cause the code of the Rewrite item of common data in the lock register (51) so that he can use it again the codes in the lock registers (51) of the other data processing devices (P 2 or Pl) is compared until none of the lock registers of the other data processing Device contains the same code anymore. 4. Installation according to claim 2 or 3, characterized in that in each data processing device (Pl or P 2) in response to a code lock command which is stored in the memory unit (20) at a first address (W) , a decoder (34) and storage means store the code of the item of common data, which is contained in the code lock instruction, that the means for program control (40) in each data processing device (P1 or P 2) respond to the first comparison signal to determine the corresponding to cause the data processing device to skip a retransmission command stored at a second address (W + 1) and a. To request a transfer command from a third address (W + 2), and that the means for program control (40) continue to respond to the second comparison signal in order to cause the corresponding data processing device (P 1 or P2) to use the second address (W + 1) request stored retransmission command.