DE1499226A1 - Device for testing the central unit of an electronic data processing system - Google Patents

Description

IBM Germany Internationale Büro-Maschinen Gesellsthaft mbH

Applicant in:

B öblingen on July 8, 1969 jo-sp

International Business Machines Corporation, Armonk, N.Y. 10 504

Official file number:

Applicant's file number:

Docket 7815

Device for testing the central unit of an electronic data processing system

The invention relates to a device for testing the central unit an electronic data processing system using a test program.

Because of the very complex structure of modern data processing systems it is desirable to have an automatic program controlled in any such system Provide test equipment that is able to locate defective components and circuits.

The problem here, however, is to look for such solutions, which do not add to the overall cost of the system. the Construction of such testing facilities, which are not too expensive in terms of cost is particularly difficult in systems that use read-only memories for microprogram control.

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»4 detailed documents (Art. 7 § t Paragraph, a No. ι ss

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U99226

In the previously known test devices, the control signal sequences only by a comparison with the output signals an equal and double existing read-only memory can be checked. Have these solutions the disadvantage that they are due to a duplicate read-only memory are too expensive and uneconomical.

It is therefore the object of the invention to overcome this disadvantage of the known test devices to avoid.

For a device for testing the central unit of an electronic data processing system By means of a test program, the invention consists in that control and transmission units for mutual connection the read / write memory and the read-only memory of the system as Microprogram sources are arranged on the test circuits.

An advantageous further development of the device according to the invention is thereby marked that the connection of the read / write memory or. of the read-only memory to the test circuits using a switch automatically or manually.

The control and transmission units for the test device are characterized by a test subgroup decoder, which can be switched to control signals from the read / write memory or the read-only memory by means of a monitoring switch and, depending on these control signals, selects certain control lines. Bad testing of groups of signals consisting of several bits, which can be fed in via a data bus, consisting of AND circuits for the selective generation of signals for switching over a single-stage binary counter and an AND circuit for the generation of signals for resetting the binary counter to a predetermined one Position which is connected to an AND circuit for the transmission of a branch signal for address control of the read / write memory. Dockat7815 - 009828 / 13B1 «WHERE ORIGINAL

System test facilities generally require extensive repetition of operations which, in the broadest sense, as scanning operations, Comparison operations, branch operations and end or output operations are designated. In a key-in operation, the information entered into the elements of the system that are to be checked. These elements process the information and their results are compared with the results of the test facility supervised.

With the proper functioning of a monitored machine part a branch signal is derived, which is either the next / test oper ation or generates a stop signal in the event of an error and thus Allows conclusions to be drawn about the faulty component of the machine.

The advantages of the invention are now in data processing systems with a read-only memory for the microprogram control in the central unit not as usual to provide this memory twice, what a represents an uneconomical solution, but these tests with the help of the The main memory of the system. This also makes it possible to To make preliminary tests and tests on the type of use of the computer system, since the switching of the test circuits, which is normally done with the read-only memory are connected to the main memory with the help of simple gates is made possible.

In the following the invention is explained with reference to a drawing Embodiments described in more detail. Show it:

1 shows the block diagram of the test device according to the invention.

ORIGINAL

Docket 7815 009828/1351

Fig. 2 elite schematic representation to illustrate the Connections between the test equipment and the read / write memory,

Hg. Z a representation of the read-only memory, in its place, the read / write memory alternately for the test ope

rations can be used,

4 shows the block diagram of the test subgroup decoder, FIG. 5 shows the block diagram of the test circuit,

6 shows a timing diagram for the operational sequence of the reading /

Write memory in connection with the operational sequence of the read-only memory and

7a - tables for explaining the operational sequence. 10

GENERAL DESCRIPTION

As is apparent from Fig. 1, the data processing system comprises according to In the present invention, an erasable universal memory and its address controls 1, computing circuits and registers 2 and a permanent one or semi-permanent sequence control unit 3 for the micro programs. Programs contained in the memory 1 are determined by the arithmetic circuits and register 2 executed according to the direction of signals received from the sequence control unit 3 through a series of decoder networks or circuits shown at 4. With the sequence controls it concerns so-called microprogram or subprogram sequencing controls, which are designed so that they sequentially in memory 1 to examine general program instructions and the execution of a control the corresponding sequence of basic or micro-operations.

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The subgroup - DocodiernctzworkQ 4 bonrboiton subgroups iodo group of micro-instruction signals and generate micro-operation control signals which directly the subsystems 1 and 2 and the transfer of information between these two subsystems are controlled. In the drawing are Information transmission paths for several bits by continuous double lines (See, for example, reference number 5), multiple gate circuits to Controlling the flow of information through each transmission path are through a single line is shown that is perpendicular to the double line and it intersects (see e.g. reference numeral 6), and lines which control information signals for controlling the information transmission gate circuits are shown by dashed lines (see e.g. reference numeral 7). The direction in which signals pass through the door circuits becomes indicated by arrows next to the line symbol for the door circuits, and a double arrow (see reference number 8) denotes a flow of information in two directions, and a simple arrow (see reference number 9) denotes a single direction of flow.

One of the subgroup decoding networks within unit 4 that is shown in Connection with this system test is of particular interest is denoted by the reference number 10. His exit, the schematic shown as a single dashed line 11 actually exists from 16 separate micro-operations. control lines that run together through the symbol OP and individually identified by the following digits 0 - 15 are. The subgroup decoder 10 receives four-bit binary signal combinations from one of two groups of input lines 12 or 13 and translates these into control signals on one of the IG lines 11. The other decoders in the Group of decoders 4 control signals assigned to individual lines Groups of output control lines beginning with the collective designation 14 "

BAD ORfGiNAl.

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Marked are. Each group of output lines bears the symbol OP and an individual trailing character j, k, 1, m, η or p.

The system of the present invention also has a test circuit 15 and a monitor switch 16. The test circuit 15 takes as an input, parallel sets of signals consisting of 36 bits via an information transmission path 17, the gate circuits 18 which are controlled by one of the output lines OP _ of the decoder 10, and they

J. O.

delivers at its output 19 a "good-bad" signal that the. Check status a variable bit indicating 36 bits transmitted over path 17. A particularly economical and effective arrangement for producing this information is described below.

The monitoring switch 16 can be brought into one of two states, namely "PermanGntfolgebotrleb" (PSM) or "Monitoring test mode" (ST] M). When the monitor 16 is in the PSM state, it supplies a control signal only on the PSM control line 20, and when, on the other hand, it is in the STM state, it supplies a signal only on the STM control line 21. The switch is brought into the STM state by signals which are supplied via automatic or manual devices represented by line 22. In the PSM state, it is reset by signals on the control line 23, which leads to the line OP _ß the group of output lines 11 of the sub-group test de encoder 10.

The decoder 10 is addressed by control information in one of the two connections 12 or 13, each consisting of four lines, depending on whether the monitoring switch 15 is in the STM or in the PSM state, as shown in the control inputs of the gate circuits 27 and 28 in the overgrowth of the compounds mentioned

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outputSDitsiel-

ex'Kohen is. Signals in transmission path 12 are output from four lea taken from the universal memory 1, and signals in the transmission path 13 come from four output bit positions of the subroutine control 3.

In the present exemplary embodiment, the transmission path 12 is connected to a parity channel of the bus 30. However, this creates a program loading problem, because it may be that the _{stored bits forming the codes for generating OP to OP 1K} do not have the correct parity ratio to the other bits in the assigned word in memory 1 and it is nevertheless desirable to store each program word when storing subject to a parity check. It is Z. B, it is necessary to provide mask words in the memory that contain an O-bit that can be changed in terms of position and 1-bits in all other bit positions. The four parity bits for such a word would therefore usually vary depending on the location of the O-bit. In order to generate a predetermined constant bit in each parity position of such a check word, a programming trick is used when storing the word with corresponding parity checks, whereby two different words are entered one after the other into the same memory location and one word with the other in the memory in an internal OR operation is linked to. achieve cancellation of parity with validly checked input bits. _s

The following example should suffice: A group of bits A = 10111111 (I) _{1 is to be} stored, whereby the 1 in brackets occupies a parity bit position. Ee is now assumed that the actual parity of 10111111 is 0 iet '(that is, the odd parity is represented by a 0). We now first save B * 10111111 (0), which maintains the correct input parity, and this is followed by the non-deleting OR operation of C * 10100000 (1), which also has the correct input parity.

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indicates, with B in an internal OR operation through the non-erasing regeneration of B while storing C. The unchecked internal The OR combination of B and C is 10111111 (1), which is the required one Group A acts. The facility for performing the internal OR link is described below. ·

In ordinary operation, the monitor switch 16 is in the PSM state, energized whereby the decoder input Tbrschaltungen 28 and the decoder input Torschaltun be switched off gene 27th In this operating mode

and

Information flows via the transmission path 30 into the ^v from the universal memory 1, with certain address storage locations being used which are determined by address information which is supplied via the transmission path 31, or by incrementally increased address information, which is determined by the counting controls described below with reference to FIG Memory 1 are delivered to be determined. The information leaving the memory 1 during PSM operation flows through one or more of the sets of gate circuits 32, 6, 34, 18 and 36, and the information arriving in the memory 1 passes through one or more of the sets of gate circuits 32 , 33, 34, 36 and 38. The information coming through the gate circuits 6 and 33 into the computing circuits 2 is processed by these computing circuits and in the opposite direction through the gate positions 33 to the main data bus line 30 or to the main address bus line 31 as required forwarded. On the other hand, the gates 36 and 37 make the channel connections to external input / output devices such as tape storage units, printing stations and the like. The storage / retrieval controls for directing the flow of such information into and out of the memory 1 are indicated generally at reference number 40. .

0 09828/1351 '& AD ORIGINAL

During operations in the STM mode, information can flow through one or more of the connection paths and 40. The paths 12, 17 and 31 carry information from the output of the memory 1 to the decoder 10, to the test circuit 14 and to the address controls of the memory 1. The path 39 passes one-touch test information either from the address controls or from the output field 41 of the sequence control 3 to the memory 1 or off «tast-P call information from the memory 1 to the address controls of the unit 3. The path 40 leads one-key test information from the registers 2 to the memory 1. It can under the control of the decoder 11, whose output signals the gate circuits in control the connection paths 39 and 40, that is, test conditions are established in the subsystems 2 and 3 and taken from them. Operations of the test circuit 15 can be interleaved with the key operations to '. ¹ good-bad "test indicators via the output 17 and address switching control signals via the _{line labeled OP '. 4.} The line OP' .. controls the gate circuit 32 leading via the input path 31 of the memory 1 to the address controls.

THE ERASABLE MEMORY AND THE PROGRAM LEADING TO IT

CHECK CONNECTIONS '·.

2 shows a more detailed representation of the structure of the memory 1 and the connections established to it during the initial program loading with fault location test programs (FLT) and during the execution of such programs under STM control. The memory 1 consists of a magnetic core memory matrix 60 (abbreviated to S) ₁ which is addressed by the information supplied by a memory address register 61 (SAR). The information coming from S and input in S is buffered in a memory data register (SDR) which has an input connection 63 to the sense amplifiers of S and an output connection 64 to the write drivers of S,

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The matrix S includes internal timing controls and connections (not here shown), which show the various phases of information processing between SDRT and the memory address locations in S in predetermined read / write cycles (R / W cycles) or predetermined write cycles (W cycles) control the excitation of the control line 66 or 67. The first half of one R / W cycle is the transfer of information from the addressed Reserved storage space in S for SDR. Send during this partial cycle the internal timing circuits of S send a reset signal to the SDR via the Control lines 68 and 69 in preparation for entering the sensed information into the SDR. After this reset signal, the timing circuits send control signals to the SDR input gate circuits 70 via not shown here Control lines to transfer the sensed output information from S to the Key in SDR. During the last half, the writing part, of an R / W cycle the internal timing controls of S control the output information of the SDR via the connecting lines 64 and write drivers (not shown here) into the addressed memory location. Except for certain Exceptions are those entered in the SDR in the second half of an R / W cycle Information identical to the information sensed during the first half of the cycle (i.e. the information in the addressed memory location is sensed non-extinguishingly).

In a write cycle initiated by a signal on control line 67. the SDR input strobe signals to the gate circuits 70 become common suppressed during the first half of the cycle, so actually in the first Half of the cycle no sensing takes place in S while information about the Iber circuits 36A and input bus 72 are input to the SDR will. "During the second half of the cycle, information from the SDR via the connecting line 64 in S instead of the one previously addressed in the Space available information entered. So a W cycle is the same

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an R / W cycle with the exception that those in the second half of the cycle are off The information transmitted to the SDR to S generally has no relationship to the information previously stored.

As already mentioned, the sampling signals to the gate circuits 70 are usually suppressed during W cycles. An exception is the entry of FLT program information checked for parity, in which the parity bits have to be changed by an internal OR operation. In such operations, the information is entered combinatorially in two W-cycles, the first of which is an ordinary W-cycle with gates 70 not actuated. In the second W cycle, the sampling of the gate circuits 70 is not suppressed in the first half of the cycle, and therefore the information entered from S into the SDR is linked in an OR form with the information received from the input bus * f2, which has been checked for parity. whereby the desired word with incorrect parity is entered in S during the second half of the cycle.

Part of the internal cycle time controls of S is under reference number 75

GS

shown. This part is a four-state counting circuit and relatively exclusive outputs via four lines shown at 76, which divides each cycle into four different equal parts or sections. Two of these sections coincide with the sense half a memory cycle and the other two sections with the write or Regeneration half of a cycle together. In STM operation, the gate circuits 77 are energized and they generate control signals on the lines I, IL III and IV, the functions of which are discussed below.

In addition to the input bus 72, the SDR has an input bus (Input connection) 80 to a single-key trunk line 81 via the gate switch

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schaltmigcn 82 as well as an output collector line (output connection) externally Output devices on the gates 3GB. More output links of the SDR lead to the test dialing 15 via the gate switches 18, to the test subgroup decoder 10 via the gate circuits 27, to a blanking bus 83 via the gate circuits 84 to the address bus 85 via the gate circuits 32 and to the output busbar and arithmetic circuits 2 via the gate circuits 6.

The gate circuits 32 either route address information to the SAR register 61 via the gates 86 or to an instruction address register 87 (also IAR genaint) about the gate circuits 88. The information in the IAR are usually used during program execution for addressing to be controlled by program commands! The output of the IAR is optional- " wise with the inputs of SAR and IAR via a partial value adding circuit 89 (IA) and the gate circuits 90, 86 and 88 in connection. Information will be stored in S in word units of 36 bits each, four of which are parity bits which are in a predetermined relationship to corresponding byte subsets (1 byte = 8 bits) of the other 32 bits. The addresses in SAR are usually 20 bits long and mark the beginning of each full word (36 bits) and half word (18 bits) groups of cells in S. Each time S is accessed, information is extracted and regenerated, or information is recorded for the first time, either at a VpIl or a tag boundary kick off. The storage capacity of the SDR and the ability of the input and output buses leading to it to handle parallel Signals is 36 bits.

The circuit 89 can optionally be operated in order to add a byte address count 0, 2 or 4 to the output information of the IAR and thereby the command address by a corresponding number of 0, 1/2 or 1 word limit.

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i ti

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units to increase. Of the increment controls assigned to partial value adder 89, only the one for incrementing the command count by four byte units or a word address is shown, since this is the only one that is of interest in connection with the sequence control in STM mode. This process of increasing by four units is controlled by the gates 96. These door circuits are controlled by the outputs 97 of an OR circuit 98, which combines the relatively exclusive output signals from two AND circuits 99 and 100. During the first part (I) of an STM-R / W cycle, the AND circuit 99 transmits basic clock pulses CP synchronously with the clock pulses sent to the input line 101 of the cycle counter 75 to the OR circuit 98, provided that the control line OP; _ is not energized (OP A. The AND circuit 100 transmits the clock pulses' (CP) to the OR circuit 98 in the sequence control in PSM mode, provided that a signal is present on the control line OP. *

In PSM operation, data addresses are sent to the SAR via the external gate connection 37A and gate circuits 86 or via gate circuits 86, 32 and 33 (FIG. 1). Command address information is fed to the SAR from the IAR via the gate circuits 90 and 86, with corresponding partial values being added to the command address via the gate circuits 96 or other gate circuits not shown. The IAR are instruction addresses over the Erhöhungsweg 90, 91 and 95 or via the Computerregisterweg 32, 33 or circuits or via a direct connection from the output 30 of the SRD 62 and the register of the T 32 and 95 supplied.

In the sequence control in STM mode, memory addresses are only supplied to the SAR via the gate control path 90, 86 and command addresses are supplied to the IAR either via the increment path 90, 88 or via the branch address input path 30, 32, 88 from the SDR, ^.

0098287136t.

The outputs control the Rihcnf oil control in STM or PSM operation OP to OP of the test subgroup decoder 10 a single set of. U 15

Micro-operations listed in the table of Flg. 10 are listed.

SEQUENCE CONTROLS AND COMPOUNDS PRODUCED FOR TEST PURPOSES

Referring to Fig. 3, there are the sequencing controls of the present data processing system from a control store in the form of a capacitor read-only memory matrix 120 (also referred to as ROS), which corresponds to the in address information contained in a permanent memory address register 121 (ROSAR) is addressed in the form of 12-bit words. The ROS responds to signals fed to its control input 122 with the parallel Transmission of 90 bit output signals through the gate circuits 123 in Output buffer register 124 (ROSDR for the reading memory data register).

-The embodiment described here consists of a matrix of crossed Pairs of row input drive wires and column output sense wires, at their intersections the pairs of rows can be changed with the pairs of columns by pairs of capacitive couplings, .the binary complements of each other represent, coupled, creating different binary structures of column output control signals by energizing various row driver wires to be obtained. Storage of this type are well known. The ROS contains 90 pairs of sense conductors and 2816 pairs of row lines, making 2816 control fields of 90 bits each, the so-called micro-commands, can be formed. ·.

When the ROS is energized by a signal on the connection line 122 a 90-bit signal is supplied to the gates 123. These gates

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are excited at a corresponding point in time by scanning signals, which from an internal source not shown here via the control coupling connection 125 are delivered. 84 of the 90 bits of each output signal of the ROSDR are fed to the subgroup decoders 4 via the connection 128. These branch out to the test subgroup coder path 13 and the other decoder input paths 127. Six of the ROSDR output bits will be fed via the connection 128 to an input of the address selection matrix 129, which cyclically send the next address input to the ROSAR in PSM operations selects. These six bits can be shared with six others via connection 130 bits applied to connection 131 to a 12-bit address can be combined, or all twelve bits of the address can be used over the connection. 132 are delivered. When a certain condition is met on the connecting lines 127, the decoder 4 generate a signal OP, which has six address bits on the connecting lines 130 together with six Bits aiif the connection lines 128 through the matrix 129 into the PINK forwards. Of the six bits on line 130 are four in such operations 'Microinstruction bits contained in field 127 and two are different Way Derived Branch Control Bits:,. ΤΛέηη the decoder 4 the line Selecting OP will energize gates 133 for transmission of four program instruction bits from a computer register within the block 2 of Fig. 1 via the connecting lines 131 together with the bits on the Lines 128, thereby forming ten of the twelve nearest address bits; the last two bits are zeros in this type of transmission. When occurring Upon interruption, the gates 134 are energized and provide a complete 12-bit address on lines 132 passed through the voter matrix 129 is transferred directly to the ROSAR. The selection of a next control address can thus be accomplished in one of three ways, so as to to effect required microprogram sequencing.

'. . . COPY '

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If an interruption occurs, the one previously contained in the ROSAR Address through the gates 135 to an auxiliary register (not here. ". shown) within the processing unit 2 (Fig. 1), and at the conclusion the corresponding interrupt microprogram sequence the same information from the. Auxiliary register to the ROSAR via the door circuits 136 retransmitted.

The ROSAR can also receive a 12-bit address word from another source, namely from the SDR register coupled to the erasable matrix S of FIG. 2 via the gate circuits 137. When this transmission path is energized, all other address signal paths are blocked.

The actuation of the matrix ROS is determined by signals sent by the logic Circuit 140 are generated, which from the OR circuit 141 and the two AND circuits 142 and 143, the relatively exclusive output signals generate, consists. The AND attitude 142 is carried out in the PSM operation Clock pulses CP actuated periodically, which pass through the OR circuit 141, around the ROS matrix cyclically at intervals of half a micro- “.

Second to operate. The AND circuit 143 can in the fourth section (IV) of a 2 µs cycle, optionally by an OR signal from the test subgroup decoder 10 (Fig. Ι) · can be operated. With sequence control in STM operation therefore ROS only works if OP _ from the SDR information lines 12 (Eg. 1 and 2) is selected. As through the exit branch 144 is indicated by the output of the AND circuit 143, the gate circuits 137 are activated by each output signal of the AND circuit 143 energized to receive a 12-bit address signal from the register SDR via the off. to transfer tast manifold into the ROSAR, which actuates ROS, a 90-bit signal from a ROS- designated by the SRD information. To transfer the address into the ROSDR.

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In a matrix, like ζ. B. the matrix 12O ₁ with strong capacitive external coupling between the driver and sensing lines, it is necessary to time control or sample the output signal (namely via the gate circuits 123 and the sensing connection 125) with high accuracy, - so that the sensed. Information is captured at its peak. This is not particularly difficult to achieve for every single word position in the matrix. But the 2816 output words of the matrix can occur in relatively different phases of a control cycle with regard to the rise time of the pulses CP that initiate the excitation of the matrix driver lines, due to inductive and capacitive differences in the various coupling paths To enter the position of the scanning signal so that it goes out at a relatively optimal point for all outputs and occurs at a given range of fluctuations in the supply voltage. For this reason, the occurrence time of the internal scanning signal of the ROS must be precisely set when the matrix is mounted, if the time setting is also determined by the use of the components on site and if a change has to be made to the matrix on site. With regard to the latter, it must be noted that the R ^- OS matrix has a semi-permanent modular structure and consists of several partial matrix cards or panels which are plugged together to form a complete matrix. When a panel or set of panels is exchanged for another panel or set of panels in the field, completely new coupling and limit voltage conditions are introduced into the matrix system, requiring extensive readjustment of the scan timing. ,.

In any case, setting the sampling timing requires the use of a controller located outside of the ROS system itself for the selection of the address to be examined in a certain cycle, since the addresses *

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selection matrix 129 is at least partially dependent on information in dom of the current output field generated by the ROSDR and since this is or can be of an indeterminate nature before the setting of the sampling timing. It will be shown below that with the connections controlled by the gate circuits 137 and certain other connections described in more detail below, the erasable universal memory 1 (Fig. 1) can be used in a switchable manner with the ROS system 3 to control the subgx-uppendecoder, or with micro-operation selector 10 _{4 to} generate a sequence of scan, compare, and address branching micro-operations for effective testing of any and all elements of the ROS system, including scan timing.

Five key-in connections, controlled by Tbr circuits 150-154, form subset-key connections from the ROS system to the SDR register of Figure 2 for testing of the entire ROS system. The gate circuits 150-154 are controlled by the output signals OP 'to OP _{r of the test subgroup decoder, respectively.} The key connections 150-153 connect the ROSDR to the SDR in groups of no more than 31 bits. The key-in connection 154 connects the 12-bit output of the ROSAR to the SDR. For ease of illustration, the timings of all of these key connections are shown by a single set of gate circuits 156. Although the logic circuit arrangement for this is not shown in the figure, the gate circuits 156 are actuated by the combination of one of the early clock pulses CP shown in FIG. 6 with a control signal I or PSM.

Fig. 6 illustrates the temporal relationships between the early and the late clock pulses CP and, Sections I to IV of an R / .W cycle. According to Fig. 6 begins and ends an R / W cycle of the matrix S with the beginning of a CP pulse, the R half of the cycle coincides with sections I and

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II xirid the W half together with Sections III and IV. With the exception of ÖP_, all processes caused by the output signals of the subgroup decoder in the sequence control in STM operation take place in section I of an R / W cycle. As can be seen, an early clock pulse coincides with the tail of each section and an ordinary clock pulse coincides with the beginning of each section. The values generated by OP ₇ to OP = - ', OP ₅ and OP ₇ -

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controlled processes, which are the keying operations for the transmission of paging information to the SDR, are all found during the with the early clock pulse in the section I coincident period instead, and all other operations are performed during the period coincident with the ordinary clock pulse in section I. ' The resetting of the SDR occurs before the early clock pulse in section I, '.

TEST SUBGROUP DECODER ■

As FIG. 4 shows, the decoder 10 comprises four AND circuits 27 with input connections to four digits, namely 32 - 35, of the 36 digits (O 35) of the SDR register. Positions 32 - 35 are for normal PSM operation Parity bits. Another group of four AND circuits 28 is with the four lines controlled by the output signals of the ROSDR 13 coupled. The circuits 27 and 28 are the relatively exclusive ones Controlled by the STM or PSM lines coupled to them. ■

The output signals of the circuits 27 and 28 are paired by four OR circuits 170 linked. The outputs of the latter are from one Combination of gate circuits 171 conditionally scanned, the signals of which are interlocking Flip-flop circuits 172 held by their reset input 1T3 their output on the binary combination of the conditions OÖOO for the Selection of OP can be set.

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The 4-bit output signal of the self-holding circuits 172 selects a corresponding line from the 16 control lines OP- to OP ₅ via a 1 out of 16 dialing network 174 / the details of which are not shown here, since such circuits already belong to the prior art. The scanning of the gate circuits 171 is controlled by the combination of a clock pulse CP with a control signal III or PSM via the AND circuit 175 and the OR circuit 176. Another control line is connected to the AND circuit 175 so that the sequence control is manual or on can be controlled in other ways, thereby making it possible to introduce a test program into S and set the IAR to an initial test address if the PSM controls are known to be malfunctioning. If the PSM controls are still working well enough to introduce a program in S, even if not well enough to continue operation below the limit values of the supply voltage, it is relatively easy to switch to PSM operation to enter the program ( ÖP _r , Fig. 10). If this is not possible, however, one can use an arrangement such as that formed by the bistable multivibrator 177 and the AND circuit 178 in order to block the AND circuit 175 to the combination of OP ₁₁ and I or PSM and thus the output signal of the latch circuit 172 on OP _{11 to} hold. As a result, the gate circuits 77 (FIG. 2) are blocked and the R / W cycle of 75 via the OR circuit 98 is prevented. When the bistable multivibrator is reset, the latch circuits 172 are reset to OP. the STM cycle is then resumed with the actuation of the matrix S and the latch circuits 172.

Other controls not shown here set during the FLT program input SAR and IAR in the stand, S in W-Zylden via the write controls 67 (Fig. 2) to press to store an FLT program segment in S, after which IAR is set to the address of the first FLT check word

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to save, and after which a signal is sent via 179 that the bistable multivibrator 177 again in the active state and via 173 too the lock circuit 172 resets.

TEST CIRCUIT '·

The test circuit 15 shown in FIG. 5 consists of an AND circuit with 36 inputs which are connected to the 36 output points of the SDR; the output of this AND circuit is only excited when there are binary ones at the input. The output signal of the circuit 200 is fed to a further AND circuit 201 which generates an output pulse when the circuit 200 supplies a signal consisting of all binary ones, a clock pulse CP, an operating control condition OP ₅ and an output signal from the OR circuit 202 exist. The OR circuit 202 constantly supplies an output signal in PSM operation and an output signal in each case in the I section of each STM cycle. ·

An output pulse of the circuit 201 switches a bistable multivibrator 203 (BT) into its complementary state. Therefore, two such pulses leave BT in the state it was in before the first of the two pulses. BT is reset to a first reference state (BT = 0) by the combination of CP, OP and PSM or I via the OR circuit 202 and the AND circuit 204. The output signal from BT is fed to an AND circuit 205 which, when the combination of BT = 0, CP OP _J4 and PSM or I _{is present, generates the signal OP '14} , which enables the transmission of a branch address from the SDR via the gate circuits 32 (ELg. 2) controls in the IAR, whereby a branch test sequence can be initiated, which begins with a new address in S. . '■ ■ - ".

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EXAMPLE 1 - ROS TESTS

The coordinated mode of action dcx · arrangement described above becomes more comprehensible based on the tabular descriptions of their Applications in Figures 7-10, in conjunction with the explanations below. The first working example given in Figs. 7A and 7B relates to the test of the ROS control memory including those mentioned above Sampling timing by means of the relatively independent STM controls that the Matrix S and the test subgroup end coder 10, the test circuit 15 and the 2 and 3 include blanking and blanking busses shown in Figures 2 and 3.

At the top of Fig. 7A a time scale is plotted showing the relative timing of Sections I through IV of an STM cycle. After that, everyone has these sections a duration of 500 ns or 1/2, us. The beginning is used for clarity every 125 ns quarter of an STM-Ab slice through a marked after and subscript ge put letters, where z. B. start the first quarter at I., the second at L, and so on.

Prior to initiating a test sequence, a test program segment is entered in S as described above and the IAR is set to an address which is four less than the address of the first test word. In the first round of checking, the IAR address increased by four is transferred after the SAR and IAR, and S is actuated to begin an R / W cycle. In the R part of each such cycle, the SDR is reset and the check word calibrated at the address g <^> is keyed into the SDR at the address specified by the SAR. The SDR register is reset at about I and the sampled information in the matrix S is reset at about III. keyed into the SDR register. This first check word contains the code for the selection combination Olli van OP ₁₇ as control segment (bits 32 to 35). This code will

Q09828 / 1IS1

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«23 -.

H99226

therefore stored in the circuits 173 (Fig. 4) during section III. while the regeneration or W-II half of the R / W cycle is in progress.

During section IV and the first part of section I, the operations controlled by OP_ are carried out. Twelve SDR bits are transmitted into the ROSAR over the output bus and blanking bus (Fig. 2) and gates 137 (Fig. 3), and the ROS is transmitted for one cycle over control connection 122 (Fig. 3). operated to insert a 90-bit word into the ROSDR. The correctness of this word can be checked by the other check words in the sequence described here. At the beginning of section I of the next cycle, BT (FIG. 5) is reset to 0. ■■ .. ". ' ■■ "-.-

In the second STM cycle, the output signal of the OR circuit 98 (FIG. "2) again initiates the transmission of IAR plus 4 to IAR and SAR, and another R / W cycle with reference to the next word address in S begins Bits 32 through 35 of the second test word keyed into the SDR are latched during Section III of this cycle These bits constitute a code for selecting one of the five key-in control operation lines OP.-OPg carried out in section I of the next R / W cycle for the reasons explained below: In section I of the third STM cycle, the content of the IAR increased by four is transferred to the SAR and IAR, an R / W cycle is initiated, and that SDR is reset, then (see Fig. 6) a selected operation from control operations OP through OP _{5 is} carried out by selectively transferring information to the SDR from either the ROSAR or the ROSDR.

As can be seen from FIG. 10, ΟΡ _χ transmits the ROSDR bits 0 to 30, OP transmits the ROSDR bits 31 to 55, and OP- transmits the ROSDR bits 56 to 87

BATH ORIGINAL

00 982871351

and OP ₄ transmits the ROSDR bits 88 and 89 to the SDR, OP ₅ transmits the 12 address bits in the ROSAR to the SDR. Any such transfer is carried out with reference to pre-allocated bit positions in the SDR with the exception of control bit positions 32-35. Since the scanned information is entered into the SDR after the SDR is reset, the third check word keyed into the SDR during Section III is overwritten (ie, ORed with) the scanned information. This third word is a mask word determined by programming, which consists of an O bit in a selected position of the SDR positions 0 to 31 and 1 bits in all other 35 positions. The OR link of the mask word and the scanned information thus consists either of a zero and 35 ones or of all ones, depending on the state of a bit located in a certain position in the scanned information.

Since the sampled information is excluded from levels 32 through 35 of the SDR, these levels contain four ones which form the code for selecting OP_. OP ₁ _ is executed (the complement is formed to BT if SDR contains all ones) at the beginning of section I of the next {fourth) cycle before the SDR is reset. During this same section I, a new R / W- £ yldus roit üqv transfer from IAR Φ 4 to SAR and IAH arcs “The fourth check word is a reference word determined by programming, which consists of all ones or a zero and -35 rushes exists, depending on the expected state of the mask linked in the or form and the scanned information. OP ₁ - will be repeated during section III of this fourth cycle

1 ö

stored in 172 and executed at the beginning of the next (fifth) cycle (FIG. 7B). If the reference and the ORed words are the same in both cycles of the execution of OP ₁₅ , they produce the same effect (ie, BT either remains de-energized in both cycles or it is advanced twice} - and in or form

QO 9 8 2 8/1 3 B 1, _nm original

linked words are different, BT is switched in one cycle and not aroused in your other cycle; Since BT between cycles 1 and is reset to the state BT = 0, it follows that the state of BT after the fifth cycle in. Depending on whether the reference and the Words linked in the OR form are the same or different, either is equal to 0 or equal to Ϊ. Since these words are only used in one programming can differ from certain selected bit positions, it also follows that that the state of BR is determined exclusively by the scanned information in the relevant bit position. Hence it is important and a memorable one. times the invention that the state of BT from a single bit in a Group of sampled bits can be made dependent without any actual selection circuitry can be used to identify this bit or to distinguish it from others.

In the fifth cycle, the operations IAR + 4 after SAR and IAR, cycle S and SDR reset are carried out. During section III of this cycle, the fifth check word is locked in the SDR. The control bits in this word which form the code 1110 for the selection of OP ₁₄ are stored in the latches 172 of the decoder (FIG. 4). According to FIG. 5, during section I of the next (sixth) cycle, if BT is equal to 0 because it has either been switched twice or not at all, OP- ^ via the AND circuit 205 for the transmission of a clock pulse to the control line OP _{'14 is} effective to initiate a transmission of bits 12 to 31 of the SDR into the IAR. In addition, OP locks'., The gate circuit 88 (Fig. 2) and the gate circuit actuates 32 (Fig. 2), whereby the transmission of IAR + suppressed by IAR 4 and in its place the transmission of SDR after IAR simultaneously with the transmission of IAR + ■ 4 is carried out according to SAR. For reasons that are irrelevant here, it is technically impossible to attempt to carry out a transfer from SDR to SAR * in one cycle. Therefore, a wait or idle position (OPo) is switched on in cycle 6 through programming.

009828/1351

As already mentioned, it is a precondition for the branch address transfer from OP ₁₄ . that BT = O. Therefore, the address contained in the IAR at the end of cycle 6 if BT »0 is the branch address transferred from the SDR or, if BT = 1, the address increased by four in the previous cycle. Since BT = 0 represents a "good" condition and BT = 1 represents a "bad" condition, the check words entered by programming in these two addresses therefore initiate various operations. The branch address information supplied to the IAR from the SDR is programmed to four units as the actual address of the branch check word to be generated during the seventh cycle, so that when it is increased by four in the seventh cycle, the correct address is represented.

In the seventh cylinder the programmer can choose between several options. If the test shows "Bad" (BT = 1), the addressed memory location in S can be provided with a word that contains the control bits for the selection of the stop operation OP. having. As can be seen from FIGS. 2, 7B and 10, OP prevents the initiation of the next R / W cycle of S by locking the AND circuit 99 (FIG. 2), whereby the conditions locked during the previous cycle remain in place. Bits 0 through 11 and 23 through 31 of this word are programmed to indicate the ROS word and the bit addresses at the "bad" point.

If BT * is O ("Good"), in cycle 7 the next word in S specifies the selection of 0P ", ÖP_ or OP .. depending on the test stage reached. When all tests have been carried out in a program input, OP .. is specified to initiate input of the next program load in S. When all tests have been carried out in a complete series, OP specifications are made in order to convert the controls to PSM operation. In. in all other cases OP is specified.

BATH ORIGINAL 00 3 828/1 3S 1. .-, - w: 1-

OP- is only necessary to a limited extent in order to check a RÖ3 «bit that is not the first bit of an RGS word. This is only the case if the previous test shows that BT - 0. If it _{terminates with OP Q} (Stop) because BT = V 1 ("Bad"), BT must be reset before the next bit can be tested. The test control information would thus be stored in S in the following order: OP ₇ , ΟΡ · _{χ 2 3 4 odej> ßf} OP ₁₅ , OP ₁₅ , OP _1, OP _Q , OP (next bit test) and so on.

To check an s 90-bit word in the ROSDR, at least 7 χ 90 - 630 Checkwords are stored in S. For example, if S only has a capacity of 16 OQO words, an FLT program load would not exceed Check 25 ROSDR words. Since a single FLT program run through a 16,000 word matrix S at a rate of 2.us per The cycle lasts only 0.032 seconds, and in the worst case scenario, you have a full set of tests of the ROS system - in less than five minutes To calculate what will be compared to the time a technician normally takes füx * requires the implementation of equivalent tests, very cheap except «. ■

As shown in cycle S in FIG. 7B, if the last test of a series is successfully completed, the last word of that test can select OP "by setting the monitor switch to the PSM mode to bring control of the system back to the ROS. Transfer system. If the final check sequence is merely the final sequence of an FLT load, the final check word _{can select OP 11} to initiate the start of a new FLT program load, as discussed above.

_{BATHROOM 0R1QINAL} 00 8.82 8/1361

H98226

BKISPIET, 2 - S-CHECK SEQUENCE

The example explained above illustrates the sequence of STM operations that are necessary for testing the ROS system. A sequence can also be carried out in STM operation to check the state of the S matrix and its peripheral devices without further ado Facilities to consider than those described above. According to FIG. 8, the sequence begins with a first set of four test cyclones, and is continued on a conditional basis with subsequent sets of two test words each as follows: The first cycle of the first set of tests is the same as the first cycle in FIG OP is stored in the decoder latch circuits. The important operation in this cycle is the resetting of BR (Fig. 5) while all other operations are unnecessary.

In the second cycle, the code for the selection of the control operation OP _{1 is} locked, and the information stored in the bit positions 12 to 31 of the SDR form a branch address. *

The matrix S is a three-dimensional X, Y, Z matrix in the form of a square. Plane in the X, Y dimensions, while the 3G BlUWuTtCr extend in the Z direction. Programming ensures that the apparent address of the second test word addressed in S defines the memory location of the first word position along the main diagonal of the -Χ, Y-plane. It is also achieved by programming that each word along the Ilauptdiagonalc the address of the next word along the same diagonal in their bit positions 12 to 31 and the code for the selection of OP. reveals in their bit positions 32 to 35, while every word not on the main diagonalc, with the exception of the word adjacent to the main diagonal word, contains the code for the selection of OP (Stop). The word adjacent to the main diu ^ onal word indicates OP “(not OP) .

009828/1351

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OP. . is therefore selected in Part III of the second cycle only if the i-.hz word, in particular the first word on the main X, Y diagonal, is correctly addressed and correctly keyed into SDR «If anything other than this occurs , OP _Q or ° £ \ _Q would be selected in Part III and the exam would end in one of the next two cycles. When OP. is selected, a wait operation is carried out in the third cycle, as described above for the sixth cycle in FIG. 7B, so that there is sufficient time for the branch address transfer from SDR to SAR due to the state of BT. In the next or fourth cycle, if OP. . has been selected and if a branch address was transferred to the IAR during the previous cycle, the information keyed into the SDR will appear to be that located along the next major diagonal (XY) word position of S, creating the fourth cycle with them Conditions would complete as when the second cycle was completed except that the second address on the main diagonal would be checked instead of the first and the next step in the check would be to repeat the action specified in the third cycle. On the other hand, if OP _{1n is} stored during the fourth cycle due to a failure, all operations are stopped. The test is therefore continued with a repetition of the operations called up in cycles 3 and 4, or it ends with a "Schlech.t ^u" signal.

Important information can be derived from every "bad" signal. For example, the inability to address any memory location on the diagonal indicates an addressing error, while the inability to address a particular address memory section could indicate a sampling timing error due to noise in the sense lines of S. If no address memory space in S has been successfully addressed, this could also be caused by a failure of the input parity check circuit that is assigned to the program load channel.

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UUyOiä / IÜ »I

- J

EXAMPLE · 3 - BT -PRUFFQLGB ϊ'ίι

A third application example for the test arrangement shown here is shown in FIG. 9 and relates to the testing of the binary multivibrator BT and the logic circuit assigned to it (FIG. 5). The first six cycles of the test sequence shown in FIG. 9 are intended to check whether BT can be reset to the state BT = via the reset input scontrol line (the output line of the AND circuit 204, FIG. 5), and whether it can be reset from this state to the State BT = 1 can be switched over by an action of the AND circuits 200 and 201 of FIG. 5 and the connections leading to them. In cycle 1, BT is apparently switched to the state BT * 0 by selecting the control line OP_ as a result of the corresponding programming of the first check word in S. In the second cycle, BT is apparently switched by a check word consisting of all ones in the second check address position of S, which, if used accordingly, _{would excite the AND circuit shown in FIG. 5 and also select OP 1} _ to to energize the AND circuit 201. During the third cycle, the third one included in the SDR- * *

probed check word control information for the selection of OP., so that, in the many * «'th and fifth cycles, a branch address selection operation takes place in accordance with the status of BT. If BT = 0, which means that it has not switched, although it should have apparently changed to BT = 1, the branch address specified in the SDR is transferred to the IAR and a control code for the selection of OP _{10 is} generated whereby the test is terminated with a "bad" signal. If, on the other hand, the test should indicate that BT = 1 (this is date opposite of the test criterion used in the ROS tests of FIGS. 7A and 7B), the test continues with a series 6 to 10, through which it is checked whether BT can first be reset to the state BT = 0 and then toggled twice to generate the state BT = 0 again after first

009 828/1351 BAD ORIGINAL

the state BT = 1 has been passed through. In cycle 6 is through the previous. Cycle selected OP ₇ BT is reset to the state BT = 0, and the addressed memory location in S supplies a word consisting of all ones for activating the AND hold 200 and for the selection

of OP, apparently to switch iim BT. In cycle 7 this consists of S 15th

addressed word again made up of all ones, and again BT is apparently toggled to be reset to the state BT = 0. In 'cycle 8 OP,. is selected, and an address branch is carried out in cycles 9 and 10, corresponding to the status of "BT. In this branch, if BT = 0, _{a branch address is transferred from SDR to IiVR by OP 5} , and the information at the branch address directs the Cycle 1 of a new test series. If BTnot is equal to 0, the current series ends with the selection of OP,. '

COMPATIBILITY

The above examples show how general purpose erasable memory, which is not normally used for direct micro-operation control purposes, can be incorporated into a circuit that takes advantage of a small portion of the special permanent micro-operation controls of a data processing system to provide an effective and, in terms of mass, economical test of the Perform system micro-operation sequencing controls and a quick check of the operability of the erasable memory itself and the control circuitry it shares. On successful completion of the whole series of tests can be assumed that * both erasable and the permanent controls arbeien properly so that while holding a "Poor""signal further tests untex ^one of the direct control of the permanent Ivlikr © operations order -

BAD ORIGINAL, 009828/1351

Controls in relation to all other parts of the data processing system including der.Reehenschaltungen and peripheral devices so long run until the error is found.

The described arrangement is particularly economical because it can test parallel groups of signals bit by bit without having to resort to special circuit devices to distinguish or select the individual bits, since the selection function is carried out using programmed binary mask words,
which each contain an optionally placed zero bit in a field that otherwise only consists of ones.

BATH ORIGINAL

009 828/1 3B 1 ./-

Claims (3)

- 33 PATENT CLAIMS 1. Device for testing the central unit of an electronic Data processing system using a test program, characterized by the arrangement of control and transmission units (16, 28 and 27, Fig. 1) for the alternate connection of the read / write memory (1) and the read-only memory (3) of the system as microprogram sources to the test circuits (4, 15). 2. Device according to claim 1, characterized in that the connection the read / write memory or the read-only memory to the test circuits with the help of a switch (l6) or automatically done manually. 3. Control and transmission units for the test device according to claims 1 and / or Z, characterized by a test subgroup decoder (10 Fig. I), wel & he by means of a monitoring switch (16) either to control signals s read / write memory (1) or the read-only memory (3) is switchable and, depending on these control signals, ^{selects certain control lines (OP} _{obis 15} ), the signals of which control certain T or circuits of the central unit to carry out the micro test operations, furthermore by a test circuit (15) for good / bad testing of several bits Existing groups of signals that can be supplied via a data bus (30), consisting of AND circuits (200, 201, FIG. 5) for the selective generation of signals for switching over a single-stage binary counter (203) and an AND circuit (204 ) to generate signals to reset the binary counter to a predetermined position (BTsO) with an AND circuit (205) for transfer processing of a branch signal (OP ..) for address control of the read / write memory 1st, · \ ■; ■ BAD ORIGINAL 009828/1311