DE1487810C - Synchronization device for image signal transmission systems - Google Patents

Description

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Orders are not combined, but they are achieved for images that correspond to the respective amount of the Signal transmission systems are essential, as they are adapted even in the event of a fault. It is also a very stable one small synchronization errors due to the re-operation of the synchronization device The required time ensures that disturbances are generated, since the synchronization errors are low 5 Control circuit for gross synchronization errors reduce considerably. Avoidance of such disturbances can not influence and therefore with their Aufrungen With regard to numerous other malfunctions, there is no switch-on process with high amplitude possibilities, which in turn already require degradation.

can cause deterioration of the image quality, an embodiment of an inventive

worth seeing. io synchronization device is used below for

The invention is based on the problem of finding a use case in a facsimile transmitter EMP synchronization device described for image signal transmitters that are connected to a telephone network to create, which can be activated above. In the figures are the individual radio shows Requirements met, that is to say in the synchronous addition units of such a transceiver very stable and insensitive to interference. It shows

in the non-synchronous state, on the other hand, F i g. 1 the basic circuit for generating

ensures fast synchronization. Time reference signals,

A synchronization device of the initially shown FIG. 2 in the circuit according to FIG. 1 recorded Art is to solve this problem in the form of impulse forms,

appropriately designed such that the comparison 20 F i g. 3 the scanning device of the facsimile transmitter circuit determines the size of the frequency difference with the associated control circuit,
and as a function of the frequency deviation F i g. 4 the control circuit for the write input

at least three different signals to three directions of the facsimile receiver,
Outputs control circuits that have a coarse and a F i g. Figure 5 shows another embodiment of a part

fine synchronization errors as well as the synchronous 25 in FIG. 4 arrangement shown,
ized state indicate that the first control F i g. 6 the logical synchronization control switch

circuit dependent on the one coarse synchronization for the writing device and
sation error characterizing signals periodic F i g. 7 in the circuit according to FIG. 6 to control signals to increase the frequency of the pulse generator used for synchronization by a first amount to the pulse generator pulse shapes.

rator provides that the second control circuit depending on F i g. 1 shows the generation of the in F i g. 2 dar-

the time-marking signals used by the synchronization pulses identified as a fine synchronization error are periodic control signals to the encoder circuits. These control the operation of increasing the frequency of the clock generator to one of a facsimile transceiver. A tuning fork oscillator or the clock generator, arranged in a clock second, compared to the first smaller amount, supplies the generator, and that the third control circuit generates another stable oscillating arrangement 201 , depending on the circuit, the synchronous state a signal with a frequency of 3840 Hertz, which in Characteristic signals a direct switching through a pulse shaper stage 202 is used to form a sequence of certain transmitted signals as periodic positive pulses of this frequency. Causes control signals to the clock generator. 40 These pulses are a counting chain or a

When a synchronization device is supplied according to the frequency divider, which is made up of the seven in series, it is one of the roughly switched trigger flip-flops I to VII. It and after subtle errors separate synchronization. A quartz oscillator with a higher frequency can also be used with subordinate image divider stages that work with line-by-line scanning; If the mode of operation of two counters 203 with a counting volume of 64 steps of cyclically operating devices is summarized in the manner shown. Should all be, then the cases of too high or counting levels can be differentiated 50 at the same time from a common too low operating speed of the one source via the diodes 204 to zero to the device with respect to the other. At the output of the counting stage VI. Both errors can be generated by accelerating a signal in the form of a 60 Hz right of one device compared to the other. At the output point in time the same phase position of both devices of stage VII appears a 30 Hz signal H, the same is reached. At this moment, the causes according to 55 if a square wave voltage. The motor has a third control circuit provided according to the invention speed of 3600 / min and drives a write a direct through-connection of certain transmitted drum with 180 / min, so that one revolution 333 Vs signals as periodic control signals on the clock milliseconds or 20 periods of the signal generator . This is then because it lasts the synchronous one. The drum generated via cams as well as has reached state for further operation in 60 switches in the in FIG. 4 shown in more detail held this state. A synchronization means, time reference signals M, ~ M and S. With reference to the direction according to the invention made possible by the rotation of the drum, the signal M appears in the separate synchronization of coarse and fine syn- 0 volt or logical "1" state of 355 , 5 until the chronization error reaches a correspondingly high speed 7.5 ° and the signal S in the »!.« State from 22 until the control is in the synchronous state. Since 65 36 °. The signal Ή, the inversion of the signal M fine synchronization errors more often than coarse synchronous represents. Because of the fixed interaction between the chronisationsfehler occur can be applied to the frequency divider 203, and the drum is conveniently by the invention shown way Regelgeschwin- moderately, the angular position of Drum for fixed

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Laying the various generated pulse trains to use an output pulse of minus 6 volts of 31.5. It should be noted that in the illustrated to 36 °. This pulse is fed to an input of the flip arrangement for one period of the oscillator 201, a flop circuit 231. Furthermore, the off-duration is 0.26 milliseconds and 0.28 ° corresponds to the output signal of the inverter 213 in the gate 221 with the drum rotation. A 5 signal M combined therefore lasts and causes a signal of degrees of drum rotation about 0.93 milliseconds minus 6 volts from 355.5 to 0 °. This impulse becomes the. the second input of the flip-flop circuit 231

The output signals "0" are fed to stages III and IV. This is done alternately by the signals

of the counter 203 are set and reset at their two inputs in the NAND gate 205,

in summary, whose output signal appears through the In- io at the corresponding output a Si

verter210 is inverted. The congnal in the state »1« means that it ranges from 31.5 to 355.5 °. This

capacitor 224 is somewhat delayed and the NAND gate signal is referred to as the image gate signal /. The

ter 215 supplied. This signal is in the logic of the output signal of the gate 221 is in the inverter

was "1" when the counter 203 also inverts steps 0 232 and forms a signal im

to 3, 16 to 19, 32 to 35 or 48 to 51. The 15 state »1« from 355.5 to 0 °, which is

further processing of this signal is referred to below as signal E ,

described. The output of the inverter 213 also becomes

The output signals "0" of the stages V and VI of the first inputs of the NAND gates 222 and 223

Counters 203 are fed together in NAND gate 206 , the outputs of which with the inputs of a

The output signal 211 of which is inverted 20 flip-flop circuit 233 are connected. The second

and forms the signal D. This is in the logical input of the gate 222 receives the signal M, while

was "1" if the counter 203 on the steps 0 rend the second input of the gate 223 the invers-

up to and including 15. This output signal er sion of this signal, namely the signal M supplied

appears 20 times per revolution at 0 to 4.5, 18 to becomes. In this way the flip-flop changes

22.5, 36 to 40.5 ° etc. and its state is always used as the clock signal 25 233 -when the signal M

designated for the feed. changes, but this change is always

The output signal “0” of stage V is delayed until a “1” signal is received from inverter 213 and output signal “1” of stage VI is sent in gate 207 . The flip-flop changes accordingly, and its output signal is inverted in circuit 233 only at 355.5 ° and 13.5 ° inverters 212. The signal obtained therefrom 30 instead of at 352.5 and 7.5 °. The output signal of the flip is in the "1" state during the count-flop circuit 233 from 355.5 to 13.5 ° is N steps 32 to 47 inclusive. This signal is designated.

in the NAND gate 217 with the incoming Si The already mentioned signal D is in the gate 216

gnal S combined, which combines from 22 to 36 ° in addition with the signal M , which is a condition

stood »1«. The 35 generated by gate 217 represents that only one signal D per revolution

Signal is inverted in inverter 228 and is switched through. The signal obtained from it

in state »1« from 27 to 31.5 °. It is inverted as is in the inverter 227 and forms a signal,

Pre-image signal G denotes. which is only in the "1" state from 0 to 4.5 °.

The output signals "1" of the stages V and VI are The output signal of the gate 216 is also combined with the one in the NAND gate 208 , whose signal 40 is fed to the delay multivibrator 225 , which is in the logic state "0" when the delay is by Almost one drum revolution counters 203 acts on steps 48 to 63 inclusive and generates a signal Q which is shown in FIG. 2 shows. This signal F is in the logical delivery stage.

"1" was from 0 to 13.5, 18 to 31.5, 36 to 49.5 °. Signal B is also included in gate 215

etc. It is inverted in inverter 213 and leads to 45 the output signal of the inverter already mentioned

a signal that combines in the logic state "1" 210 . The negative output signal of the

from 13.5 to 18, 31.5 to 36 degrees, etc. Therefore gate 215 only appears from the counting steps

as a control signal for gates 218, 220, 221, 222 th 0 to 3 of counter 203 and only in the O ° position

and 223 used. The second input of the gate development of the drum. The signal received is internally

218 is inverted with the output signal "1" of stage IV 50 verter 226 and forms a signal C, which is activated. Accordingly, the output signal is only in the "1" state from 0 to 1.13 °.

of the gate 218 the triple coincidence of the counter F i g. 2 shows the signal pulses described above

stages IV, V and VI. This signal is in the In- as well as a composite signal UF, which the Ko-

verter 229 is inverted and thus a signal K is generated, incidence of signal F and the inversion of signal D

which is shown in the logical state "1" for the counter 55. This composite signal appears

steps 50 up to and including 63 or from 15.75 to from 4.5 to 13.5, 22.5 to 31.5 ° etc.

18, 33.75 to 36, 51.75 to 54 degrees, and so on. together with certain other represented signals

The triple coincidence signal of the output signal len is used.

"1" of stages IV, V and VI is also assigned to the gate. FIG. 3 shows in a more schematic and somewhat more precise manner

209 fed, inverted in inverter 214 , the scanner of the facsimile transmitter in gate 60 representation.

219 combined with the “1” output signals of the stages II and fluorescent lamps 181 with reflectors 301 III and finally in the inverter 230 are inverted on a plate 302 for receiving a writing. The signal obtained from this is provided in the piece state, which is generated by the drive and input "1" during counting steps 62 and 63. It is transported with pressure rollers 177 . In the plate 302 L labeled and appears from 359.6 to 360, 17.6 65 is between the lamps 181 and immediately above to 18, 35.6 to 36 °, etc. the mirror galvanometer 183 with mirror 184 a

The output of inverter 213 is provided in slot 303 . Furthermore, between a gate 220 is combined with the signal S and causes optics 185 and a photomultiplier 186 to open

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aperture or aperture 304 arranged to apply the size. It is known to contain two Antriebsdes on the document by the Spiegelgalvano- coil, which determines the coils shown correspond to 305 meter 183 to be scanned field. and are switched on alternately. The photo-ais mirror galvanometer 183 can be used any arrangement multiplier 186 is with a controlled right, which converts a receiving amplifier 321 sufficiently quickly for the scanning signals into a corresponding rotation of a mirror 184 , which is not shown. The commercially available mirror z. B. transmitted via a telephone channel, galvanometer for oscilloscopes with optical The excitation of the galvanometer 183 will work by multi-channel recording, are controlled for this one contact KIb of the relay K 2, so that purpose is suitable. A special arrangement for the illustrated one is only available if an arrangement suitable for the direction of the writing can also be created over the slot 303 . The excitation, by placing a mirror with a diameter of 12.5 mm, is produced either by a prescan generator 319 on the pen of a writing galvano or a scanning generator 320 , depending on the meter. from relay K 6, which is controlled in a manner not described here. In FIG. 3, sensor switches 306 and 15 are also controlled. The scan generator 320 generates represented a 307 a paper linearly increasing voltage, indicating in the scanning device with the drum "sheet. The formwork rotation by the Signal7 (Fig. 1) synchronized ter 306 is actuated, the presence, if the Paper on the left is. The prescan generator 319 filters and is input to the side of the scanner, and the boosts the 30 Hz square wave voltage H (Fig. 1) and switch 307 puts the paper inside the scanner 20 generates a sinusoidal signal of 30 Hz, the device close to the slot 303. The switch periods or 20 half-periods per drum rotation.

306 actuates a multi-contact relay Kl, which has rotation. A triangle voltage could equal switch 307, a relay Kl. The switch if used.

307 can also be replaced by a delay circuit of the writing device of the facsimile transmitter, which is activated by the switch 306, FIG. 4 shows the supply and control circuit. The supply current for the relays is supplied via a catcher. The recording drum 122 is guided by a switch, which is driven in the operational position of a motor 150 . The motor 150 is the facsimile transceiver is closed. Only when controlled by the signal ^ (Fig. 1) that was previously in the closed switch can therefore be amplified by a power amplifier 601. The switch 306 operated relay Kl work. Below another 30 pen holder 154 is on a lead screw which is arranged through a contact KIa of the relay Zl 159 , which is turned a voltage of minus 6 volts to a resistor 160 and 161 by the stepping motors. Connected to the 312 described here, the other terminal of which is grounded. The figure shows the drive coil 606 of the motor 160. The voltage drop across this resistor 312 and the drive coil 607 of the motor 161 is fed to the inverter 313 , the output of which is 35. The stepping motors used for the step-by-step rotation of the reference voltage can set the control voltage T for the transmitter spindle 159 and are in the "1" state if every suitable relay Kl is already energized for the stepping motor relay K1. It will have the form described for controlling the BE 178. A common drive of the transceiver is used in the transmission state order of two motors working in one direction. If the operating switch is closed, but the relay Kl is not energized back to back on a common shaft, then minus is possible. The stepping motors are driven by 6 volts at the resistor 322 and not at the resistor pulses that are fed to the two drive coils 312. This voltage is fed to the inverter 323 alternately. A special amplifier 608 is used to generate its output signal only in the state. The output "1" is when the switch is closed and the signal from this amplifier is not energized. It therefore serves as the control KIb and KIc of the relay Kl (Fig. 3), the voltage R for the receiver and controls this either on the stepping motors of the transceivers in the receiving state. The re-writing device (Fig. 4) or the step switch £ 2 has a contact KIa, which direct the relay Kl motor of the transmitter (Fig. 3). If no writing is excited as long as the relay K2 is working. Therefore 5 ° piece sent, the relay Kl is not energized, the relay Kl remains energized as long as a document and its contacts are in the illustrated is located above the slot 303 , and the signal T position, in which the amplifier 608 with the write remains in state "1" during this time. The re- direction instead of the transmitting device connected relays Kl and K2 and other yet to be described.

Relays are shown with their contacts in the idle state. 55 Other relay contacts K2> d and K3e determine. In the drawing, the contacts are not always in the vicinity of their associated relay stepping motor 160 or the reverse stepping coil. Switching motor 161. The relay K 3 is shown in Fig. 4. The drive motor 178 is provided with two field coils and will be described below. The 305 provided. It can be used for engines 178, 160 ⁶ ° completeness, it should be noted that a further 161 and many types of stepper motors comparable Contact K3C the relay K3 control of the turns are. They can for example consist of an amplifier 608 either through the pulses D normal electrical coil, which acts on a (FIG. 1) or via a NOR gate 609 enables ratchet switching. A rotary coil with a one-way clutch connected to the gates 734 and 735 in FIG. 6 can also be a drive mechanism which will be described later. The output signals of the so-called cyclonomic motor from Sigma ver of the amplifier 608 are sent to the relay of a conventional stepping relay or the contacts Kl b and KIc. The impulses from which are turned. This latter type is preferably a circuit according to FIG. 6 control the step-by-step

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motor 160 and it via the amplifier 608, the flip-flop 621 is further connected to an inverter 623

fed via the relay contacts described, connected to a response in the event of a negative

if no document is sent. instead of enabling with a positive signal. is

In a power amplifier 610 , the image relay K 5 is excited, so its contact K5a is a write or write signal from the circuit according to FIG. 6 5 closed, whereby the relay is amplified via the current and fed to the pen carrier 154. circuit itself holds, in which an alarm reset switch. An amplifier 611 amplifies the circuit 130 . The other relay contact K 5 b switches according to FIG. 6 originating pen pressure signal, voltage to an alarm signal generator 624 and then to the electromagnet 157 of the pen an alarm signal oscillator (not shown). To the carrier 154 is fed. If the alarm signal is interrupted, the operator

Cams 162 and 163 are located on the electrician. Activate the reset switch 130 , the mel 122. A voltage of minus 6 volts is interrupted via the holding circuit of the relay K 5, but every switch 164 on the grounded resistance also instantly K relay 3 turns on, stand 602, and through switch 165 to ground Accordingly, the stylus support is connected at 154 to the underlying resistor 604. Both switches 15, interruption of the alarm signal, are actuated by the cams 162 and 163. The position brought.

The voltage drop across the resistor 602 is the load. The flip-flop 622 is connected to the output of a control voltage Ή, not already described, and the demodulator shown in FIG. This is set conversion in the inverter 603, the control voltage M. alarm transmission at the remote receiver determines if Similarly, the drop across the resistor 604 is the transceiver chip 20 illustrated in the transmitting state benung Έ in the inverter 605 is inverted and is for. The flip-flop 621 is connected to the transmission control control voltage S. These voltages are connected to the signal T and, if this signal fails, controls the timer circuits of FIG. B. by terminating the transmission, and their functions have already been caused. The flip-flop 620 was written. Of course there are many other ways 25 holding a control signal from the circuit shown in FIG. 6, for deriving such control voltages from which either the lack of receiver synchronization drum rotation is possible. Magnetic circuit switches, photography or further writing capacity when electrical switching elements and the like are reached can be used instead of the cam switches shown in the end position of the pen holder 154. Confirmation of switch 613 indicates. Therefore, a switch for initiating a control alarm signal can indicate the end of the transmission of a written signal to the desired position of the drum 122 piece at the transmitter and the receiver. Can also be used, with a multivibrator or the like. It signals the lack of synchronization of the reception duration of this signal. Also, the catcher or a lack of writing capacity, the functions of switches 164 and 165 by using the handset prematurely from its additional frequency divider stages, gate switch box and the alarm in the transmitter, etc. in the circuit according to F i g. 1 reaches its recipient. Resetting the alarm. The type of signal generation shown is signals in the receiving device, but causes a reset to be simple, economical and reliable. the writing device in the starting position for

Limit switches 612 and 613 are trying to write again on both ends.

that of the lead screw 159 and are 40 F i g. FIG. 5 shows another embodiment of a pen support 154 on the left or part of the one shown in FIG. 4 shown device. The right end position of his movement is actuated. The drum 122 is connected to the drive motor 150 via switch 613 which has a normally open contact which is coupled by the gears 151, 152 and 153. With the pen carrier 154 is closed. The idle intermediate gear 152 is here, however, a rotary potentiometer contact of the switch 612 is opened by this at 45 meters 661 and with the drum 122 a rotary potentiometer return to its starting position. Connected by tiometer 662 . Each potentiometer is in the closing of the switch 613 , the relay K 3 is switched in the manner shown with a positive and negative, which closes its contact A3 α and connected tive voltage source. The voltage on the switch 612 holds itself. As a result, the wiper is then a function of the position of the input of amplifier 608 with signals D 50 potentiometer axis. The rotation of the potentiometer (FIG. 1) and the output of the forward tiometer 661 generates a 30 Hz voltage, which switches the motor 160 to the reverse motor 161 after amplification as the prescan voltage for the tet. Another contact K3b of relay K3 causes galvanometer 183 to be used. The podium output of a control voltage to the in F i g. 6 tentiometer 662 generates a circuit shown per drum revolution, which will be described later. By 55 practically linear tension. After switching on the relay K3 , the pen strengthening for controlling the galvanometer 183 at carrier 154 can be quickly returned to the left, and normal scanning can be used. In this way, although with 60 switching steps per second, the potentiometers can replace one or both stepping motors 161. If the pen holder arrives, scanning generators 319 and 320 (FIG. 3) can be replaced. 154 to its initial position, it opens the scarf 60 The voltage generated by the potentiometer 662 ter 612, so that the relay K3 is released and the comparable can be made slightly non-linear, non-linear to the various circuits back into their normal supply something The connection of the control chip level for the forward movement brings, whereby the voltage of the galvanometer 183 with the displacement of the scanning point mel 122 caused by the Tangen recording of a new document on the drum effect is prepared. 65 balance. Since a suitable jet return im-

Three monostable multivibrators 620, 621 and 622 pulse into the voltage of the potentiometer 662 or

are connected together with their outputs so that the sampling generator 320 can be used

that a relay K5 can be energized by each. by making minor changes to the corresponding

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The control circuit allows the galvanometer 183 circuit 732 to be normally in its reset state during slow scans and while on until a document is completely recorded on drum 122 by slow subsequent faster scans. If both the potentiometer 662 or the generator 320 to flip-flop circuits 731 and 732 are in reset control. 5 state, the coincidence of the incoming F i g. 6 shows the received and logical syn signals with the internal signal D detected. Each chronization circuit. The strong lines characterize the coincidence signal via the NOR gate 609 to draw the signal value. It is advantageous to start with (FIG. 4) the stepping motor 160 (FIG. 4) on the assumption that the transmission is taking place. The stepping motor 160 of the writing device receiver is in the receiving state, depending on the operation of the stepping motor 178 due to the lack of a document in the scanning device of a remote transmitter,
device, and that the timer circuits from As long as the flip-flop circuit 732 in the reverse Fig. 1 remains synchronous with that of the remote transmitter, will work via gate 736. The signal arriving at a demodulator, which is located between the flip-flop circuit 732 and signal, is connected to the gates 711 and 712 in parallel with the amplifier 611 (FIG. 4), which conducts write. The output of gate 712 is held sharp on drum 122. The signal / an input of the NOR gate 714 is supplied, while is also supplied to the gate 736, in order to raise the output signal of the gate 711 first above the writing tip when it wanders on the drum 122 via a clamp of a monostable delay circuit 713. In this way and then to the other input of the NOR gate 20, neither the write process nor the pre-714 can be supplied. The monostable circuit 713 start switching before the first incoming does not respond to "1" signals that are shorter than 1 MiIIi image prepulse G is received. Should be the writing second. Longer signals trigger this switching process no further, so the device and cause the delivery of a pulse from flip-flop circuit 732 either by a signal 4.2 milliseconds or 4.5 ° duration, the beginning of which is 25 over the Contact K 5 b of the alarm relay K 5 (Fig. 4) by 1 millisecond compared to the input pulse or by a synchronization error signal which is delayed. The one-shot circuit 713 is a circuit shown in FIG. 6 set. The latter leads to the formation of control pulses used which are opposite to the image signals also used to respond to the alarm circuit in FIG 30 device and the alarm multivibrator 620 (Fig. 4) to avoid the etc. The remaining indicated connection shown in Fig. 6 exists.
If two signals constructed according to the invention or those of the monostable circuit transceiver are connected to one another, then either the direct input signals must be connected to one another

713, depending on the opening of the gate, they are brought into synchronism with one another and into the -712. In the initial state, the gate 711 is open and held in its state. More precisely, the gate 712 is locked, which is why the signal of the indicates that the signal generated in the receiver D monostable circuit 713 via the NOR gate with the corresponding incoming signal

714 goes to NAND gate 727. The other coincidence must form, or that the two inputs of this gate in the receiver receive the received signal D in the same connection with the reception control signal R and a synchronization signal. 40 of the drum 122 must be, as it was when the transceiver was in the received pulse to be received in relation to the drum and if it was correctly synchronized with a remote transmitter 122 in the transmitter when it was sent, then you can get there The transceiver always sends a series of signals via gate 727 and inverter 728 on signals B (FIG. 1) in front of each control or gate 729, 730, 733 and 734 Image signal. These signals can be used to produce the 729 coincidence of the incoming signal with a synchronism in the receiver, and internal image pre-signal G, so via its output there are also devices provided through which the flip-flop circuit 731 in its »1 “-The synchronism was set during the transmission of a document, which in turn keeps gate 711 of the document.

and the gate 712 is opened. This 50 assuming that the recipient is initially

signals that have not yet been influenced can be recorded completely out of synchronicity with the transmitter,

and on the circuit according to FIG. 4 is the one on the left-hand side of FIG. 7 shown

works. All of the following situations pending at gate 733. In this figure there are several at the

Signals can be displayed within the writing period from synchronization occurring pulse trains,

depending on the image gate signal / through the gate 733 55 The lack of synchronization is due to the gates

get through and the writer 720 and 722 are detected, which together produce a NAND

fed. Form gates with four inputs at the end of each written line. The integrated

is the flip-flop circuit 731 by the signal 77 image signal of the monostable circuit 713 is with

reset, whereby the gate 733 locked and compared to the signal Ή , which is the inversion of the

gate 734 is conditionally opened. This forms 60 cams 162 and represents the generated signal from 7.5

with the gate 735 a NAND gate with four one to 352.5 ° lasts. If the incoming Si

corridors. The same coincidence with the internal signal B in this period becomes such a conditional one

pulse G, which previously sets the flip-flop circuit 731, coincidence of the incoming signal with the Si

simultaneously sets flip-flop circuit 732 via signal M in gate 720. The gate 722 the gate 730 back. 65 is through the "1" output of the flip-flop circuit

While the state of the flip-flop circuit 731 732, which, as described, is initially set

and gates 711 and 712 are at the end of each state, and opened by signal 3,

If the write line is changed, the flip-flop remains - allowing one pass of the first received

Pre-image signal G is prevented by the gate. The signal of the gates 720 and 722 indicating the lack of synchronism sets the flip-flop circuit 716 to the "1" state and causes the signal lamp 131 to light up via the amplifier 717. If the receiver and the transmitter are in completely poor synchronism, then the signals B also fall outside the scope of the internal signals Q , and a coincidence of the incoming signals with the signal "Q is detected in the gate 704 , whereby the flip-flop Circuit 705 is reset to the "O" state.

If the flip-flop circuits 705 and 716 are in the described state and the receiver control signal R is in the logical "1" state, the signals K and R can pass through the gate 710 and the gate 706 and are sent via the NOR gate the multivibrator 719 which generates a positive pulse of 0.2 millisecond duration. This is the reset diodes 204 in the in F i g. 1 is supplied to the circuit shown for resetting all stages of the counter 203 to zero. Since signal K is generated in counting step 56 , counter 203 is reset in this step instead of normal counting step 64, and all signal sequences as well as drive motor 150 and drum 122 are accelerated by a factor of 64:56, ie by about 14%. As a result, the received signal B is quickly caught up with the other signals B from the transmitter.

Since the receiver drum 122 now performs a rotation of more than 410 ° per corresponding rotation of the transmitter drum, it is possible during one rotation from the state in which the received pulse B is in front of the internal signal M to change to the state in which he follows it. In these circumstances, the need for synchronization is not determined and the eventual establishment of synchronism would be delayed. This possibility can be eliminated by accelerating the counter less quickly, so that the receiver drum gradually overtakes the transmitter drum, or by increasing the signal pauses in signal M. The former method would always lengthen the time required for synchronization, the latter is also unfavorable . In the circuit shown, however, the coincidence of the received signal B with the signal Q is first determined. The total length of the overlapping signals Q and M is such that signal B cannot be processed during a single revolution. The signal ~ Q is inverted in the inverter 737 and thus forms the signal Q, which is then compared in the gate 708 with the signal of the NOR gate 714 and with the signal Ή. If a coincidence of the incoming signal with the signal Q but not with the signal M is determined, the flip-flop circuit 705 is set to its state "1" and the passage of the signals K through the gates 709 and 710 is blocked . Instead, the signals L, which were previously linked with the signals Q in gate 701 and inverter 702 , can pass through gate 703 and NOR gate 707 to multivibrator 719 . The signal L is shown in FIG. 1 generates and accelerates the counter and the devices connected to it by a factor of 64:62 or by 3% when used to reset the counter. The signal L can only pass through the gate 701, however, when the signal Q is also present, so that relatively few pulses L can reset the counter, which means that the counter continues to count at an average rate that is only slightly greater than the normal 60 steps per second. This allows the receiver to accelerate slowly by this small amount in accordance with the low requirement for full synchronization.

ίο If the synchronism is finally achieved, a coincidence of the incoming signal with the internally generated signal J is determined in the gate 715. The gate 715 then resets the flip-flop circuit 716 to the "0" state, whereby the lamp 131 is extinguished and the reset signals K or L against the NOR gate 707 are blocked. At the same time, the gate 707 is opened by the flip-flop circuit 716 and the control circuit already described for the write operation is activated so that it responds to incoming signals, control signals or image signals. It should be remembered, however, that the writing device does not start writing until the first pre-image signal C is received, thereby avoiding any unnecessary consumption of paper on the drum 122 . The first received image pre-signal G resets the flip-flop circuit 732 , whereby the gate 722 is blocked and the following image signals can then no longer change the state of the flip-flop circuit 716.

The gates 721 and 723 as well as 725 and 726 can be viewed as two separate NAND gates with five inputs each. Each of these two gates can be opened conditionally by the “0” output of the flip-flop circuit 716 and is also connected to the incoming signals via the NOR gate 714 . Furthermore, each gate can be opened conditionally by the reception control signal R. However, one of the gates is opened by the M signal while the other is opened by the delayed N signal. Finally, both gates are driven alternately by the flip-flop circuit 732 . Prior to receiving the first Bildvorsignals G, the flip-flop circuit 732 is in the set state, and opens the gate 725 and 726. Each incoming signal, preferably a signal B or D, that occurs in the particular time period by the signal M is passed via the NOR gate 724 to the multivibrator 719 described and causes the counter 203 (FIG. 1) to be reset to zero. In this way, the receive counter is brought into exact phase coincidence with the transmit counter, whereby precise synchronism is achieved. A correction of ± 9 ° is possible in this way. Even if the local oscillator 202 operates slightly faster or slower than the transmitter oscillator, the overall phase error between the two can be eliminated for each revolution of the drum 122 during an image transmission.

Upon receipt of the first picture pre-signal, the flip-flop circuit 732 is in the reset state and the gates 721 and 723 are opened instead of the gates 725 and 726 . As a result, the reset pulses fed to the counter 203 are linked to the signal iV instead of the signal M , which provides better protection against an erroneous reset at the end of the image transmission.

15 16

signals used in contrast to control signals, the flip-flop circuit 757 switches back in the period is enabled. During the actual "!." State. Shortly thereafter, this signal is sent via the write process, the incoming signal is a delay circuit 756 (z. B. multivibrator) back and forth between gates 711 and 712 to gate 758 and controls it so that it switches so that the image signals unchanged to the 5 "1" output signal of the flip-flop circuit 757 in FIG. The circuit shown in FIG. 6 reaches the control signal via the inverter 759 and switches the flip-flop signals to the "O" state via the monostable circuit 713, however, circuit 762. The third to be led. Input signal at gate 753 switches the flip-flop

The in F i g. 6 can also return to the "0" state in circuit 757. If the form for synchronization is unchanged after an io, both flip-flop circuits are in the "O" state, other methods can be used. Instead of one, the gate 764 blocks the gate 753, and further signals pending on the monofrequency oscillator 201 (FIG. 1) of the one gate are not evaluated. Frequency divider 203 with variable dividing ratio controls approximately 1 second after resetting the flipert, an oscillator with variable frequency flop circuit 716 , the gate 751, can be used temporarily, whereby the reset diodes 204 15 correct through the delay element 750, open are omitted. In the transmit state, no control signals are fed to the oscil- lator and internally generated signals G. Your Wirlator receives, and the transmission is the one that passes through the gate 753 receiver works in the manner already described for the signals due to the symmetry of the circuit. In the receiving state, the flip-flop is opposed. Assuming that both flip circuits 705 to connect one of two control flop circuits 757 and 762 in the "0" state used voltages to the oscillator, the first incoming pulse G sets the more or less Great acceleration in the flip-flop circuit 757 into the state "1", to be achieved in the manner described. Present at reaching next it will reset and the circuit 762 in the approaching synchronization is the flip-flop Scarf state "1", and the third sets the circuit 757 tion 716 as previously reset thus the Toggle 25 again " 1 "and holds circuit 762 at" 1 ". incoming control signals through the gates 721, 723, the gate 763 then prevents changes of state 725 and 726 to a phase detector, the flip-flop circuits are passed through further pulses G. den, which compares them with the internal signal B and the next pulse G, however, in a difference a correction signal for the phase of the oscillator 201 is decorative element 765, e.g. B. a capacitor, differentiated generated. 30 and an input of gate 766 , des-

A compensation circuit can also be used with the other two inputs with the "!" Outputs

in which the counter 203 has its resetting capabilities of the flip-flop circuits 757 and 762 connected

Liability retains and the oscillator 201 are in turn on. If there is coincidence in gate 766 , the flip

is a monofrequency oscillator, the frequency of which is set to the "1" state per flop circuit 732 and

but can be changed within small limits. At 35, in connection with FIG. 4 described

With this arrangement, flip-flop circuit 705 conducts the alarm.

Reset signals in the manner described for normal operation are the flip-flop counters 203, whereby a coarse synchronization er circuits 757 and 762 in the "0" state before it is enough. Thereafter, the flip-flop circuit first frame pre-pulse G arrives, since the gate 753 716 is reset and switches a phase detector 40 three or more signals B or G are pending. After effective, the control voltage for the oscillator determining the synchronism can internally ER- 201 testified for adjusting and maintaining the fine signal G generated by the gate gelansynchronisation 751st gen. Therefore, a signal G is set during normal operation

The circuit according to FIG. 6 also contains a flip-flop circuit 757 in the "1" state, the

reversible synchronization indicator circuit, the 45 next received signal B puts it back into the

signaled lack of synchronization. The internally "0" status, etc., however, is dropped by the recipient

Generated signals G are fed to the gate 751 , the transmitter out of step or are the received ones

However, the flip-flop circuit 716 blocks signals due to transmission interference or a. mutinous

until synchronism is achieved. If the operation is melted, no further signals get through the

approximately synchronous and the flip-flop circuit 50 becomes gate 753, and the reversible counter only counts

716 is reset to the "0" state, the signals G passing through the gate 751 arrive.

in the particular period by the signal N Si- After four faulty signals received at genus

gnale on the gate 753. Assuming that ter 753 , the gate 766 determines a coincidence and

the trigger flip-flop circuits 757 and 762 cause an alarm in the receiver and in the transmitter,

are in the "1" state, the output of the gate 55 The flip-flop circuits 757 and 762 as well as the

ters 764 on OVoIt or in the logical "1" state, associated elements form an exemplary embodiment

and the incoming signals B or D go to a reversible counter, but it can

through the flip-flop circuit 753 and the inverter also other known reversible electronic or

754 and switch the flip-flop circuit 757 into the electromechanical counter as well as analog integral

"0" state. The next signal at gate 753 60 gates can be used with equal success.

For this purpose 2 sheets of drawings

Claims (5)

1 2 series of basic pulses of a predetermined patent claims: contains frequency and that the timer devices by a multi-stage, of these im- 1. Synchronization device for image signal transmitted with line-pulse controlled frequency divider (203) of bilateral scanning, which by the first and the second control systems, in particular for facsimile switching (705, 716) by means of periodic reverse directions, to synchronize the receiving · control signals, whereby it skips a side image signal evaluation with the transmission-side first and a second number of counting steps for image signal transmission by comparing and thereby an operation in each case with signals that are periodically from an io to the first or A second amount can be generated against the evaluation device, with signals generated and transmitted on the one hand above the predetermined pulse repetition frequency at a higher frequency. predetermined, the speed of the image 5. Synchronization device according to one of the Pulse repetitions characterizing the transmission of signals. Claims 1 to 4, characterized in that sequence in a comparison circuit, and by 15 the signals generated periodically at the receiving end control of the fre- queries that are dependent on the comparison have a longer duration than the sequence of generated and transmitted signals controlling the image signal evaluation.
Clock generator, characterized in that the comparison circuit measures the size of the Determines frequency difference and depending on ao of the frequency deviation at least three different signals to three control circuits (705, 716, 715) gives a coarse and The invention relates to a synchronization his fine synchronization error and the direction for working with line-by-line scanning of the synchronized state characterize that the 25 image signal transmission systems, especially for Fakerste control circuit (705) dependent on the simile devices To synchronize the gross synchronization error on the identification side of the image signal evaluation with the sending signals, periodic control signals for the image signal transmission on the side by comparing the increase in the frequency of the clock generator (201, signals, the receiving side periodically from a 202, 203) by a first amount the clock 30 evaluation device are generated, with the transmitter (201, 202, 203) provides that the second generated and transmitted signals with predetermined control circuit (716), depending on the one ter, the speed of the image signal transmission fine synchronization error he characteristic characterizing pulse repetition frequency in a VerSignalen, periodic control signals for increasing equalization, and by the comparison from the frequency of the clock generator (201, 202, 203) 35 dependent control of the frequency of the image signal by a second, compared to the first low evaluation controlling clock generator,
ren amount to the clock generator (201, 202, 203) by the German patent specification 954 885 is one supplies, and that the third control circuit (715), circuit for clock synchronization with a dependent on the synchronous state of image and sync signal existing ^ Television recording signals, a direct switch-through 40 signal mixture known. The synchronization for the processing of certain transmitted signals as peri- horizontal pulses and vertical pulses is carried out separately by means of odic control signals to the clock generator (201. For each type of pulse 202, 203) . a phase discriminator is provided to which also 2. Synchronization device according to claim 1 generated by a local clock generator, characterized in that 45 pulses are applied as a clock generator. Depending on the comparison (201, 202, 203) a voltage-controlled comparison result that the phase discriminator delivers, a reliable oscillator is used and that the frequency of the clock generator (705) and the second control circuit (716) rator is regulated. with switching elements (707, 724, 204) to A further circuit for synchronizing a circuit of a first or second control voltage 50 vibration generator is by the German Publication 1079 124 known to the clock generator (201, 202, 203). She works with one are bound. Phase comparison circuit whose capture range is 3. Synchronization device according to claim dependence on a coincidence evaluation by 1 or 2, characterized in that the clock, a control voltage is changed. A generator (201, 202, 203) is a circuit arrangement 55 between the phase comparison circuit and the voltage (202) for generating periodic timer oscillation generator contains filters by means of devices (203) which respond to certain timer pulses controlled by the control voltage and a number changed in the event of faulty synchronization so that repetitive timing signals generate the control loop formed by the overall arrangement, of which at least one of said 60 undamped predetermined pulse repetition frequency becomes the same pulse rate until natural oscillations occur. repetition frequency, and that the third control- A problem exists with synchronization circuits circuit (715) the specific transmitted signals of this known type in that the entire signals to the logic timing devices control loop in the synchronous state very stable unc (203) switches. 65 must work insensitive, im not synchronous 4. Synchronization device according to claim state, however, a fast control for syn 3, characterized in that the clock generator state is guaranteed. This own gate an arrangement (201) for generating a shafts are by the known Schaltungsan