DE1487799C - Time division multiplex transmission system for code characters bit of different coding type and winding speed - Google Patents

Description

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The invention relates to a transmission system. When it is scanned, each input terminal applies of data characters and in particular a data about a complete code character to the common transmission system for connecting incoming signal bus lines. So in the plant is during lines with corresponding outgoing lines each scan cycle one character from each transmitted over a common transmission path or a 5 input port. Having an input manifold in time division multiplex. connection a complete character to the common

When there has been a large number of data signal channels from the bus, it starts each

a common facility is processed, is the next following input port. The entrance

It is often useful to follow the signals of all channels so that a complete character is determined

Time division multiplexing has been transmitted on a common path io, in which it · an additional

admit. Each incoming line inserts its final bit into the code character and determines

Signals an input connection of the multiplex system that this final bit is applied to the bus

to. The input connections can be disconnected one after the other.

Each output port reads a full one during each scan cycle from each input port a data bit along with 15 characters from the common bus and a frame or synchronization signal to one then energizes the next output terminal, transfer common manifold. In the counter- A counter counts every read and from the issuer the data bits from the collection point are registered under the output connection until the count value of the Control of the frame signal to the input connection bit number in the characters of the connection assigned corresponding output connections corresponds to the 20 ned code. Then the next one Splits. Each output port applies the bits that energize its output port. If not available, arranged outgoing line, so that from the incoming code character inserts the input connection associated incoming line received signals related to the state of the incoming line to be restored. additional speaking flag bit. at

Multiplex systems in which one bit of every 25 registration of the flag bit brings the output to each Input port during each scan cycle port the outgoing line in the corresponding ones are very useful when the condition.

The same for all individual signal lines The counters and registers of the output connections Data code with identical signal speed applies. Such systems cannot easily be lost in order to adapt the distribution of data to the case when the output connections for the signal lines are blocked. The counter times will apply when the different encodings and the signal speed of the synchronization are regained. In addition, since multiplexing is activated again, whereby the counting value systems, the data bits of the code characters are kept interleaved for distribution, even though a regime is transmitting data bits of other channels, an overriding of the data is excluded.
averaging of line states, for example the one advantage of the invention is the creation of a free or interrupted state, in the absence of a flexible multiplex system, which can only be achieved with difficulty on signal lines with code signaling. Systems with these different codings and signal speeds are also highly dependent on the conditions that can be adapted. Another pre-maintenance of the synchronization, since a distribution, is the possibility according to the invention. Loss of conduction in the synchronization leads to erroneous states of being able to transmit the data bits to the output connections via a multiplex system in the absence of code signaling, so that the data can be transmitted to the wrong channels. to recover the station without sending any message data

The invention has set itself the task of distributing these 45 to the wrong output connections.
Eliminate difficulties. To this end, it is based on A better understanding of the invention results from a time division multiplex transmission system for code from the following description of an execution character bit of different types of coding and example in conjunction with the drawings. It shows gnal speed with a variety of input F i g. 1 in the form of a block diagram of a multi-connection for each individual coding 50 plex system for the transmission of a character type and signal speed, the incoming according to the invention,

Character bit received and a common path F i g. 2 and 3 in the arrangement according to FIG. 7, and with the input connections the details of the circuits and equipment, associated output connections, which each form the common typical input data from the corresponding input connections to the connection or buffer according to the invention,
register common path forwarded bit. The F i g. 4 in schematic form the details of the special feature recommended with the invention consists of the common transmission path or the communal in that each input connection applies the bit to the common bus and the common one of a character to the common path, fixed gear and output control equipment according to the created, if a complete character is sent to the community,

along the way, and then the next F i g. 5 and 6 in the arrangement according to FIG. 8 the

Apply one character at a time through an input. Details of the circuits and equipment that

connection initiates, and that each output connection in common is a typical output data connection

each of the applied bits of a character is registered or forms a buffer,

detects when a complete character is registered 65 · -c 1 ·

and then the next entry in each case General Explanation

of a character through an output terminal. 1 represent the data input lines 101

directs. to 104 four of a variety of incoming

Lines of the multiplex system represent. The data input lines 101 to 104 are connected to input connections or buffers 105 to 108.

The outgoing lines of the system are shown in the form of data output lines 111 to 114, connected to output ports or buffers 115-118. The data output lines the input buffer 105 to 108 and the data input lines of the output buffers 115 to 118 are connected by a common transmission path or bus, the is shown as metallic line 120. The collecting line 120 can, according to FIG. 1 a short one Be a line, but also consist of a long transmission line that uses conventional high-frequency or carrier frequency equipment such that it receives data signals at the input and restores them at the exit.

The common input control 124 is assigned in input buffers 105 to 108, as follows will be described below, controls the reading of the input buffers and the generation of the synchronization or frame signal. The output buffers 115 to 118 are assigned the common output control 125, which, as will also be described later , detects the frame signal and then initiates the distribution of the data bits to the output buffers.

The system also contains the clock generator 121, which supplies the clock pulses. In the event that the Bus 120 consists of a long transmission path, the clock 121 can be a higher-level Clock either at the outgoing or incoming end of the bus 120 and contain a slave clock at the other end which is in synchronism in a known manner is kept with the higher-level clock. In either case, the clock 121 provides a pulse source represents the simultaneous clock pulses to all input buffers and output buffers as well as the common Input control and the common output control supplies.

It is now assumed that characters signals on the incoming lines, for example, the data lines 101 to 104, are received. The input buffers 105 to 108 take the data character and store it. Assuming further that the reading of the input buffer 108 has ended, then its terminal STS outputs a signal to the common input control 124. This then applies a frame signal to the bus line 120 under control of the next clock pulse from the clock generator 121 . The common input control 124 then sends an actuation signal to the terminal STP of the first input buffer, namely the input buffer 105. This enables the input buffer 105 to receive clock pulses via its terminal CL-I which are used to read a data character via the data output line of the input buffer 105 can be used. In addition, the input buffer 105 supplies an additional flag bit which can advantageously indicate the state of the parity bit of the code character. If, however, no code character has been received via the data input line 101 , the input buffer 105 alternatively inserts a flag bit which indicates the signal state of the line 101 , for example the interrupted or free state. In any case, character bits which designate the code character or the state of the line 101 are read by the clock pulses applied to the input buffer 105 until all bits including the flag bit have been applied to the bus 120. The input buffer 105 then outputs a signal to the connection STP of the input buffer 106 via its connection STS . This initiates the operation of the input buffer 106 , which is stored in the

ίο essentially reads out the characters stored in it in the same way. The input buffers are therefore activated one after the other in order to read out one character at a time on the bus line 120.
When the reading of the last input buffer 108 is finished, this outputs a signal to the common control 124 via its output connection STS, as indicated above. A scan cycle is then completed and a frame signal is provided on bus 120 and a new cycle initiated.

Note that all input buffers each have an actuation voltage after they have been read to common input control 124 via their CK connections. This becomes the common Input control 124 indicates that none of the intermediate buffers are in use and enables common input control 124 to send a frame signal to the bus 120 and a new cycle upon completion of the reading of the input buffer 108 initiate.

Recall that each cycle is initiated by a frame signal and this signal is detected by the common output control 125 which scans the bus after distributing the bits to the output buffers as described above. Assuming that an error-free frame signal has been detected, the common output control 125 supplies an actuation signal to the terminal STP of the output buffer 115.

This enables the latter to receive clock pulses from clock generator 121 via terminal CL-I. The output buffer 125 uses these clock pulses to read and register the bits applied to its input by the bus line 120 and to store a count value for the applied bits. Since the output buffer 115 is started immediately after the frame signal, the character bits applied by the input buffer 105 are read and registered by the output buffer 115 for subsequent delivery to the data output line 111.

When the count for the bits applied by bus 120 corresponds to the number of bits of characters with the coding assigned to the first buffers plus the flag bit, the reading and registration of the bits is terminated and the output buffer 115 supplies STS via its connection Actuation signal to the terminal STP of the buffer 116. This then begins with the counting, reading and registration of the bits of the character applied to the bus 120 by the input buffer 106. In a corresponding manner, each output buffer counts, reads and registers the data bits of the corresponding input buffer until the output buffer 118 has finished counting and registering. The output buffer 118 then sends a signal to the common output control 126 via its connection STS.

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tion 125 enabled the bus 120 cut-off voltages are removed so that the

read again to determine the frame signal. normal operation continues.

When the distribution cycle ends, the

common output control 125 the frame input data buffer

signal and forwards on the assumption that there is an error 5

is free to start a new distribution cycle. A typical input data buffer is in the

Assuming now that an input buffer is not a F i g. 2 and 3 has received code characters in general form through the block, the buffer gives a 201 shown. The input data line 202, corresponding to the state of the incoming line, leads to the input data buffer 201. As explained above, the flag bit is sent to the bus line 120. Since the output buffer corresponding to a predetermined data code is assigned to the data line 202, the data for which is accepted is assigned at the same time That it is receiving a bit, it checks the flag bit in the event that there is no code start-stop code with a parity bit, which is received in characters, and returns even parity in this case,
its outgoing line in the corresponding input data line 202 leads to the deletion status. It should be noted that the counter in the output 15 input C of the SM flip-flop 241, which, as explained in the following buffer, the appropriate count value for the number of the, is normally retained in the deleted incoming bit. Hence the state of mind is located. In addition, the input data division cycle is maintained and the next diversion 202 with the first stage of the input data inbound buffer for reading the corresponding time register, which is generally actuated by block 208. 20 is set, and with one input of the oscillator

Assume now that a distribution control circuit 203 is connected.

The oscillator control circuit 203 is a bistable output control 125 the next bit on the component, of which one input with the data input bus 120 is checked and as faulty, one line 203 and the other input with the line loss of the Synchronization indicating signal is firmly connected. The output of the oscillator control provides the common output control. A circuit 203 is connected to the oscillator 204. Cut-off voltage at the connections DD in all If there is a negative voltage jump, for example output buffers 115 to 118. This prevents a distance start signal via the input line 202 from registering all data bits. In addition, the oscillator control circuit leads the common output control 125 to the 30 203 thereupon in one of its bistable states. Terminal DIS of the first output buffer 115 is brought into play. In this state, the control circuit supplies the cut-off voltage. As a result, their counter 203 is an excitation voltage to the oscillator 204, which is switched off and prevents the counting of the bits on the collective then at its output pulses with the bit line 120. Then the frequency of the incoming signals on the data common output control 125 is checked by the next following, 35 input line 202 generated. These bit pulses are used as bits applied to bus line 120 and each bit following the bit as shift pulses for input register 208 until an error-free frame signal is permanently used. The oscillator control circuit 203 remains switched on. Then the common out of this state until a negative voltage jump removes the cut-off voltage from the input via the input line 209 until a negative voltage jump is received by the end DIS of the output buffer 115 put on stand. This makes the oscillator 204 bits. However, the registration of the bits is prevented, switched off and no more shift pulses are applied since the input register 208 continues to apply the switch-off voltage to the connection DD.
located. As stated above, the data input

After the corresponding number of bits has been counted through line 202 to input register 208. This has output buffer 115, as above in a number of stages, which are correspondingly described in FIG. 2, output buffer 116 receives a signal corresponding to the elements des for the input line 202 so that these are numbered for counting the next bit provided start-stop code. How series passes. The output buffers thus provide one that will be explained in the following, all count values of the bit distribution cycle are, however, without 5 ° stages normally in the deleted state. From right to left one of the bits applied to bus 120 is the first stage of enrollment. Note that during this output register 208 is designated by STP and corresponds cycle every outgoing line in the signal state to the start bit of the start-stop code. The following is held, which in the event of loss of synchronization the stages are denoted by 1 to N , and their number was present. 55 is equal to the number of message elements of the start

At the end of the bit distribution cycle, the stop code is. Stage N is followed by stage P, which in turn corresponds to the output buffer 118 a signal for the common parity bit in the start-stop code, and the same output control 125, which in turn corresponds to a stop element at stage SP, although the bus 120 checks applied bit. Assuming the start-stop code assigned to the input line 202, it is assumed that the second bit of an error-free frame 60 can contain more than one stop element.
Bit jst, another distribution counting cycle is started since the data input line 202 is initiated, although the bit registration is still prevented by input register 208 or, more precisely, with the stage. When this cycle is completed, SP is connected via line 206, this clears the common output control 125 again in the common application of a marking potential of the activity and in the event that the third bit 65 data input line 202 to the stage SP and a The error-free frame bit is,. It is assumed that the voltage jump at the output of the oscillator 204 is that the system is again in synchronism, and the SP applied to the terminals DD of the output buffer from a low to a high value. If on the other hand a break potential together

is applied with a shift pulse voltage jump to the stage SP , this is set. The stage SP thus stores a pause bit when it is set and a marking bit when it is cleared. The same applies to all other stages of the input register 208.

Assume now that a start-stop character is received from data-in line 202; when the start bit is received, the corresponding negative voltage jump on the line brings the oscillator control circuit 203 into the first bistable state, and the oscillator 204 is set into operation, as described above. The oscillator 204 then delivers a shift pulse in the theoretical midpoint of the starting element and, since it is operated at the bit frequency of the incoming line, in the theoretical midpoint of each subsequent element. The level SP of the input register 208 is set in the theoretical midpoint of the start element. When the first message element is received, the oscillator 204 generates the next shift pulse in its theoretical center, which brings the stage SP into the state corresponding to the first element and introduces the start pulse into stage P by setting this stage. In a corresponding manner, each of the following message elements, the parity element and the stop bit are entered in the SP stage of the input register 208 and each preceding element in the register is shifted on until the start bit in the STP stage and the message bit in the 1 stage to JV, the parity bit in the P stage and the first stop bit are stored in the SP stage.

When the start bit enters the STP stage, it is switched from the deleted to the set state. This causes the "0" or clear output terminal of the STP stage to go from high to low voltage. This negative voltage transition at the “0” output of stage STP is transmitted to line 209 and thus to oscillator control circuit 203. This is then, as described above, reset to the original state, whereby the oscillator 204 is switched off and the application of shift pulses to the input register 208 is ended. The input of data bits into the input register 208 thus stops until the next negative or pause transition on the data input line 202.

When the start pulse enters stage 5TP and takes it from the cleared to the set state, the set or "!" Output terminal of stage STP goes from low to high voltage. This high voltage state is passed via line 210 to delay circuit 211 and, after a predetermined delay, to an input of AND gate 212. The other inputs of gate 212 are connected to lines 214 and 215.

Line 214 is the "not" clock line leading to the output of clock 401 in FIG. 4 leads. The clock generator 401 delivers normal clock pulses on its output clock line and on its "not" - Output clock line inverted clock pulses, d. that is, the pulses on the "not" clock line correspond the pulse pauses on the clock line. The pulse repetition frequency of the clock 401 is determined the bit frequency on the common bus and is therefore slightly higher than the total signal frequency, required for the signals received on all input channels.

As described above, line 124 is positive during the interpulse clock period to gate 212 which is consequently actuated during this period. This causes that the subsequent operation of the input register 208 and its reading are not during others Operations of the input data buffer 201 occur,

ίο the ¹ are initiated by the clock pulses.

It has now returned to gate 212. The input line 215 leads to the "0" or clear output of the i? M flip-flop 321. As will be described below, this flip-flop is in the cleared state when no data is read out to the common bus. If it is therefore assumed that no data is being read out, the i? M flip-flop 321 is in the cleared state, the line 215 is at a high potential, and the gate 212 is activated. Depending on the delayed voltage transition from the stage STP , the output of the gate 212 is brought into the high potential state. This potential is passed on to the clearing input of the STP stage and brings it back to the clearing state.

Resetting the STP stage to the quenching state brings its "0" output to the high potential state. This positive voltage transition is applied to the monopulser 218, which then generates a positive pulse at its output. This positive pulse travels via line 219 to the clear inputs of stages 1 to JV, P and SP in input register 208. As a result, all stages of input register 208 are returned to the clear state in order to be prepared for the next reception of signals via data input line 202 . The output pulse from monopulser 218 indicates that the start-stop character has been stored in input register 208 and represents the read or gate pulse. This gate pulse runs from the output of monopulser 218 via line 220 to one in FIG. 3 gates shown as block 301. In general, the gate 301 is used to read the character from the input register 208 into the bus register shown as block 320.

Viewed from right to left, bus register 320 contains levels 1 through JV, which correspond to levels 1 through JV in input register 208, and level F. Levels 1 through JV are assigned to the data bits in the start-stop code and the F is a frame bit which is added to the code character as will be described below. The flag bit entered in level F depends on several conditions

the parity bit, the status of the data input line 202 and certain from this received encodings.

Gate 301 contains AND gates 311 to 314 and 315 to 318. Let us begin with the gates 311 to 313 considered. One input of each of these gates is connected to line 220, which, like stated above, which supplies gate pulses. The other inputs of the gates 311 to 313 lead via the Lines 221 to 223 to the "!" Outputs of the

Levels 1 to JV. The outputs of gates 311 to 313 lead via OR gates 302 to 304 to the Setting inputs of levels 1 to JV of bus register 320. Gates 311 to 313 and the

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between these, not shown, gate voltage on line 215 from gate 212,

thus depend on the gate pulse to prevent reading of the input register,

on the line 220 the stages 1 to N of the collective The function of the output connection CK should continue

line registers 320 as described below.

Levels 1 to N of the input register 208 set 5 When the .RM flip-flop 321 is in the setting. As a result, a pause bit stored in register 208 is located in a level of the input status, and its “1” output connection is read out and brought to a high voltage, which is applied to the AND gate and in a corresponding level of collector 326 . Gate 326 forms line register 320 stored. Read-out gate that is activated when the RM flip-flop 321

The gate 301 also contains the AND gate io is operated in order to read out the states of the first stage in 315 to 317, of which a bus register 320 is read out in a similar manner. The out input is connected to line 220. The input of gate 326 goes to high voltage, the inputs of gates 315 to 317 are over when the first stage is cleared, and to low lines 231 to 233 with the "0" outputs of the voltage when the first stage is set. Connected at levels 1 through N of input register 208. 15 Storage of a marker bit in the first stage Since the output signals of gates 315 to 317 via the bus register 320, a positive-OR gate 306 to 308 becomes the clear inputs tive condition on line 328 and then on that of stages 1 to N of the bus register 320 is given connection BI which, as shown in the following, the gates 315 to 317 mark bits carry the explanation with the common bus connected in the stages 1 to N of the input register 208 to 20 direction.

corresponding stages in the bus register. The "O" output terminal of the .RM flip-flop 321 320. As will be described below, they are also connected to an input of the OR gate 314 and 318 with the corresponding flag bit 325 connected. Since i? M flip-flop 321 enters stage F of bus register 320. is normally in the deleted state and in summary it results that after input 25 its "0" output is at high voltage, the start-stop code character in the input register changes this voltage via the OR gate 325 to Lei-208 and if that Bus register 320 not transmitted to device 340. The other input of the gate is read out, the input register 208 via the ters 325 is connected via the line 327 to the clock gate 301 in the bus register 320 output output. If the AM flip is read and that register 208 in Er-flop 321 is cleared, waiting for the next signal from the data input but output line 340 of gate 325 on line 202 is held high voltage reset so that the creation of will. Clock pulses is prevented.

Reading the bus register 320 to when the AM flip-flop 321 is set and

the common bus takes place after 35 _se goes to low voltage in the "0" output

the input data buffer lying before the buffer 201, consequently the high one applied to the line 340

fer has finished reading or, if the input voltage has been removed. Then over the line

Input data buffer 201 is the first buffer after device 327 applies clock pulses through the gate

the common controller passed its frame signal to the 325 on line 340.

has created a common manifold. Is at termination 40, as described below, the supply of the reading for the previous buffer i by? M flip-flop 321 applied high clamping Or, if the data buffer 201 of the first buffer is, _n ung simultaneously with the arrival of the Vorderbei applying the Frame signal on the collecting edge of the clock pulse on the line 327, a positive pulse is removed from the connection STP. The first transition from low to high received and thus applied to line 322. 45 Voltage on line 340 does not occur until Be- The positive pulse on line 322 occurs at the beginning of the next following clock pulse. The setting input of the .RM flip-flop 321 is performed and the AM flip-flop 321 is, however, for a full bit period brings the flip-flop into the setting state, before this transition was set, and it should be remembered that the flip-flop was before Hch the gate 326 has been actuated. Accordingly, the readout is in the erased state. In addition, the state of the first stage of the collective bar is read, the pulse on line 322 is read out via line register 320 before the transition to the clear input of M flip-flop 323 occurs on line 340. That first bit will give. As a result, the M flip-flop 323, which is connected via the line 328 and the connection BI to the normal common bus line according to the following description, is applied,
55 The line 340 leads to the shift pulse input was offset. Note that an output of the bus register 320 and for setting M-flip-flops 323 with the bus register 320 input of the M flip-flop 323. The above-mentioned, and specifically associated with the step F is. The next shift pulse, that is, the first shift, ensures that when shifting pulses are applied, the transition from low to high voltage on the level at level F is brought into a state 60 line 340, so sets the M flip-flop 323 and is , which corresponds to the state of the M flip-flop 323 and delivers the first shift pulse for the busbar. processing register 320. This shift pulse is therefore

It should now be remembered that the beginning of the marking bit from the M flip-flop 323 in stage F, read-out pulses on line 322, the -RM flip- shifts the flag bit from stage F to flop 321, so that its "0" output is 65 level N and the state of each level is lower than each level. Voltage is applied to the outgoing stage, so that the state of stage 2 output connection CK and line 215 applied to stage 1 is shifted. Then the second will be. As described above, the low bit from the bus register 320 toggles via the

Read gate 326 for common bus.

When the next successive shift pulse is applied to the bus register 320 , each bit is shifted forward in a corresponding manner. Since the M flip-flop 323 is now in the set state, a pause bit is entered in the F stage. At the same time, the marker bit originally written in step F is shifted to step N.

With each subsequent shift pulse, the marker bit originally stored in the M flip-flop 323 and entered into the F stage is shifted from the N stage to subsequent stages. In addition, if the M flip-flop is set, 323 pause bits are written into stage F and, following the marker bit, shifted through the stages. If the code character followed by the path bit is shifted through the bus register 320 , a marker bit immediately following the flag bit is shifted through, and the subsequent stages are filled with pause bits. The code character is thus shifted further through the bus register 320 until the flag bit enters level 1 and the marker bit in the level and the subsequent levels are filled with pause bits.

At the end of the reading of the flag bit by gate 326 , the next shift pulse transition is applied to line 340 , whereby the marker bit is shifted to level 1 and all subsequent levels are filled with pause bits. The “1” output connections of all subsequent stages are therefore at high voltage together with the “!.” Output of the M flip-flop 323. These terminals are all connected to AND gate 345. The output of AND gate 345 therefore goes to a high voltage, which is applied to the clear input of i? M flip-flop 321 . This flip-flop is accordingly cleared, switches gate 326 off, applies the high voltage again via OR gate 325 , switches gate 212 on again and applies the high voltage to terminal CK again. Note that this erasure of the /? M flip-flop 312 occurs simultaneously with the application of the leading edge of the shift pulse, since this shift pulse has shifted the marker bit out of stage 2 to actuate gate 345 and to clear the RM flip-flop 312 . The line 340, which was at a high voltage due to the shift pulse, is therefore kept at a high voltage by the i? M flip-flop 321 .

The output terminal of the AM flip-flop 321 is also connected to the monopulser 346 . When the AM flip-flop 321 is cleared, the positive voltage transition at its "0" output goes to the monopulser 346, which generates a positive pulse at its output. This is applied to the output terminal STS via the line 347.

As described above, the STS terminal of each input data buffer is connected to the 5TP terminal of each subsequent input buffer with the exception of the last buffer, the STS terminal of which is connected to the common control. As a result, when the read-out is completed and when the /? M flip-flop 321 is reset to the cleared state, the monopulser 346 sends a positive pulse to the STP terminal of the next buffer or to the common control. As a result, the reading of the next buffer is initiated in the same way as described above with reference to the input data buffer 201 .
The positive pulse at the output of the monopulser 346 is also fed via line 348 to gates 242 and 244 (FIG. 2). As described above, the SM flip-flop 241 is normally in the cleared state. That with his

ίο »(k output terminal connected to gate 242 is then operated. On the other hand, the gate 244 connected to the" 1 "output terminal is switched off. In the normal state thus the pulse is transmitted on line 348 via gate 242 to line 243. The conduit 243 is connected to the OR gate 305 and the OR gates 306 to 308. Since the output of the OR gate 305 is connected to the setting input of stage F and the outputs of the OR gates 306 to 308 are connected to the clear inputs of stages 1 to N are connected in the bus register 320, the step F is brought into the set state, and the stages 1 to N are returned to the erased state. Thus, the level F is at the end of reading out usually in the set state, and the stages 1 to N of the Bus registers 320 are normally reset to the cleared state in preparation for the next reading of the character in input register 208. In addition, the i? M- Flip-flop 321, if it is in the cleared state, ready to respond to a further pulse from the connection STP in order to read out the character stored in the bus register 320 for the common bus.

If the operations described above are summarized, the information elements of the code character received and stored by the input register 208 are read out and transferred to the bus register 320 . In this process, the start and stop elements are stripped off, the parity element is checked as described below, and a new flag bit is entered in bus register 320 . Then on the basis of a signal from the previous input data buffer or from the common control, if the buffer 201 is the first channel, the message elements and the flag bit are read out to the bus. At the end of this process, a signal is transmitted to the subsequent input data buffer so that it can begin reading. Each input buffer is assigned a plurality of successive time slots, the number of which corresponds to the number of message elements for the code character assigned to the input line of the buffer plus a flag bit. For each read cycle, the input buffers send a character to the bus one after the other.

Insertion of the flag bit

As indicated above, the flag bit entered into bus register 320 depends on the input code characters, the state of the input line, and / or the parity bit received from input register 208. In the event that the input line is in the free marking state

13 14

finds, a "1" or pause bit is transmitted unchanged. Since all message elements of the "Enter book into level F of bus register 320 " characters are marker bits, the "0" are given. This ensures that with the on-outputs of levels 1 to N in the input register 208 holding state with "0" - or the marker bit in at high voltage. These outputs are all connected to stages 1 to N with a "1" or pause bit continuous 5 to gate 251 , so that its output is of course input to stage F, which goes to high voltage via the OR -Gate to indicate the free state of the line. However, if 252 is transmitted to line 253. The line a »rub out« or »letters« - 253 in turn leads to an input of the AND - (“letters”) character that is received only in May gate 318 in gate 301. The other input contains kier message elements, a "0" or io of the AND gate 318 of the marker bit connected to the line 220 is input into the F stage. An "off, wipes the high voltage on the line 253 " can therefore clearly be distinguished from a free gate 318 in the position of being able to distinguish the gate pulse through the conduction state. allow and via the OR gate 309 to delete

If the incoming line is to be passed on in an input of level F of the bus register 320 longer "interrupt" or pause status 15.

is located, an "O" bit is entered in the F stage. So if an "erasure" - or "letters" -

While characters are being received during the "interrupt" state, the marker bits are also "1" or pause bits in levels 1 to N and elements in bus register 320 and a "0" or marker bit in level F inscribed marking flag bit inserted in level F,
ben. If an "Empty" - ( "blank") character empfan- ₂₀ when an extended "interrupt" - or gen, all message elements pause pause is received in the so actuated anelemente are, a "1" - or breaks -Bit entered the oscillator stage F in the catchy marker-pause transition. As a result, the “empty” control circuit 203, which then sends the oscillator 204 characters from the extended “interruption” shift pulses to the input register 208, or the pause state can be distinguished. 25 leaves. This leads to the entry of the pause bit in the

During normal signal sequences, a "1" bit becomes input register 208, since input line 202 is entered into stage F when the parity bit of the is paused. Accordingly, the end of the start-stop code is a "0" or marker bit, and a simulated pause start of a character interval is an "O" bit if the parity bit is a "1" or a bit in the STP stage introduced, and the monopulser is pause bit. This normal signal state comprises 30 218 outputs a gate pulse to line 220. All cases with the exception of those cases in which a Then gate 301 takes the pause bit from the "free", "interrupt", "letter" or input register 208 and puts it in the collective "empty" character is received. line register 320 a.

If one now assumes that the input line 202 is free in the "interruption" state, the oscillator control circuit 203 does not switch on the oscillator 204, line 202 contains the simulated input. Consequently, no character entered into register 208 becomes a stop element. Pause bit entered into the input register 208. As a result, a pause bit is introduced into the stage SP of the input and the monopulser 218 does not supply a gate pulse to the input register 208 . Its "1" output to line 220. It should be remembered that at is then brought to high voltage, which sends a pulse to line 348 via OR gate 252 to line 253 upon completion of the readout going over the gate. The gate 318 will therefore go to the line 243 when the 242 is applied. This pulse is then excited by the gate pulse and gives a marking bit to the gates 305 to 308 and gives marking to the level F. Accordingly, based on the bit to the levels 1 to N and a pause bit in the "interruption" Signal pause bit in the stages 1 stage F. So if the input line 202 is in 45 to N of the bus register 320 and a free state and the application of a marker bit is entered in the stage F.
Gate pulse to the line 220 is prevented, because the "interruption" state of the input

. the levels 1 to N in the register of hand, "a series of silence bit kept erased state and 208 Stage F in the set state when it is determined are the"! "- outputs of stages 1 next reading of the bus register 320 50 to N. This "1" outputs are at high voltage levels are accordingly to the corresponding N all connected to the gate 255 1, the output of tag bit is read out, followed by the accordingly located in the high voltage. This chip-level F stored pause flags bit. In the case of loading voltage is one input of the aND gate 258 zuendigung of reading out the mono Pulser 346 is performed. the other two inputs of the aND turn a pulse via the gate 242, and there are 55 gate 258 with the "!" - outputs of stages P are reconnected tag bit in the stages 1 to N and and SP in the input register 208, since only a silence bit into stage F entered silence bit inserted into the input register 208..

If one now assumes that an "erasure" - or has been, these "1" outputs are also received on "letters" characters, this leaves a high level of tension. Then the output of the start element gate of the character, the oscillator control circuit 60 258 goes to high voltage, which actuates the oscillator 204 at an input of the device 203. Accordingly, AND gate 259 is supplied. Since the other is entered, after the character has been completely entered into the input of AND gate 259 via line 230, input register 208 and the start element is connected to line 220 , the one that is written into stage STP becomes monopulser monopulser 208 The gate pulse generated is actuated via the 218 , as described above, in order to apply a gate 65 gate 259 to the setting input of the SN flip-flop pulse to the gate 301 . Accordingly applied 241 . The receipt of the first transition, the message elements of the character from the "interrupt" signal causes the input register 208 to the bus register 320 position of the SiV flip-flop 241. Its "0" output

15 16

then goes to low voltage and this supplies gate 255 with high voltage at its output gate 242, and the "!" output goes to high gear. This is applied to the inverter 257, the Voltage and actuates gate 244. then low voltage to AND gate 256 over-

It should be remembered that an "interrupt" carries and switches this gate off. The gate 256 signal represents an extended pause condition. 5 therefore applies a low voltage to the OR gate If accordingly the character described above is 252. Since the message element has not ended any marker bit interval, the stages are on, the gate 251 supplies low voltage to input register 208 and cleared the oscillator control output, as explained above, and this low circuit 203 is returned to its initial state. The voltage is applied to the OR gate 252, as explained above. As the tingangsleitiing lays io. All the inputs of the gate 252 are therefore on 202 in the pause state, if there is no post-low voltage, the marking-pause transition which then carries over to the line 253 is present. This line leads to the input which could actuate the oscillator control circuit 203. Inverter 350, the high voltage at the input. As a result, the oscillator 204 is not returned to the gate 314. The gate 314 is actuated, switched in order to apply further shift pulses to the input 15 and there its other input with the line 220 register 208. After the first character is connected, it lets the gate pulse through and interval are accordingly the following pause bit leads it to the input register 208 via the OR gate 305 for setting, and at the input of stage F of the bus register 320. the monopulse 218 is generated no subsequent When receiving the start-stop “empty” character who gate impulses. 20 the pause bit in levels 1 to N of the sam-

If one now recalls that upon completion, line register 320 was entered and a pause in reading from bus register 320 the flag bit is introduced into stage F.
Monopulser 346 is actuated, so the assumption that a start-stop code character input pulse which is applied to the line 348 is received that no "empty" or "book does not pass through the gate 242, there If this gate is 25 letter "-sign, the gate 251 is neither switched off by the deletion of the .W flip-flop 241 nor the gate 255 activated. When the exit is. When the gate 244 is actuated, however, the Im- of the gate 255 is at a low voltage, pulse on the line 348 via this gate to which the inverter 257 sends a high voltage to the AND line 245. This line is connected to gate 256, which is actuated when the emp-OR gate 309 is connected, so that the start-stop character a marking parity bit _{that is caught by the pulse 30 clears the level F.} Line 245 is also included. Stage P of input register 20 is connected to OR gates 302 to 304, which are cleared. As a result, low voltage is applied to your stages 1 through N due to the pulse on the "!." Input to AND gate 256, set line 245. So even though after reading the "interrupt" signal, there are no gates at the OR gate 252 after reading the low voltage. Since the other inputs of the OR gate impulses are applied to the gate 301, which are also at a low voltage, as described above for the setting of the STV flip-flop 241 and the one described below, the line 253 goes to the low-voltage actuation of the gate 244 to input voltage, and inverter 350 turns the AND gate pause bit on in stages 1 through N of bus 314, as discussed above. The gate pulse is passed to register 320 and a marker bit in stage F. 40 that is from gate 314 through gate 305. With each subsequent readout, stage F corresponds to and sets. Accordingly, when a flag parity bit input to bus register 320 from input register 208 emp flag indicates the "break" state. will catch a break flag bit in the

Upon completion of the break condition, stage F of bus register 320 goes inserted, input line 202 to tag condition 45 if break parity bit from input return. This pause marking transition is received at register 208, and the "1" output, clear input of STV flip-flop 241, is applied. The stage P at high voltage and actuated the flip-flop is cleared, the AND gate 244 and gate 256 turns on, since the inverter 257 high span and the AND gate 242 on again. In this way, the circuit is applied to the original input 50 at the other input of the AND gate 256. As described above, the high voltage level is returned via the OR signal before the "interrupt" is received at the output of gate 256. Gate 252 and line 253 to gate 318

If one now assumes that a "blank" character leads. This gate is accordingly switched on and received, so when the start is received, the gate pulse is activated via the OR gate 309 element of the "empty" character, the oscillator control 55 to the clear input of stage F of the bus circuit 203, which then actuates the oscillator 204 registers 320. So if a pause parity bit turns on from. The "empty" character is then received in the input register 208, a Mar input register 208 is entered, and the introduction of the kier flag bit in the stage F of the bus of the start element in the stage STP actuates the register entered.
Monopulser 218. This delivers a gate pulse 60

to the gate 301, which then all pause bits from the common input control
Input register 208 to the bus register

320 transmits. In Fig. 4, the line 403 represents the common

The "empty" character contains a stop pulse, the busbar. It is connected to the output of the so that the stage SP low voltage to the AND-65 OR gate 402. The inputs of gate 258 are there, which turns off the gate OR gate 402 is connected to the BI terminals and supplies low voltage to OR gate 252 of the input data buffer and the common inputs. Since all message elements are pause bits, gang control 406 connected. Hence this leads

17 18

OR gate 402 which transfers the clock line to the OR gate 411 from the input data buffers,

read data to the bus 403 and besides- Since the SW flip-flop 408 has been cleared, and the

the one frame pulse from the common input from its "1" output to the OR gate 411

gear control 406 as described below. applied positive voltage has been removed

The common input control, which as block 5 is a positive clock pulse transition to the setting

406 in FIG. 4, as already mentioned, the output of the SW flip-flop 408 is transferred. The setting

the frame bit after reading out all inputs of the flip-flop brings its "1" output again

data buffer on. This frame bit is alternately at high voltage, and the monopulser 416 is there

a mark bit and a pause bit. So if at the end a positive impulse is sent to its output

of a read-out cycle the frame bit a marking line STP-I. As described above, this line is

is impulse, the frame bit is rewritten at the end of the and sent to the first input data buffer

The first readout cycle will be a pause pulse and then and there the i? M flip-flop will set the readout

initiate another cycle at the end of the next readout cycle. Since the SW flip-flop 408 is now

Marking pulse. is set, its "0" output goes to low voltage

It should be remembered that after reading 15 voltage and the gate 409 switches off. This will

of the last buffer that the monopulser 346 received from the common input control 406

The corresponding monopulser terminates a pulse on its delivered frame pulse,

output connection STS-N applies. It is still important at the end of the read cycle of the input buffer

reminds that when the readout is completed by, all CK connections are again at high voltage

each input buffer that corresponds to flip-flop 321 , and the last input buffer supplies one

The corresponding ÄM flip-flop is cleared and the CX-An pulse is sent to the connection STS-N. Accordingly, will

ends with high tension. After switching off the SW flip-flop 408 is cleared again, the state

when reading the input buffer, all CK- An of the SB flip-flop 410 are reversed and another

It closes at high voltage, and a pulse frame bit is generated, the state of which corresponds to that of the preceding-

to the STS connection of the last input data 25 is the opposite of the frame bit, the

buffer created. Manifold 403 created. After that, at the next

According to FIG. 4, the most clock pulse to the CK connections, the frame bit ended, and the

lines leading to AND gate 414 in first input buffer is started to the next

the common input control 406 connected. Initiate readout cycle.
In addition, the 30 leading to the connection STT-N is

Line connected to AND gate 415 . When common exit control
all CK lines are at high voltage

the output of the gate 414 to high voltage and the signals given to the bus 403 operate the AND gate 415. As a result, the pulse is distributed to the various output data buffers from the terminal STS-N through the AND gate 35 and the common output control, the 415 for the clear input of the SW flip-flop 408 is shown as block 418 . When the SW flip-flop 408 goes into the clear state control 418 determines whether the frame bit has been brought, its "1" output connection goes to a low voltage and removes the voltage previously connected to the alternating mark and pause bit and when the frame bits are error-free, OR gates 411 conducts applied high voltage. At the same time, the first output data buffer is operated, so that the "0" output of the SW flip-flop 408 goes in time to read the first character of the scanning cycle. For high voltage, and this transition is sent to the case that the frame bits do not alternate, the toggle input of the SB flip-flop 410 is overridden by the common output control 418 . The high voltage at the “0” output of the following bit, until the correct, alternating sequence of SW flip-flops 408 is also detected at an input 45. This "slip" of time slots of the AND gate 409 is transmitted. restores the correct framework.

By applying the positive voltage over- The operation of the common output control

input to the toggle input of the SB flip-flop 410 , 418 is initiated when the last output data

whose status is buffered in the other status and receives its data character. This buffer

changes. So if the flip-flop was cleared, it will then send a signal via the connection STS-N to 50

now set, and vice versa it is deleted, common output control 418, as in the following-

if it was previously set. Assume that it is being described. The signal represents the line

the SB flip-flop 410 brought into the cleared state 419, the ECC flip-flop 420 a. Since also

the resulting high voltage on line 419 becomes the toggle input of the ST flip-flop

his "0" output leads to the AND gate 409 reasonable 55,421 whose state is reversed. The

lays. The output of the AND gate 409 then goes to Sr-FIipflop 421 stores the alternating input

to a high voltage, which protruded to OR gate 402 of the frame bit. When the Sr flip-flop

will wear. The voltage runs through the gate, so 421 is in the set state, a mar-

that a marker frame bit is expected on the bus kier frame bit, and if the STV flip-flop

403 is applied. On the other hand, if the SB flip-60 421 is cleared, a pause frame bit is generated.

flop 410 is brought into the setting state, is waiting. Accordingly, if the ST flip-flop 421 is

whose "0" output is on low voltage, so that is and a marking frame bit over the Sam-

Also receiving the output of gate 409 low voltage line 403 turns the high

supplies. Accordingly, a low voltage is applied to the voltage at the output terminal "1" of the ST flip

Gate 402 is applied, which then a pause frame- 65 flops 421 the gate 426 , which then the marking-

Transmits bit to bus 403 . Transfers frame bit to OR gate 428 . The

At the beginning of the next clock pulse from clock OR gate 428 , an actuation voltage is applied

Transmitter 401 is a positive voltage transition via the setting input of stage A of the shift register

430. Although level A is not set until a shift pulse is applied to it, the energization of the set input indicates that the correct frame bit has been received. On the other hand, when the 5T flip-flop 421 is cleared and a pause frame bit is received from the bus 403, the "0" output terminal of the flip-flop 421 turns the gate 427 on. Inverter 425 reverses the pause frame bit and passes it through actuated gate 427 and OR gate 428 to the set input of stage A of shift register 430. This indicates that the correct frame bit has been received.

Let us now return to the setting of the ECC flip-flop 420. The high voltage at its output terminal "1" operates the gate 442. The "not" clock pulse is then transmitted as a shift pulse via the gate 442 and the OR gate 443 to the shift register 430. The above-mentioned actuation of the setting input of the stage, together with the shift pulse, leads to the setting of stage A. At the next clock pulse, the OR gate 442 ^ sends an actuation pulse to the clear input of the ECC flip-flop 420. Its "0" output goes then to high voltage, and the monopulser 455 then applies a pulse to the output terminal STP-I . This indicates the end of the frame pulse and the pulse on terminal 5TjP-I initiates the operation of the first output data buffer, which reads the first data character of the cycle. When the ECC flip-flop 420 is cleared, a high voltage is also applied to the OR gate 422. This makes the output of the OR gate 422 independent of the clock pulses. In addition, when the £ CC flip-flop 420 is cleared, the AND gate 442 is turned off and disables the "not" clock pulses to the shift register 430.

In the event that synchronization has been lost and incorrect frame pulses are received the common output control 418 checks the following time slots as long as until a bit with the correct state is found. However, this process will only be initiated if two consecutive faulty. Frame bits are determined.

Assuming now that ST flip-flop 421 is set by a pulse on line 419 and a pause frame bit is received, gate 426 is off but no high voltage pulse is passed from bus 403 to it Gate created. As a result, the output of OR gate 428 goes low so that the inverter provides an actuation signal to the clear input of stage A of shift register 430. Then, when the "not" clock pulse is applied through gates 442 and 443, the stage is cleared. On the other hand, when the 5r flip-flop 421 is cleared in anticipation of a pause frame bit and a marker frame bit is received, the gate 427 is operated as described above, but the inverter 425 applies a low voltage to that gate. As a result, the output of the OR gate 428 is at a low voltage, and the inverter 429 applies an actuation voltage to the clear input of stage A. The stage is thus cleared when an incorrect frame bit is received.

When the next following frame bit is to be expected, a pulse is again applied via line 419 to the toggle input of ST flip-flop 421 and its state is reversed. If the correct pulse arrives now, the stage is set and the circuit continues to work in the normal way. However, if an erroneous frame bit arrives, an actuation voltage is applied through inverter 429 to the clear input of stage A in the same manner as described above. When the "not" clock pulse is received, the shift pulse applied by the OR gate 443 brings stage / 1 to the deleted state and shifts the previous deleted state of the stage to stage B.

When the two stages A and B of register 430 are in the clear state, their "0" output terminals go high and switch AND gate 450 on. This gate is in turn connected to an AND gate 451 and 452, respectively. the

so other input of AND gates 451 and 452 is connected to the clock line. As a result, the the next clock pulse the AND gate 451 to clear the DD flip-flop 439 and the DS flip-flop 434 to be set.

The "1" output of the cleared DD flip-flop 439 goes to low voltage. This voltage is applied to terminal DD , which is connected to all output data buffers. As described below, when the voltage at the connection DD is low, the input gate of the registers in each output data buffer is switched off, so that the registration of subsequently received characters is prevented.

Let us now return to the setting of the DS flip-flop 434, whose output terminal "0" then goes to low voltage. This voltage is passed on to the DIS terminal, which is connected to the first output data buffer. As will be explained in the following, the application of the low voltage to the terminal DIS switches off the first output data buffer so that it cannot initiate the counting of the incoming data bits and consequently cannot advance the readout cycle and the subsequent actuation of the second output data buffer. With the DS flip-flop set. 434 the read cycle of the output data buffer is stopped.

When DS flip-flop 434 is set, its "1" output also goes high and operates gate 444.
The clock pulse that set DS flip-flop 434 and cleared Z) D flip-flop 439 also cleared £ CC flip-flop 420, as described above. When the first output data buffer is switched off, however, the corresponding pulse supplied by the monopulser 455 for actuating the first output data buffer does not initiate the readout cycle. However, although the first bit is not registered by the first output data buffer, it is checked by gates 426 and 427 since the 57 flip-flop 421 remains in its previous state. If there is still no correct frame bit, the next "not" clock pulse clears stage A of shift register 430 again when gate 444 is activated. The common output control 418 then leaves

the output data buffer is switched off and another data bit passes. The next bit of data is then checked again and this process is repeated.

Assuming now that a data bit corresponding to a correct frame bit is detected, an actuation voltage is applied to the setting input of stage A. The "Not" clock pulse then applied via gate 444 and OR gate 443 sets the stage and brings its output to high voltage. This turns on gate 433 , which clears DS flip-flop 434 when the clock pulse is received. When the flip-flop 434 is cleared, the counting operation of the first output data buffer is initiated and the output data buffers store a count of the read-out cycle, although the registration of the characters is prevented because the DD flip-flop 439 is kept in the cleared state. In addition, when DS flip-flop 434 is cleared, its "1" output goes to low voltage and switches AND gate 444 off. The application of shift pulses to the shift register 430 is therefore terminated, so that the display of the data bits received from the bus 403 ceases.

At the end of the read-out cycle, the last output data buffer again sends a pulse to line 419, which sets ECC flip-flop 420 and reverses the state of ST flip-flop 421. Thus the next frame bit is checked in the same way as described above.

If the frame bit is incorrect, stage A is cleared again and the process described above is repeated. The DS flip-flop 434 is set when two consecutive incorrect frame bits are detected, and the common output control 418 then allows time slots to pass in order to detect an error-free frame bit.

However, assuming a second healthy frame bit is being displayed, the "no" clock pulse provides a shift pulse to shift register 430 as described above, and levels A and B are set. The following clock pulse then clears the ECC flip-flop 420 and thus initiates a new read cycle. Since the DD flip-flop 439 is further cleared, however, the data characters are still not registered by the output buffers.

At the end of this read-out cycle, the last output data buffer again sets the IsCC flip-flop 420 and switches the state of the ST flip-flop 421 . Then the next frame bit is checked. Assuming that this frame bit is error-free, the "no" clock pulse sets stage A and shifts the previous set states of stages and B to stages B and C. Thus, all stages in shift register 430 are set. This is checked by AND gate 437 , the inputs of which are connected to the "1" output terminals of the stages, B and C. Since these terminals are all high, gate 437 turns gate 438 on . At the same time, the clock pulse is applied to gate 438 . Gate 438 then sets DD flip-flop 439 . This causes the "!." Output of DD flip-flop 439 to return to high voltage, and when terminal DD is high, the output data buffers are caused to register the data characters. Thus, if the circuit falls out of synchronicity, three consecutive error-free frame bits are required to bring the circuit back to normal.

Output data buffer

In the F i g. 5 and 6, an output data buffer is indicated generally by block 501. All output data buffers are essentially identical with the exception that the first output data buffer shows minor deviations, as described below.

Reading out by the output data buffer 501 is initiated by a pulse at the connection STP which is supplied by the preceding output data buffer. In the first buffer, the connection STP is connected to the corresponding connection in the common control, which, as described above, emits a pulse to the connection STP in order to initiate the reading of the first output data buffer when the system is in synchronism. In any case, the pulse at the ' STP terminal goes via line 515 to the setting input of the MS flip-flop 502, which is then set. This takes place at the beginning of the clock pulse, so that the MS flip-flop 502 is set simultaneously with the beginning of the first bit of the code character to be read.

When the MS flip-flop 502 is set, its "1" output terminal goes to a high voltage, which is applied to an input line of the AND gate 507 . Line 519 also leads to gate 507 and is connected to positive battery voltage in all output buffers with the exception of the first buffer. In the first buffer, line 519 is connected to port D / 5. As explained above, when the equipment is in synchronism, a high voltage is applied to the terminal DIS by the common output control, and the first output data buffer is activated. In either case, under normal operating conditions, line 519 will be high so that gate 507 will be on. The third input of gate 507 leads to the "not" clock connection. As a result, the "not" clock pulses are applied to AND gate 508 via gate 507 , with the pulses occurring in the theoretical midpoint of the bits of the data character. > ι «<

Let us now return to the setting of the MS flip-flop 502. The high voltage appearing at its "1" output terminal is also given via line 503 to monopulser 570 , which applies a pulse to an input of gate 504. As described below, the CM flip-flop 512 is in the cleared state as long as the output data buffer 501 is ready to register a received character. The output "0" of the flip-flop 512 then gives a high voltage to the gate 504. Then, when the MS flip-flop 502 is set, the monopulser 570 transmits a pulse via the gate 504 to delete the SD flip-flop 505. This flip-flop then gives high voltage Line 506 which leads to an input of AND gate 508 .

In addition, line 518 leads to gate 508 and is connected to terminal DD . As explained above, the common output control applies a high voltage to terminal DD when the

The system is in synchronism and the output data buffer can register characters.

Assume the system is synchronous and high voltage on line 518 on the gate 508, when the SD flip-flop is deleted, 505 gate 508 turned on to deliver the "not" clock pulses supplied by gate 507 to the shift pulse input of the bus shift register, generally referred to as block 511. When accordingly the output data buffer 501 is ready to accept a data character, the "not" - Clock pulses are transmitted as shift pulses for bus register 511 via gate 508.

Note that the "not" clock pulses passed through gate 507 are also applied to the count input of counter 509 which normally provides low voltage for gate 510 at its output. However, when the counter 509 has counted to a value equal to the number of message elements of the code character plus 1, the output of the counter goes high. The _% counter 509 thus supplies a count which corresponds to the number i) of message elements plus the flag bit of the code character.

The shift register 511 contains a plurality of stages, which are designated by 1 to N and correspond to the N message elements of the code character, as well as the stage F, which corresponds to the flag bit accompanying the code character. The incoming code character is applied by the bus to the connection BO of the output data buffer 501. The connection BO is connected to the stage F of the shift register 511 via the line 517. In the theoretical midpoint of the first data bit applied to stage F through the common bus, the “not” clock pulse applied via gate 508 brings stage F into the state corresponding to the first bit. Approximately in the theoretical midpoint of the second bit, the "not" clock pulse applied via gate 508 shifts the first bit to level N and brings level F into the state corresponding to the second bit. In a corresponding manner, each subsequent bit of the code character is entered into the shift register 511 and the previous bits are shifted through the stages until the first bit in stage 1, the last bit in stage N and the flag bit in stage F is stored. ■ -.? '

The »NichU clock pulse, which sends the flag bit to stage F , also switches counter 509 to the final state. As a result, counter 509 applies high voltage to gate 510 and turns it on. When the gate 510 is switched on, the next clock pulse is allowed to pass and clears the MS flip-flop 502. This switches off the high voltage from the gate. Then the "not" clock pulses are blocked, the incrementing of the counter 509 is stopped and the registration of subsequent code elements from the common bus is terminated.

The deletion of the MS flip-flop 502 brings its "0" output to a high voltage, which is transmitted via the line 516 to the connection STS. As described above, the terminal STS is connected to the terminal STP of the subsequent output data buffer, so that the reading process of the subsequent buffer is initiated. Of course, if the output data buffer 501 is the last buffer, the high voltage on line 516 will be transmitted through the STS to the common output control to allow it to sample the frame bit, as discussed above.

: 5 The high voltage at the "O" output terminal of the MS flip-flops 502 goes to the counter as a reset pulse 509 and resets it to its initial value. In addition, the high voltage goes to the "0" output of the MS flip-flop 502 via line 513 to the setting input of the SD flip-flop 505, its setting removed the aforementioned actuation voltage for gate 508.

The high voltage on line 513 is also at one input of AND gate 520, the other input of which is connected to line 523. As will be described below, line 523 is normally at high voltage, with the exception of cases where "free" - Characters are registered by the shift register 511.

ao If this is not the case, gate 520 is actuated and sets CM flip-flop 512. at when the character is registered in the shift register 511, the CM flip-flop 512 is set, its "0" - Output terminal goes low and gate 504 is turned off.

When the CM flip-flop 512 is set, its "1" output terminal goes high and operates gate 521. The other input of gate 521 is on line 524. As will be described below, line 524 is high Voltage when the output buffer sends out a data character. Then the character can be entered into the bus shift register 511. Assuming that the input into the shift register 511 is permissible and that a high voltage is applied to the line 524, the AND gate 521 excites the monopulser 522. This then delivers a gate pulse at its output.
The gate pulse at the output of the monopulser 522 goes via the line 525 to an input of the gate 526, the other input of which is connected to the line 527. Line 527 is normally high except when shift register 511 is storing a character corresponding to the

Corresponds to an "interruption" or extended pause state. Assuming that this is not the case, the high voltage on line 527 actuates gate 526 which then allows the gate pulse to pass. The output of gate 526 is connected to the clear inputs of stages 1 to N and the setting input of stage.F in shift register 511. The pulse passing through gate 526 thus clears levels 1 through N and sets level F. Entering a marker bit in levels 1 to N and a pause bit in level F corresponds to the »space character. When the shift register 511 is read out, the “empty” character is entered, as described below.

The gate pulse provided by monopulser 522 is also transmitted over line 525 to a read gate, shown generally in FIG. 6 is drawn as block 601. Gate 601 reads the character stored in bus shift register 511 into the channel shift register, represented generally by block 602. In addition, the gate pulse goes on line 525 via line 604 to the setting input of stage STP in channel shift register 602. The gate pulse therefore writes a pause bit in

25 26

the stage STP corresponding to the pause start element 623 is the high voltage at its "O" output of the code character on. In addition, the gate pulse is given via the delay network 627 to the line 524 at the output of the monopulser 522, whereby, as described above, the gate clear input of the flip-flop 512 is performed. By the 521 is switched on and the monopulser 522 clears the CM flip-flop 512, the gate 504 is activated again 5 gate pulse for reading out the bus, as described above, and shows that shift register 511 supplies. If the oscillator 622 indicates that the character is setting in the bus shift but CG flip-flop 623, the high span register 511 has been read out. The gate 601 contains the AND gates 605 to line 524 removed. During the transmission of the 609 and 611 to 615. An input of the gates 605 io code characters, the gate 521 is therefore switched off. ¹ to 607 on lines 530 to 532 with the first output pulse of the oscillator 622 'O' output terminals of stages 1 to N of the CG provides flip-flop 623 which clears the shift register 511 connected one. The other input high voltage at its "0" output. Accordingly, the gate 605 to 607 is on the line 525. The gate 521 is switched off and the high inputs of the levels 1 to N of the channel register applied to the monopulser 629 via the outputs of the gates 605 to 607 with the clear gates 624 602 Tension removed. At this point in time, however, when the oscillator 622 is applied, the gate 601 reads the first output pulse to that of the gate pulse on the line 525, the marker OR gate 624. Its output remains so elements in the bus shift register 511 at high voltage, and the first output pulse and sends it to the channel shift register 602. 20 of the oscillator 622 does not deliver a positive span 613 via lines 535 to 537 with the "1" exit does not come into operation. Note that at this point in time, stages 1 through N in the bus register are those data output lines 628 that connect 511. The other input of gate 611 is connected to the "0" output of stage STP until 613 is on line 525, and output 25 is at low voltage and a pause start of gates 611 to 613 is simulated with the setting inputs , since the previous one, connected via the unfortunately levels 1 to N of the channel register 602. device 604 applied gate pulse has set the stage STP - read the gates because of the gate pulse.

The pause elements in the bus register 511 At the end of the period of an element, it delivers and puts it into the channel register 602. The gate oscillator 622 sends the second output pulse. This terimpuls on the line 525 also causes in runs via the OR gate 624, and the mono connection with the gates 608, 609, 614 and 615, pulser 629 then delivers a pulse to the Leidass the parity bit of the code character in the P stage device 625. This line is with the shift pulse and the end or stop bit of the code character in the input of the channel shift register 602 and to which the stage SP of the channel register 602 is entered, 35 control input of the stage SP via the OR gate as described below . 626 connected. Consequently, at the end of the start bit, the input of data bits into the channel shift interval, the monopulser 629 gives a shift pulse register 602 directs the operation of the transmission switch to the shift register 602 and at the same time sets a device for the transmission of the data to the output Pause bit in level SP . Through the sliding line 628. The scanning of the character in the 40 pulse is switched on by all code elements by one stage. Shift register 602 is taken over by the OR gate, so that this is done in the first stage. The input lines of the OR gate 620 of the stored code element are shifted to the STP stage with the "O" output terminals of the stage 1 being. Accordingly, the first message element through N, P and SP of the shift register 602 is connected. of the data character to the data output line 628

Assume now that gate 601 is given a 45.

Characters from bus shift register 511 into Each subsequent pulse from oscillator'622

the channel shift register 602 outputs, as described above, the monopulser 629 in a corresponding manner,

ben, a marking bit is sent to one of the levels 1, which then transfers the data bit via the levels of the shift

to N, P or SP of the shift register 602 given. register 602 advances so that "successive

Consequently, the »(k output terminal places one or 50 low data bits to the STP stage and thus to the data

several stages of high voltage can be pushed to the OR gate output line 628. Simultaneously

ter 620, which supplies the high voltage to the oscillator- every shift pulse on line 625 is over

control 621 there. This then switches the oscillator to the OR gate 626 given to the pause bit

622 to write a series of STP pulses at the output. The shift register 602 with a bit frequency that the signal frequency 55 is padded with pause bits that the data on corresponds to the data output line 628. characters follow through the shift register.

The first output pulse of the oscillator 622 is. The shift pulses are sent to the

at the same time applied to the setting line of the CG flip-flop shift register 602 until this was previously in the

623 and stop bits stored on an input line of the OR gate stage SP for stage STP

624 created. At this point the CG flip-60 is being pushed. At this point everyone else is flop 623 normally cleared so that its "0" levels are filled with pause bits. Hence their Output high voltage to the other input "0" outputs all on low voltage, and that of the OR gate 624 applies. The OR gate OR gate 620 provides a low voltage on sei-624 so normally delivers high voltage at its output. This low voltage removes the to the input of the monopulser 629. The "0" -off 65 actuation voltage from the oscillator control The output of the CG flip-flop 623 is also via the 621, so that the oscillator 622 is switched off. the Delay network 627 with line 524 reduces the low voltage at the output of the OR gate bound. If the CG flip-flop 620 is normally cleared, it is also transmitted to the inverter 630,

which then supplies a high voltage to the clear input of the CG flip-flop 623. This flip-flop then goes into the cleared state and again applies a high voltage to the OR gate 624. In addition, the high voltage at the "O" output of the flip-flop 623 is applied to the delay network 627 , the delay time of which corresponds to the duration of the stop element. At the end of this time, the high voltage goes to line 524 so that AND gate 521 is activated again. This indicates that the transmission of the data character has ended, so that the circuit can generate a further gate pulse through the monopulser 522 .

The sending operation can be summarized as follows. When a gate pulse generated by the monopulser 522 inputs a character into the channel shift register 602, the characters are detected by the OR gate 620 and start the transmission circuit, which contains the oscillator control 621, the oscillator 622 and the CG flip-flop 623 . When the character is detected, the transmission circuit supplies shift pulses to the channel shift register 602, as a result of which each of the code character bits is given to the data output line 628 . The shift pulses are also used to enter pause bits into shift register 602 so that it is filled when the data character is shifted out. At the same time as the transmission of the data character, the AND gate 521 is switched off and the monopulser 522 cannot generate a further gate pulse. As a result, no subsequent character from the bus shift register 511 can be put into the channel register 602 during transmission. When the code character has been completely read from the channel shift register 602 , the transmitter circuit is returned to the free state, the shift pulses cease, and the AND gate 521 is switched on again to enable further gate pulses to be generated subsequently.

Referring now to that one character read into the bus register 511 and then the CM flip-flop is set 512 as described above, the CM-flop 512 provides a positive voltage transition to an input of gate 521. At this time, a code character is sent out, the gate 521 is switched off, as described above, and the monopulser 522 can therefore not generate a gate pulse. However, the CM flip-flop 512 remains set so that the high voltage on gate 521 is maintained. Thus, upon completion of the transmission, high voltage is applied to line 524 , as described above, so that monopulse 522 is actuated and the gate pulse is generated to transfer the new character from bus register 511 to channel register 602 in the same manner as described above.

Assuming now that a code character is sent out from the channel register 602 and another code character is stored in the bus register 511 , which is waiting to be transmitted to the channel register 602 , the registration of a new character in the bus register 511 is prevented, although a new start scan cycle is initiated in that a pulse is applied to the termination STP from the preceding output data buffer. When the character is stored in the bus register 511 , the SD flip-flop 505 is set as explained above. As a result, low voltage is applied from the "0" terminal of SD flip-flop 505 via line 506 to one input of gate 508 which then turns off. In addition, the CM flip-flop 502 is set as described above, and if the generation of a gate pulse is prevented, the flip-flop remains set as long as the character in the channel register · ($ 02 is sent. From the "0" output of the CM flip-flop 512 that is, a low voltage is applied to gate 504 which turns the gate off.

When the new key start signal is applied to the terminal STP , the MS flip-flop 502 is set, as explained above. This turns on gate 507 and applies a high voltage to gate 504. However, since CM flip-flop 512 remains set, gate 504 is off, preventing the SD flip-flop 505 from being cleared. As a result, gate 508 remains off. The "not" clock pulses then pass through gate 507 but are blocked by gate 508. This prevents the character from entering the bus register 511 , but allows the bits to be counted by the counter 509 . Thus, although the registration of the character is prevented, the counter counts the data bits and thereafter the MS flip-flop 502 is cleared as described above so that the scan start signal is given to the next output data buffer. The sequential reading of the characters by the output data buffer is thus continued continuously, although one of the data characters, which is presumably an "empty" character, is dropped in the case of a character stored in the bus register 511.

Display of code and flag bits

In addition to entering the data character into the channel register 602 , the gate 601 feeds the parity bit and the stop bit into stages P and SPw of the channel register. The bit fed into stage P corresponds to the parity bit of the code character supplied to the input data buffer. Correspondingly, the bit input into the stage SP contains the stop bit, which corresponds to the stop bit of the code character applied to the corresponding input data buffer.

If one now assumes that the code character entered into the bus register 511 via the bus represents a free or empty state, this "empty" character, as described above, supplies a marker bit to levels 1 to N and a pause bit to stage F in bus register 511. AND gate 540 has a plurality of inputs which are connected to the "0" outputs of stages 1 through N. These outputs go to high voltage when the corresponding stages store a marker bit. Thus, entering the "empty" character in bus register 511 turns on AND gate 540 , the output of which then goes high. This voltage is transferred to AND gate 541 . The other input of the AND gate 541 is above the line 538 at "1" output of Step F of manifold register 511. Since this output is also at high voltage, the gate transmits 541 high voltage to the inverter 542, which then low voltage at the line 523 applies. This turns off gate 520 and the setting of the CM flip

flops 512 prevented. As a result, the generation of a gate pulse is prevented, the entry of a new character in the channel register 602 is disabled, the operation of the transmission circuit is not initiated, and the marker stop bit remains in the STP stage, so that the data output line 628 is kept in the free marker state .

When a "letter" character is received from the bus, marker bits are entered in levels 1 through N and a flag bit is entered in level F of bus register 511 . With marker bits in stages 1 to N , a high voltage is generated at the output of gate 540 in the same way as has been described above for the reception of an "empty" character. However, since a flag bit is received for the "letter" character, there is a low voltage across line 538 at gate 541. As a result, inverter 542 supplies high voltage to line 523. This turns gate 520 on and enables the Setting the CM flip-flop 512 so that the monopulser 522 can deliver a gate pulse. The registration of the “letter” character thus enables a gate pulse to be generated and the bus register 511 to be read out into the channel register 602.

As already explained, the code characters contain parity bits. Assuming even parity and an odd number of information bits or odd parity and an even number of information bits, the "letter" character needs a marking parity bit. In this case, the output of the gate 540 is connected to an input of the AND gate 545 . The high voltage at the output of gate 540 then goes through OR gate 545 and line 546 to AND gate 608. Since the other input of AND gate 608 is on line

525 , the gate pulse is transmitted via gate 608 to the clear input of stage P of channel register 602 . As a result, a mark parity bit is input to the P stage. On the other hand, if the parity bit for the "letter" character with the coding associated with the output data buffer 501 is a pause bit, the connection of gate 540 to gate 545 is open. The OR gate 545 then outputs a low voltage to the inverter 549, which accordingly applies a high voltage to the gate 614 via the line 550 . The gate pulse is then transmitted through gate 614 to the set input of stage P so that a pause parity bit is entered into channel register 602 .

When the "letter" character is stored in bus register 511 , the output of AND gate 552 is at a low voltage, as described below, so that the output of gate 553 is also at a low voltage. This voltage is provided to inverter 554 which then applies high voltage to line 566 . This line leads to an input of gate 609, so that gate 609 switches on and transmits the gate pulse to the clear input of stage SP of channel register 602 . Then a marker stop pulse is inserted into the stage SP .

The high output voltage of inverter 554 also switches the gate via line 527

526 , so that when the bus register 511 is read out, the "empty" character is entered again, as described above. As a result, the "letter" character from bus register 511 is placed in channel register 602 , the corresponding parity bit is entered in stage P and a marker stop bit is entered in stage SP . Since the gate pulse enters a pause start bit in the STP stage and marker bits are inserted in the channel register 602 , the operation of the transmission circuit is initiated and a "letter" start-stop character is sent to the data output line 628.

give. ··, .ü

When a "break SA" character is received from bus register 511 , output line 628 is paused. This state remains until another character, which is not an "interrupt" character, is given to the bus register 511 .

Recall that a "break" character contains only a pause information bit and a flag bit. Thus, when a "break" character is received, levels 1 through N of bus register 511 are set and level F is cleared. The “!” Outputs of stages 1 to N of bus register 511 are connected to the inputs of AND gate 552 . Since all "1" outputs are high when an "interrupt" character is received, the output of AND gate 552 goes high. This is applied to inverter 562 which then applies a low voltage to gate 548 and turns the gate off. When the voltage at the output of gate 548 is low, the output of OR gate 545 is low and inverter 549 supplies high voltage to line 550. Since line 550 leads to an input of gate 614 , this gate is switched on and is A gate pulse to the setting input of stage P of channel register 602. The storage of an "interrupt" character in bus register 511 thus leads to the entry of a pause bit in stage P. The output of gate 552 is also connected to an input of gate 553 whose other input is via line 533 at the "0" output of stage F in bus register 511 . Accordingly, both inputs of gate 553 are at high voltage, so that the output of this gate is also at high voltage.

The high voltage at the output of gate 553 goes via line 560 to AND gate 615 in gate 601. If a gate pulse is subsequently generated, it goes through gate 615 and OR gate 626 to the setting input of stage SP in channel register 602 . the storage of the "interruption 'signal in the bus register 511 so leads to enter a pause bits in the level of the channel SP register 602.

The high voltage at the output of gate 553 is also applied to inverter 554 , which then applies line 527 to a low voltage and switches gate 526 off. Then the gate pulse cannot enter the "empty" character into the bus register 511. This will maintain the "break" state if synchronism is lost, as described below.

The high voltage at the output of gate 553 is also transmitted to an input via line 556.

passage of gate 557 given. The other input of gate 557 is on line 525 so that the gate pulse can pass through gate 557 and clear the 55 flip-flop 558. As described below, the SS flip-flop 558 remains in the cleared state as long as the "Interrupt SA" characters are received.

If one now assumes that the transmission circuit is prepared to receive the »interrupt-x-character, the gate 521 is switched on. Upon receipt of the "interrupt" character, the CM flip-flop 512 is set in the same way as described above, so that the AND gate 521 supplies the monopulser 522 with a high voltage. This then generates the gate pulse and the "interrupt" character is read from bus register 511 into channel register 602. As described above, since all message bits are pause bits and pause bits are input to the P and SP stages of the channel register 602 , the OR gate 620 does not read any flag bits and the operation of the broadcast circuit is not initiated . However, the gate pulse has set the stage STP in the channel register 602 . Accordingly, the data output line 628 is brought into the pause state. This state is maintained to simulate an "interruption" state. This operation is repeated for each subsequent receipt of the "interrupt" signals so that the pause state of the data output line 628 remains undisturbed.

At the end of the "break" state, bus register 511 receives a character that is not a "break" character. Then the output of gate 552, and consequently the output of gate 553, goes low. This will restore the low voltage on lines 556 and 560. Inverter 554 also brings line 527 high again, and when M5 flip-flop 502 clears at the end of the new character, line 513 goes high, which is transmitted through gate 564 to the set input of SS flip-flop 558 . The SS flip-flop 558 is then reset and provides a positive voltage transition at its "!" Output terminal. This positive voltage transition goes via the line 559 to the clear input of the STRi stage in the channel register 602. As a result, if a character that is not an "interrupt" signal is received, the STP stage is cleared and the data output line 628 is returned to the marking state, whereby the "interrupt" - Signal has ended.

The »space received from the output data buffer only contains a pause information bit and a pause flag bit. Thus, when a "blank" character is received, levels 1 through N and level F of bus register 511 are set. Since all "!" Output connections of stages 1 through N are at high voltage, the output of AND gate 552 goes to high voltage. When level F is set , however, its "0" output applies a low voltage to gate 553 via line 533. The output of gate 533 therefore goes to low voltage. Also, the low voltage on the "O" output terminals of stages 1 through N in bus register 511 brings the output of gate 540 low and turns gates 541 and 544 off. The inverter 542 accordingly applies a high voltage to the line 523, so that the gate pulse for transmitting the "empty" character to the channel register 602 can be generated. Finally, the low voltage at the output of gate 553 is transferred to inverter 554 , which then applies high voltage to lines 527 and 56,6. When the voltage on line 566 is high, the gate pulse puts a marker stop ^ bit in stage SP

ίο of channel register 602 . Thus, the "space" is read from bus register 511 and entered into channel register 602 in the usual manner, and the gate pulse sets the appropriate start and stop bits.

It has heretofore been assumed that the code character contains a parity bit which provides even parity. In this arrangement, the inverter 562 is connected to the Gater 548, so that the gate 548 turned off upon receiving the "Empty" -symbol. When both gates 544 and 548 are off, OR gate 545 provides low voltage to inverter 549. Inverter 549 then applies high voltage to line 550 and operates gate 614 so that a pause bit is entered in P stage of channel register 602 will. With an even parity code, a pause parity bit is entered when the »empty« character is received.

As described above, when normal data characters are transmitted, the input data buffer provides a pause flag bit when a flag parity bit is received and a flag bit when a pause parity bit is received. The output data buffer then checks the flag bit and enters the corresponding parity bit in stage P of channel register 602 . Upon receipt of normal characters, the output of gates 540 and 552 will be low and characters from bus register 511 to channel register 602 will be transferred in the manner previously described.

When gate 552 is low, inverter 562 provides an actuation voltage to gate 548. Simultaneously, when the output of gate 540 is low, gate 544 is turned off. Then only gate 548 can pass high voltage to OR gate 545. Assuming now that the code character received contains a flag bit, the "!" Output terminal of stage Ψ ' in bus register 511 goes low and gate 548 is turned off. The low voltage resulting at its output is passed to the inverter 549 , which sets the line 550 to a high voltage. Gate 614 turns on and a pause bit is entered into P stage of channel register 602 . On the other hand, when a pause flag bit is received, the "1" output of stage F of bus register 511 goes high and gate 548 applies high voltage to line 546 through OR gate 545.

Gate 608 can then input a marker bit into P stage of channel register 602 . Accordingly, when a flag bit is received, a pause parity bit is input, and a flag parity bit is inserted into the channel register 602 when a pause flag bit is received.

The circuit also sets a stop bit in channel register 602 upon receipt of normal characters. When receiving a conventional character

the output of gate 552 goes low as described above. The output of gate 553 then also goes low and inverter 554 applies high voltage to line 566. Gate 609 can then pass the gate pulse. As a result, a mark bit is inputted to the stage SP which is the mark stop element of the code character.

Bit distribution

during synchronization recovery

If the synchronization is lost, the common output control prevents the Registration of characters and counting of character bits by the output data buffer as above explained. However, if an error-free frame bit is detected, the output data buffers can use the Data bits count, but the registration of the characters is prevented until three consecutive ones error-free frame bits are determined.

If one now assumes that the synchronization of the system is lost, the high voltage normally present at connection DD is removed. In addition, the high voltage applied to the DIS terminal in the first output data buffer is also removed. Accordingly, gate 508 in each data buffer and gate 507 in the first output data buffer are turned off. If the gate 507 in the first output data buffer is switched off, the "not" clock pulses applied to the counter 509 via this gate are blocked. When a sampling cycle is started by the common output control, the MS flip-flop 502 of the first output buffer is set as described above. If synchronization is lost, however, gate 507 is switched off and blocks the application of the "not" clock pulses to counter 509. As a result, MS flip-flop 502 remains set while the low voltage at terminal DIS is maintained.

If a suitable frame bit is detected after a lost synchronization, the terminal DIS goes high and the gate 507 in the first output data buffer is actuated. Then the "not" clock pulses can pass through gate 607 to counter 509 . The gate 508 remains blocked because of the low voltage at the terminal DD and prevents the registration of the character received from the bus over the line 517 . As a result, although the character is not registered, at the end of the corresponding count, the MS flip-flop 502 is cleared, as explained above, and the scan start signal is sent to the second output data buffer.

When the second output data buffer receives the scan start signal at its terminal STP, its MS flip-flop 502 is set and operates gate 507. However, terminal DD is still at a low voltage and gate 508 is turned off. As a result, the second output data buffer counts the data bits, but does not register the data character. Each output data buffer therefore counts the bits and starts the next data buffer, but does not register the character. The process is repeated until the last buffer counts the bits, and at the end of the counting the last data buffer gives a signal to the common output control via its connection STS-N. The common output control then samples the next bit to see if it is the correct frame bit, as described above. These cycles are repeated until the common output control regains synchronization, as explained above, restoring the high voltage on terminals DIS and DD of the output data buffers.

Note that if synchronization is lost, if the output data buffers count but do not register the characters whose MS flip-flop 502 is toggled cyclically, that is, they are set and deleted one after the other. This in turn clears and sets the SD flip-flop 505 successively. The CM flip-flop 512 remains cleared, however, because, as described above, the circuit enters the "free" character into the bus register 511 , causing the line 523 to be low. This voltage switches off the gate 520 and prevents the setting of the CM flip-flop 512. If the synchronization is lost, each output data buffer puts the "free" character in the bus register 511 and prevents transmission through the channel register 602, so that the data output line 628 in the free marking state is held. However, if there is an "Interrupt SA" character in bus register 511 , CM flip-flop 512 toggles since line 527 is held low, as discussed above. This low voltage turns gate 526 off, preventing the "idle" token from being entered into bus register 511 . Accordingly, the "break a" character remains in bus register 511, as discussed above. If the "break" character is in the bus register 511 , transmission by the channel register 602 is prevented, as explained above. However, a pause-interrupt condition is maintained on output line 628 since the STP level of channel register 602 has been set as described above. Thus, if the output data buffer receives an "interrupt" signal shortly before synchronization is lost, the "interrupt" state is maintained on data output line 628 until synchronization is restored and a new character is received.

Claims (10)

Patent claims: 1. Time division multiplex transmission system for code character bits of different coding type and signal speed with a plurality of input connections for each an individual coding type and signal speed, the incoming character bits receive and forward a common path, and with the input connections each associated output connections, each of the register bits fed to the corresponding input connections on the common path, characterized in that each input connection (101 , 102, etc.) applies the bits of a character to the common path (120) (345) when a complete character is applied to the common path, and then initiates the next application of one character at a time through an input terminal (321, 346, STS, STP) and that each output terminal (115, 116 , etc.) has the applied bits registers one character at a time (511), detects (509, 510) when a complete character is registered, and then initiates the next registration of one character at a time through an output terminal (502). 2. Time division multiplex transmission system according to claim 1, characterized in that a pulse source is provided whose repetition frequency of the signal frequency on the common Path corresponds to that each input port first, by each pulse from the pulse source contains actuated means which apply a bit to the common path and that the first Actuating means comprise a first pulse supply circuit which receives the pulses from the Feed the pulse source to the next following input connection. 3. Time division multiplex transmission system according to claim 2, characterized in that each output connection second means, actuated by each pulse from the pulse source, comprising a register bit applied via the common path, and that the second actuating means have a second pulse feed circuit have that feed the pulses from the pulse source to the next output terminal. 4. Time division multiplex transmission system according to claim 1, characterized in that each input connection a memory circuit for storing the bits of the received character prior to being applied to the common path and means for indicating the presence of the bits contained in the memory circuit, and that the indicating means Have means responsive to the removal of all bits from the memory circuit and actuate the next input connection. 5. Time division multiplex transmission system according to claim 4, characterized in that each input terminal Contains means responsive to the application of bits and a flag bit in the Enter control circuit for delivery to the common path. 6. Time division multiplex transmission system according to claim 5, characterized in that the input means Have means to take action when there are no character bits from the input port and a predetermined flag bit corresponding to the state of the received from the input port Enter signal. 7. time division multiplex transmission system according to claim 6, characterized in that the Registration means have means which respond to the registration of the predetermined flag bit address the non-existent character bit and send a corresponding signal state to the output connection invest. 8. Time division multiplex transmission system according to claim 3, characterized in that each of the second actuation means have means for counting the bits applied to the registration means and that the counting means are adapted to the second actuating means upon counting one Press the predetermined number of bits corresponding to the number of bits contained in the code symbol. 9. Time division multiplex transmission system according to claim 8, characterized in that synchronization means are provided, the application means individually assigned to a first input connection and the corresponding one at the same time Actuate output connection individually assigned recording means, as well as means for display a failure of the synchronizing means, the indicating means having a device for switching off the counting means individually assigned to the first output connection and all recording means. 10. Time division multiplex transmission system according to claim 9, characterized in that the display means means for re-establishing the synchronization; Actuation of the switched-off counting means, so that each output connection a count but prevents bit registration. For this purpose 2 sheets of drawings