DE1474147C - Time division multiplex analog computer - Google Patents

Description

1 2

The invention relates to a time division multiplex analog F i g. 6 (I) and 6 (II) graphical representations of the computers with a variety of input channels, with input and output waveforms, at least one via a first sampling switch F i g. 7 (I) and 7 (II) excerpts from FIG. 6 (I) and arithmetic circuit connected to it and with this 6 (II) on an enlarged scale, with the input also via a voltage synchronous with the first 5 sampling by a straight voltage curve switch working second sampling switch is approximated, closed output integrators. F i g. 8 is a block diagram to which in FIG

For an analog computer or an analog simulator Description of a known time division multiplex calculation

are referred to in many cases within the research circle,

numerous non-linear circuits with the same characteristic io F i g. 9 is a block diagram of a modified one

line used. This makes a multitude of such on- embodiment of the invention and

agile circuitry required. F i g. 10 a graphical representation of input

In "Proceedings of the IRE", May 1959, p. 847 bis wellenformen.

851, a time division multiplex analog computer is described, an example of such a non-linear switch using the time division multiplexing technique a 15 circle. is a multiplication circle, its input multiple utilization of non-linear circuits and output characteristics each independent of or function generators. In each case during the part of an analog computer within which he of a sampling interval, new values are used in which is the same. For example with the solution Arithmetic circles entered throughout a partial differential equation by following Sampling period are stored and as 20 conversion into a difference equation or into a Input values are used. So it is an amplitude simulator where a large number of circuits of the. sampling of the input function provided. The respective system to be simulated has the same character input voltage a large number of circuits is required for the various computational statistics, there is a step voltage. The different function generators, each of which is the same Integrators also work between the individual 35 creating functional relationships. At a Sampling times. known computer according to FIG. 1 are for example

Tests carried out have shown that multiplication circuits M ₁ , M ₂ , M ₃ , ...

This type of calculation results in considerable errors in function generators F ₁ , F ₂ , F ₃ , ... for generation

can adjust. same functions, integrators I ₁ , I ₂ , I ₃ , ■ ■ ■ and

The object of the invention is to improve the 30 potentiometers P ₁ , P ₂ , P ₃ , ... and each input

Computational accuracy in a time-division multiplex analog and output terminals ^ ₁ , ei _ia , et ₂ , e < ₂ ", ei ₃ , et _3a , ...

Computer of the type mentioned and a saving of and e ₀₁ , e ₀₂ , e _oa , ... provided. In such a case,

complex intermediate storage of the sampled values. where the arithmetic circuit from a large number of

According to the invention, this task is thereby constructed with computing circuits with the same characteristics

solved that the time constant of each integrator must be taken into account, the number of

ratio of the closing time of each scanner contact to the computer-based non-linear circuits such as

Period of rotation of the sampling switch compared to the multiplication circuits and function generators

Value for a single-channel operation is shortened and that is not off. Their number can accordingly also be used for

each integrator in each case inadequately solving other tasks posed during the closing time

Be the scanner contact on the second scanner switch in the 40. Also have when planning a

Computational state and otherwise in the hold state simulator non-linear switching elements in general

is. a higher price than linear switching elements, except-

The invention therefore proposes a reduction in the size of such a device. Consequently

Time scale · of the integrators before, so that during one endeavors to provide the number of

the respective sampling interval, d. H. reduce the closing time of 45 circuits as much as possible,

of the relevant sensing contact, the waveform with The present invention is based on a computer

is evaluated on a reduced time scale. So that, for example, according to FIG. 1, which is in the

the computer according to the invention evaluates the entire input stages of a large number of integrators

in the respective contact closing time has decaying circuits with the same characteristics, and

cut out the input curve. An intermediate 50 proposes a circuit arrangement, according to which by means of

The integrators store the values for the various computations in an excellent method

no channels. can be controlled in a manner yet to be explained

The invention is based on execution and according to which a time division multiplex method is possible

examples in connection with the drawings is borrowed in more detail. This creates an analog computer

explained. 55 in which the required number of arithmetic

It represents circles with the same characteristics in each case

Fig. 1 is a block diagram of a known train is reduced.

management form of an analog computer, which with an In one embodiment of the invention according to

Computer according to the invention is comparable, F i g. 2, in application to a calculator according to

Fig. 2 is a corresponding block diagram of a 60 Fig. 1, fulfills a single multiplication circuit M so-

preferred embodiment of an inventive as a single function generator / ¹ the tasks of

analog computer, multiplication functions belonging to different channels

F i g. 3 a block diagram of the structure and the circuits AZ ₁ , AZ ₂ , AZ ₃ , ... and function generators F ₁ ,

Circuit of an analog integrator, F ₂ , F ₃ , ... in the computer according to FIG. 1. The one

F i g. 4 is a block diagram of a control circuit with 65 output waveforms via input switches

a variety of control switches, S ₁ , S _ia , S ₂ , S ₂₀ , S ₃ , S _3a , ... and the output

F i g. 5 shows a time diagram to explain the output waveforms via output switches T ₁ , T _ia ,

Opening times of the control switch, T ₂ , T ₂₀ , T ₃ , T _3a , ... decreased.

3 4

During operation, the changeover switches with application circuit and a function generator are

the index 1, so S ₁ , S _ia , T ₁ and T _ia , each reaching for one.

fixed time closed. If then this changeover, however, if the frequency characteristics of the non-switches are opened, the switches with the linear switching circuit are bad, then index 2, ie S ₂ , S _2a , T ₂ , T _2a , can be closed. In each case 5 achieve sufficient results that the output following switching cycles are each actuated the changeover switch Tj and Tja with a time switch with the indices 3, 4, .... If the delay ZJf _{0 is opened} after the input changeover switches Sj and Sj _a , which are ultimately the last switch group in the series, have been actuated, the sequence will be closed again, as shown in FIG. 5 is indicated. by means of the switch group with the index 1 on the io The delay time ZIi ₀ is switched over to the time interval channel 1 and the entire sequence of operations is the same, with which the output voltage of the non-repetitive, linear circuit each time after closing the

The control of the opening and closing of the on switches Sj and S _{] a of} the input voltage follows. In

gear and output switch takes place, for example, this case is the savings factor for the non-

by means of a control circuit according to FIG. 4, in which a 15 linear circuit is not exactly, but approximate

Signal pulse generator for generating a PO peri- _we j JL _se

dischen pulse train as well as a ring counter RC vor- η '.

are seen. That achieved in the manner previously described

To control the opening and closing the calculation result is essentially the calculation result

called switch, the output pulses of the 20 serve the same without time division multiplexing, if only the

Levels 1, 2, 3, ... of the "ring counter RC, with a cycle time t ₀ significantly shorter than the fluctuation

Switch group in each case the stage with the corresponding period of the calculation result is what in detail

Index is assigned. It follows either mechanical from the following considerations,

or electronic switches are used. In the input and output waveforms of a

In detail, each of these switches will periodically represent 25 computing channels. 6 (I) and 6 (II) open and closed. The ring period of the ring represents the curve 1 an input waveform. Counters within which a complete counting cycle If one assumes that the switch of this calculation is completed, let t ₀ and the respective channel only during the time intervals between - "". ".., ·, r ,, 1 ■ tn 1 ■ 1 see the times U, t _ia ; U, U _a ; t ₃ , t, _a ; ... closed closing time of each individual switch denoted by f. _{30 are you get} an initial shape in the form

It is assumed that the time factor of a step function corresponds to the dashed line

that computing circuit, which the output span curve a _a , c _a , b _a ... in F i g. 6 (II). This arises

voltages of the non-linear circuits M and F further from the fact that an arithmetic operation only during

,.,. . 1 . . the time segments i _1; t _ia ; t ₂ , / _2a ; i ₃ , t _3a ; ■■■ takes place where-

processed by a factor - versus an on _{35 versus during the remaining} operating time of the

Order according to fig. 1 has shrunk. This arithmetic circuit remains in its memory position.

Shrinkage is achieved by the fact that if one looks at the respective

,, ·., * 4. · j Ti j. ■ Tw 1 clock processed section of the input signal

_Time constant of each integrator by a factor - ^ _def ^. ^^ üfeef ^ _complete working period

scaled down. The respective other inputs of the Internet think 40 stretched, so that, for example, the section
grators according to FIG. 2, each of which passes from the potentiometer in the stretched portion of a _c, one obtains the Meiern P _1, P _2, P ₃ ... come from, are represented by the dashed curve indicated by the level switch T _1, T ₂ , T ₃ , ... each at the same time as the formwork function K in FIG. 6 (I). When you see these waves. So if these switches are not closed, form K as an input waveform in a known one takes place in the relevant stage of the computer no calculator without time division multiplexing is used, so that the stage in question is kept as an output voltage as a voltage, storage position. During the in F i g. 2 shows which, through the temporal expansion of the step of the computer containing the integrator I ₃ individual arithmetic clocks, calculates with a step by one according to FIG. 6 (II) for a full working period T _7,. 1 , .. . ry ■. nc 1 4th -i. j · u j- 5 ° arises, where, for example, the section a _a c _a in factor-shortened time measure factor, while the ⁵ passes over _the section α ^ _ο. Through each other-

other computer levels are in the memory position. sequence of these expanded output curve sections An integrator for low computing speed is obtained with an output waveform represented by the chain-like curve m _a normally at its connection point.
Switch U to F i g. 3. By moving this 55 The curve m _a thus results as output switch U to the contact A to obtain a waveform when the question asked by a dashed line represents storage position and when tilted to the contact B input waveform K in F i g . 6 (I) on one the arithmetic position. If, instead of the aforementioned, known computers without time-division multiplexing, there are switches Tj, Tja to be actuated simultaneously. If the frequency characteristic of the O ^- = 1, 2, 3 ...) only actuates the switch U , 60 computer periods equal to or shorter than the clock, a significant simplification of the switching period i _{0 is} suppressed, the output waveforming is suppressed. Since each arithmetic circuit only has an output waveform that is active when the η-th part of a basic period is applied, an average input voltage can be obtained, ie a number of non-linear circuits by one input voltage after the chain-like one

Factor - be reduced compared to a ⁵ ^ iT ⁶⁷ "', - τ- j r- n ·

η When the frequency of the input voltage is smaller

Arrangement according to FIG. 1 with a different frequency than the one corresponding to the clock period t _0,

Arithmetic circles. There are thus in each case a multi- the chain-shaped curve m corresponds to an input

voltage which is around the delay time than _the

means _e t ^Ar d? e * £ Κ? U * ^ " ^ ^{In F i} * ⁰ ^" n-1 voltage of the S ^^

~ Y ~ = - ^ - Ό ki Z ^

pg des nS ^ n ^^ l & Z

none Z ^ nuItiSSSSSf ⁰ J «*« * »» «, if

is delayed; ^^

^^ B ^ JL, is delayed; ^^^^^ 51? ^;

for the midpoint of the line de is Λ, and the de an, ^{during the time of the} tiplexing process

corresponding time period is t ₀ - A. On the other hand ?? ^tteI ™ g of the curve S ° Äi ^ ® ^you ? ^Off -

when using a timer, the "b ^ ÄieP ^ ß ^^ y ^ X" rushes

Output waveform, that is, the one from the in FIG. 6 (II) MäSls der vor! ? ° ^KISSING miscalculation with it

m dashed lines curve * by feh er veStrf '" ^{invention is the} ** £ * ■

Kz ^g r ^{onnene Kurveiüb} ^ ä ^^^

«3 inttr IS SS- -Α? G. 9 (A) of a further AES ^g r _p R ^{included Echen} ^ fe still ^FäIIen Sn ⁿ | ^ang " ^{1 l}

Z'u 5 ⁱⁿ «f ^] t ⁷ P ^an S ^edeut ^ da Ä. In the Central ^ t ₀ TLS ^^^ ^ ηην ηΐίίίΐ point of the route b _a e _a and the time period c _a b _a * o control wekhej I _n T / ^time tiplexschaltun ^ _g ^ equal to -Ajjst. Picks up signals. non-linear circuit

Since the input waveforms 1 and m as well as the maTbei ^ ίΐϊ, ί "° ^ ^igen description results, output waveforms 1. and _{Wa can} each by the H ^ S ^^^ ' ¹ * ¹ ^ ¹ ^^' ™! ^ Time segment - ^ = i_ ^ ₀ ) phase shifted ²⁵ circuits ^^^

j ^ same, _{which is at 30} SäSSÄSrSW ^ ¹¹⁰ ^^^! meaning ^ P ™ ¹¹ ^ ⁰¹¹ ! ¹¹ input voltage to the voltage also ώ Connectivity ^time n ™ ltiplexrechenanordbetreffenden computer without time division multiplexing circuit instead 3e? NäSÄ K ff ^ ^ s ^Schaltkre

penode r does not respond, there are ^numerous types of construction of

the time division multiplex _{circuit according to the invention over- 4} o InventuSaSÄ, Λ can be carried out, the

BeSek » ^be ! ^Analysis simulators applied

Strictly speaking, can be made to a LtfZti ^ V '° ** ^an analog simulator? ÜR

The prerequisites in practice are not fully SÄ} p ^d "r ^{e! K} ' ^{whose calculation}

S; ? ^a - ^{but ei} ? Analog computer as the most essential part of computing, Λ? ^{lchem the} display frequency

SSS5S = S ^ S>

SS5SiSrS

Application of this time division multiplex circuit - cut at around π ^ga "^.

the error usually within de? zuSffen ά ^ S _B ^^ ^A ^^ dhn _S r are different

SÄTER ZA ^{0 '8,?} Γ Γ, "^ ^Wied ^ olun _g s ₅ o calculator ^ dngbaut SV ⁿ / ^Tus * ^A ^ hl in the penode t _0, the time division multiplexing circuit Rechenkreisf are sufficiently small ^ in ^ J terminals of these

TJ T

First TJ Th J— ^who send S ^ Ä? VS ^^^ Ä to Fi! 8 auii "? ^, ^^ ^processes are made Snnen 'w ^ fi ^ rbmdungen Sflv. H ^g " ^ S? ^{in TIMEM} ultiplexbetrieb to loading 55 arising tasks HT according ^{to the} uses for the mchtlmeare be operated switching element where nichtünearen or H ° ^AnzahI existing IS ^nS V ^{nd A} _n ^{USgänge svnchron each} ZS ^ S ^ ⁿ i ih ^Schaltk

ί ' ^aS , STEZg da ■ fSS ^{WC lead to a big mistake} ?' ^g arithmetic control circuits for

SSST ^SOlChe H ^{n S} P? ^cherkrei s stored 6 ₅ a shortening of the Z? ^Integrators ™ sense corresponds to a delay of the originally called by UrrSK ^Zoitacllse and in synchronism with the input signal obtained _chen h Sil h SSSS ^w ä ^ rend the Rhki

SiS SSST ^SOlChe H ^{n S} P? ^cherkrei s stored 6 ₅ a shortening of the Z? ^Integrators ™ sense signal corresponds to a delay of the originally called by UrrSK ^Zoitacllse and in synchronism with the input signal sprungh _chen signal obtained after SSSS .ae ^w ^ rend the computing circuits F ι g. 10, even if the query period is less than SSSe ^ Sf ^enoden · ^{WO no calculation} S

power generation can be switched.

Accordingly, a time division multiplexing circuit according to the invention can not directly with a such universal analog computer can be used. By means of the additional circuits mentioned above can use the present invention in conjunction with a conventional general purpose analog computer be used.

Claims (2)

Patent claims: 1. Time-division multiplex analog computer with a large number of input channels, with at least one A computing circuit connected to it via a first sampling switch and with it as well via a synchronous to the first sampling switch working second sampling switch connected output integrators, thereby characterized in that the time constant of each integrator is related to the closing time of each probe contact to the cycle period of the probe switch versus the value for one Single-channel operation is shortened and that each integrator during the closing time of his The scanner contact on the second scanning switch is in the computing state and otherwise in the hold state. 2. Time division multiplex analog computer according to claim 1, characterized in that the second sampling switch is delayed compared to the input-side sampling switch. 1 sheet of drawings 109 536/161