DE146613T1 - METHOD FOR PRODUCING SEMICONDUCTOR STRUCTURES. - Google Patents

Claims (9)

PATENT Attorney DIPL.-ING. KURT KAHLER D - 8931 WALKERTSHOFEN Raiffeisenstrasse 4 Telephone (0 82 39) 3 41 5th June 1985 3466 / EPC European patent application 84 902 421.1 NCR CORPORATION LTD.
15th Claims 1. A process for producing silicon-on-insulator structures on a semiconductor wafer comprising the steps of: etching a silicon substrate to regions (13, 14) _t form of silicon and covering the tops and sides of the silicon regions (13, 14) with Silicon etchant masks, characterized by the steps of etching the silicon substrate between the silicon regions (13, 14), to increase the relative height of the areas (13, 14); Oxidizing exposed silicon to that covered silicon is electrically isolated from the silicon substrate to silicon islands (19, 21) form; Depositing a dielectric layer (24) to a thickness greater than the height of the islands (19, 21); Forming a planar polymer layer (28) over the dielectric layer; simultaneous Etch the polymeric (28) and dielectric (24) layers to form polymeric and dielectric material at essentially the same speed removing until the polymer layer (28) is removed; and simultaneously etching the dielectric layer (24) and the electrically isolated silicon to dielectric material and silicon with essentially same speed to remove. 2. The method according to claim 1, characterized in that the steps of etching the silicon substrate between the silicon regions (13, 14) to increase the relative height of the silicon regions (13,14) having anisotropic etching to a depth proportional to the width of the silicon regions (13, 14) is. 3. The method according to claim 2, characterized in that the step of forming a planarized polymer layer (28) over the dielectric layer (24), depositing and flowing back of polystyrene or polymethyl methacrylate includes. 4. The method according to claim 3, characterized in that that the step of depositing a dielectric layer (24). a plasma-promoted chemical vapor deposition of silica. 5. The method according to claim 4, characterized in that that the step of depositing a dielectric layer (24) is preceded by the step of stripping the covering material from the silicon islands (19, 21). 6. The method according to claim 5, characterized in that that the step of oxidizing exposed silicon until the covered silicon is electrically isolated of the silicon substrate includes thermal oxidation to remove silicon dioxide to the plane of the to grow covered silicon. O U6613 7. The method according to claim 6, characterized in that the step of covering the tops and sides the silicon regions (13, 14) includes: forming a silicon nitride layer (11) over the silicon regions (13, 14) that already have PAD oxide (2), silicon nitride (3) and silicon dioxide (4) on their Have tops; and anisotropic etching of the. Silicon nitride layer (11) around the silicon dioxide (4) on the tops of the areas (13, 14) and the silicon substrate (1) between the silicon areas (13, 14) to be exposed. 8. Method of making silicon-on-insulator structures on a semiconductor die comprising the steps of etching a silicon substrate to form areas (13, 14) of silicon to form; Covering the tops and sides of the silicon areas (13, 14) with Silicon etchant masks characterized by the steps of etching the silicon substrate between the Silicon regions (13, 14) for increasing the relative height of the silicon regions (13, 14); and oxidizing of exposed silicon until the covered silicon is electrically isolated from the silicon substrate, to form silicon islands (19, 21). 9. A method of planarizing the surface of a semiconductor die having silicon islands (19, 21), characterized by the steps of: depositing a dielectric layer (24) to a thickness greater than the height of the islands (19, 21), forming a leveled polymer layer (28) over the dielectric layer (24), simultaneous etching of the polymer (28) and dielectric (24) layers to be polymeric and remove dielectric material at substantially equal rates until the polymer Layer is removed; and simultaneously etching the dielectric layer (24) and the silicon islands (19, 21) to dielectric material and silicon -4- remove at substantially the same speeds.