DE1449533B2 - ARRANGEMENT FOR THE STORAGE AND PROCESSING OF DATA IN A DATA PROCESSING MACHINE - Google Patents

Description

held characters are generally addresses that enable the data with which these Operation to be performed select in memory.

For example, an instruction related to addition exists other than the characters that contain the Define the addition operation from two addresses which relate to the two to be added Refer to characters. The removal of this command from the memory supplies the addresses of these characters. These two addresses then enable these two characters to be extracted from the Storage. Then the addition operation is performed on the characters thus extracted.

Machines are known in which all commands consist of a precisely defined number of characters. Such commands are called "fixed-length commands," and the consecutive characters that make up each command reside in one or more reserved rows of memory in consecutive ^: memory locations. In machines of this type, the procedure is generally such that each row in the rows containing the instructions is completely filled and only contains characters which belong to the same instruction. In this way, each instruction is always completely contained in the same number of N rows. This measure has the advantage that the commands can be taken very quickly from the memory. It is sufficient, as has already been seen, to make the selection by supplying the address of a character contained in a row so that all characters of the instruction lying in this row can be taken from the memory in one cycle. Thus, using memories which can contain multiple characters per row, a fixed length instruction contained in N rows can be extracted from memory in a significantly reduced number of N cycles, or whatever comes out , in a much shorter time than in the case of character-by-character extraction. A disadvantage of this method of operation is that commands of a fixed length have unused characters and even spaces in their structure, which requires a larger memory space for the storage of such commands than when using so-called commands of variable length, in which each command is given the variable number of Assigns signs necessary for it to retain its meaning. As a result, the use of fixed length instructions results in a significant loss of memory space which could advantageously be used to store other characters.

In order to remedy this disadvantage, machines have been implemented in which the in memory registered commands have a variable length. As a result, these commands are in series in the memory recorded so that the same memory row can contain characters corresponding to two belong to different commands next to each other. This gives you the ability to record of the memory is optimally used and a loss of memory space is avoided.

The object of the invention is to create an arrangement of the type specified at the outset which makes it possible to those required for recording programs with such commands of variable length To reduce storage space even further.

According to the invention this is achieved in that each direct address stored in the memory occupies all memory locations of the same memory row that each of the indirect addresses (identifier) contains a fixed number of characters that are at most half the number of characters in a direct The address is that to the output of the memory on the one hand and to the second address register on the other hand an intermediate register is connected, the capacity of which is equal to the maximum number of characters that can be contained in a complete memory row that an identifier register is provided, whose capacity is equal to the number of characters forming an identifier, and on the one hand to the Intermediate register is connected so that there is a part of a taken from memory Receives command-forming identifier, and on the other hand is connected to the selection register, so this identifier to the selection register and from this to the selection devices of the memory for selection a direct address is transmitted, and that the direct address is then taken from the memory, successively to the second address register, to the dial register and then to the Selection devices of the memory for selecting a size to be processed is transmitted.

In the arrangement according to the invention, each identifier enables, with the aid of special wiring of the machine, the selection of one and only one memory row which contains characters which form an address of a variable to be processed. Thus, the activation of the memory on the basis of an identifier results in the selection of a memory row which contains the direct address of the variable to be processed. The advantage of this mode of operation is particularly noticeable when the same direct address is found several times in the commands of the program. In the systems used up to now, each memory location was identified by a direct address with η characters, and in order to specify a specific memory location it was therefore necessary that each direct address that formed part of a stored command has η characters. In the course of the program, the same direct address could appear again in another stored instruction, again containing η characters. If the same direct address was used k times in the course of the same program to extract the same size from memory, it would take up a total of kn characters in memory. In the arrangement according to the invention, however, each identifier is formed, for example, from two characters, which only requires a space of two characters in the memory, but to which the η characters of the direct address, ie the address of the size that can be selected with this identifier to be added. This direct address in turn enables a variable to be taken from memory. The total storage space required is therefore n + 2 characters. If it becomes necessary again in the course of the program to take this size from the memory, it is sufficient to select the memory row again, which contains these η characters of the direct address, with the help of the same identifier as before

only requires two characters, whereupon this direct address can be used to extract the size to be processed from memory. Two characters forming an identifier are sufficient to remove the required direct address from the memory. If this direct address is used / c times in the course of a program, it must be taken from the memory each time using the same identifier, which in total k requires identical identifiers. The total required for recording storage space is then "sign of the direct address and 2k sign for the whole of these identifiers, for a total of / i - 2 k characters.

The gain obtained by the invention in recording commands and addresses in memory at characters becomes obvious when the same direct address in the course of the same program is used so often that the following applies:

2k,

72 - 2

So if you use direct addresses that consist of / i = 3 characters, this occurs with the invention achievable profit in appearance when the same direct address

/ C

-2

= 3 times

used during the course of the program. If direct addresses are used that consist of μ = 4 characters will be a win for

35

k =

= 2

and the profit is even greater if one uses direct addresses whose number η of characters is even greater. The advantage of the invention is thus clearly recognizable, since on average each direct address recorded in the same program is used more than two or three times. It follows that this address system is particularly advantageous when it is applied to memories which have a large character capacity and accordingly use direct addresses consisting of four, five or more characters.

Another advantage of the invention is that the programming of the machine is synchronized, because the direct addresses of the capital letters to be processed are stored separately for each program in the memory, so that the Bc.cnle in their structure are then in place the direct ^ad r « ^scn . ^{of the} variables can contain identifiers and the programmer S ₁ Ch ment setting up the program has to deal more with the memory location which are accepted in the memory by the direct addresses of the variables. On the other hand, contains the ur d e identifiers character repertoire used Nithi 3 <e; n de digits, but also the usual "■; -nX ^{A1 P've} * s, making this Kennun- R ^" ^mnen l ^otec hnischer value is issued? .

CiV \ v "T ^dan ? ™ ^{connection to} one another and be of variable length, but this property is not indispensable, and they can contain a variable number of identifiers in their structure depending on the operation to be carried out Arrangement according to the invention possible to give a machine the greatest possible adaptability in operation.

It is no longer possible to use the same information of the memory at two different addresses conventionally Kind of give. Because of the design, the address is one and only one place of the Memory allocated, and vice versa. On the other hand, it is possible with the arrangement according to the invention, to use several different identifiers for the same size in memory, what from Programmers are very welcome.

An embodiment of the invention is shown in the drawing. In it shows

F i g. 1 schematically shows the structure of a machine in which the arrangement according to the invention is applied will,

F i g. 2 schematically shows the main components of a memory of the machine for a better understanding the mode of operation and the peculiarities of the connections between this memory and the rest the machine,

F i g. 2 a an idealized hysteresis loop of the magnetic material, from which the magnetic cores of the memory from F i g. 2 exist,

F i g. 3 an overview of the association of the F i g. 3 a to 3 ζ and

F i g. 3 a to 3 z show a more detailed circuit diagram of the circuit diagram shown in FIG. 1 shown machine.

general structure

A machine using the wired system of indirect address systems is an example schematically in FIG. 1 shown. For a better understanding of the structure and the mode of operation of this machine, the various components are represented in the form of blocks or rectangles. Among the organs which the in F i g. 1, one recognizes a quick storage device 11 assumed to be composed of, for example, magnetic cores; however, it can also be any other types of random access high-speed saves are used, d. H. of quick saves, in which at any point in time any character contained in the memory, regardless of this Content that is accessible. This memory contains all the characters (letters, digits, various other signs), which in the course of the operations carried out inside the machine should be used. Each character is made up of a combination of six binary digits (1 or O), which indicates the special meaning of the sign. It is expediently assumed that the entirety of the memory cores is distributed according to a structure in rows, columns and rows. Corresponding the particular illustration of FIG. 1 consists of a defined number of characters in each row 11a. For example, in the case of the FIG. 1 machine shown the memory five characters per row, forming the characters contained in this way in the same row a "group of characters". When excited any row of memory to indicate a group of characters this group can be defined by means of a set of

209 539/315

Lines M101 can be taken from the memory or entered into the memory by means of a set of lines M 102 by choosing an X coordinate and a Y coordinate which go through the desired row. The coordinate X is determined with the aid of an Xf selector 12 and the coordinate Y with the aid of an F selector 13. The selectors 12 and 13 are connected to a registration and decryption element 14 which contains a variable called the address and defines the location of a character or group of characters in memory. In the case of the FIG. 1, a memory is assumed which can store up to 40,000 characters, these characters being contained in 8,000 rows of five characters each. In order for each memory location to be defined, 40,000 different addresses must be available. The location of the in the upper left corner of the memory of FIG. 1 lying character is defined by the address 00000. The position of the character in the lower right corner of this memory is defined by address 39999. To specify the location of a character in the interior of the memory, an address composed of five characters must therefore be used. For example, an address is written 00016 and not just 16. Part of the address contained in the registration and decryption organ 14 is decrypted by the latter and sent to the selector 12 via a set of lines M 103. The other part is decrypted by the registration and decryption organ 14 and sent to the selector 13 via a set of lines M 104. However, the selectors 12 and 13 can only come into operation under the action of a read control signal LE , which comes from an auxiliary control generator 15, or under the action of a write control signal EC, which comes from the same generator. The read control signal is sent from the generator 15 to the selectors 12 and 13 in the form of a positive voltage of a very short duration, that is to say a pulse, when a group of characters is to be removed from the memory. The write control signal is sent in the form of a pulse from the generator 15 to the selectors 12 and 13 when a group of characters is to be entered into the memory. An intermediate register 16, which can contain a group of five characters, is used to temporarily hold a character group that has just been removed from the memory or is to be introduced into the memory. In particular, this register enables a character group that has just been removed from the memory to be stored again. The transmissions of the groups of characters between the register 16 and the memory depend on transmission organs 31 and 32, which are inserted into the line sets M101 and M 102 and permit the transmissions when they are under the effect of control signals coming from the generator 15; organ 31 receives from this generator a control signal F14 in the form of a pulse when a transfer is to be carried out from memory to register 16, while organ 32 receives a control signal F17 from generator 15 when a transfer is to be carried out from register 16 to memory . In Fig. 1 it can be seen that further transmission organs 33 to 52 are present, which are the same as organs 31 and 32 and have the task of either allowing or blocking or controlling the transmission of characters or groups of characters between the other organs of the machine. If, for example, the organ 31 receives a control signal F14 from the auxiliary control generator 15, it controls the transmission of the five characters taken from the memory in the form of pulses or voltages of very short duration to a transmission organ 46 L. The organ 46 L has the task of transmitting to block or allow all or part of the group of five characters which come from organ 31 and are to be stored in register 16. Under the action of a selection indicator 20 , the organ 46 L can either allow the transmission of the five characters from the organ 31 to the register 16 or block this transmission or only allow the transmission of four of these five characters. The register 16 can transfer its content via the two organs 33 and 34 to a "five-character" connection register 17 which can contain five characters. This transmission is made possible by a control signal F16, which comes from the generator 15 and acts on the element 33 , as well as by a permit voltage, which comes from an instruction memory 19 and arrives at the element 34 via a line M 10 LM. The instruction memory 19 is used to store two instructions, one of which is called a "read command" and comes from a main control generator 30 via a line OL, while the other "word command" is called and is supplied by this generator 30 via a line OM. These two commands arrive in the form of pulses and are recorded in the memory 19. The register 16 can transfer one of the characters contained therein to a "single character" connection register 18, which can only contain one character. This transmission is made possible by a control signal F16 that comes from generator 15 and acts on element 33. In this case, an approval voltage supplied by the command memory 19 reaches the selector indicator 20 via a line M 10 LK , which in turn emits an approval voltage which arrives at the organ 35 via a line M 11 LK. Since the register 18 has the capacity of one character while the register 16 has the capacity of five characters, it is necessary to select which of the five characters is to be transferred from the register 16 to the register 18. This selection is made by the selection indicator 20, which acts on the organ 35 as a function of part of the address contained in the registration and decryption organ 14; this address part comes to the dial indicator 20 via a cable set M 12.

The transmission of the five characters from register 17 to register 16 is permitted by a control signal F15, which comes from generator 15 and, after passing through the instruction memory , is transmitted in the form of a control signal F15 EM which acts on an element 37. The organ 37 then sends the five characters of the register 17 in the form of impulses to an organ 46 E. The organ 46 E comes into operation under the action of an approval voltage supplied by the dial indicator 20 and then allows the five characters to be transferred to the register 16 .

An organ 36 enables a character to be transferred from register 18 to register 16. This Organ is set in action by a control signal F15 coming from generator 15, which after

11 12

the passage through the command register in the form of the following command and select them

a control signal F 15 EK is transmitted and taken out of the memory. That's why it will

the organ 36 acts. The organ 36 then sends Register24 called "Program Address Register". the

the character contained in the Reaister IS in the form of the direct address contained in register 23 can be via

Impulses to organ 46 E. So that this symbol to 5 a cable set M 14 with the help of an organ 48,

is transferred to the correct place, which it is under the control coming from the generator 30

the five possible places in register 16 occupancy signal F 20 is activated, for registration

men should, the dial indicator 20 is sent by the corresponding and decryption device 14,

corresponding tensions on the organ 46 E. Each character contained in register 18 can be

Oraan 38. The by a control generator 30 xo neither a sign of a size to be processed

incoming control signal F 09 activated or a character belonging to a command. in the

enables the transfer of the characters from the last case, the character can either be a special

Register 17 to an address register 23, which is five of its characters, called the T.O. character

May contain characters. An organ 39, which is determined by a and the type of operation to be performed (addi-

from the control generator 30 coming control signal FlO 15 tion, subtraction, comparison, transmission, etc.)

is put into action, enables the transfer there, or part of an indirect address,

of the characters from the address register 23 into the register is called the identifier. There is an identifier

17. The register 23 is for receiving the direct two characters, for example, and it can be in

Address of a character in the memory is determined. It should contain a register 27, the identification register

is connected to an address changing device 26, so called ster.

which has the task of containing the register 23 contained in register 18 only one character

direct address by adding or removing _can become the defining identifier

/ to change a given size. For the sake of explanation, characters are taken one after the other from the memory; it is assumed that this variable is temporarily stored in the register 18 in the present case and then has the value +1, for example. For 25 _TO m Register transmitted 27th This transfer forms every direct number contained in register 23 with the aid of an organ 43, which is connected to the register organ 26 the same number, increased by 1, 18 by a line set M15 and thus enables the information contained in register 23 - to continuously change the address tene by a control signal coming from the generator 30, that is to say, weiterzu- p21 is put into action. So two will count. This further counting can, however, only be carried out with 30 transmissions, so that the register 27 can take place with the aid of an organ 49 which is activated by a control signal FI1 coming from the generator 30 which forms an identifier with the two characters. A verification added to register 27 is set. Two registers 24 and 25 are used in the key 29 enables the conversion of an identifier contained in principle each for receiving a five-character register 27 into an address between the existing direct address of an address to be processed 35 0000 and 7995, this address being a character. So if an operation, for example, comprises four characters and ends either with the number 0 an addition, subtraction or a comparison with or with the number 5. The address obtained in this way, two operands, each consisting of one character, can be made via a set of conductors M16 by means of an organ that A and B is to be carried out; 22 is put into action, to Regi while the register 25 transfers the direct address of the strier- and decryption organ 14 who contains operands B. If the operands have multiple den. The identifier contained in register 27 can be contained in characters, it is expedient to transfer the direct identifier register 28 so that

^N l addresses of registers 24 and 25 to be counted further, possibly a second identifier in register 27

so that an operation can be stored one after the other with all characters 45. As already briefly in the

these operands can be made. This introduction has been explained, serves each of two

Addresses are passed on by making a character identifier to extract an in

simultaneous interchanges of the contents of the three direct ones contained in a row of the memory

Register 23. 24 and 25, register 23 being its address of five characters from memory. These

Transfers the content to register 24, register 24 50 address is then used to extract a line

transfers its contents to the register 25 and the chens from the memory, which then according to the

Register 25 handles its contents in register 23 via specification of the T.O. character of the command

wearing. \ Venn the address to be continued will be in the. To avoid any confusion,

The course of these interchanges in register 23 is the result of the conversion of an identifier

det, a control signal FIl acts on the organ 49, 55 as the address obtained by means of the encrypted 29

whereby the address in this register is changed to designate an intermediate address. Corresponding

VTI * -> - ^V J ^rtauschun g ^s of the contents of the register is called a direct address, the address,

) h λ ^ ^{gen with the help of Or} S ^{anen 50} ' ⁵¹ ' ⁵² > which is taken from the memory if

vveicne by a coming from the control generator 30 - a selection made on the basis of an intermediate address

aes control signal FOl is activated 60 at the same time. Of course, the address

vveraen. In addition, as can be seen further below, which the registration and decryption organ 14

AH λ , ^{§Ister 24} as well, which can accommodate either an intermediate address

rtoresse be the last character of one from the memory, if this address is transmitted via the organ 47

ΙΤΙ i ^S to contain temporarily, gen will, or a direct address if this ^Se Ad d

»ΤΤΙΤΙ i ghend to contain gen will, or a direct address if this

!! «« • htm ir ^Se · Adresse, thanks to the 65 address is transmitted via organ 48. That

emh-.liiT λΤ ^m registers 22, 23 and 24 TO characters can, for example, have the + sign

traeen and ' ^{^ eat ' on} register 23 to be over- or the sign - if an instruction requires a

Then you can continue to pay in order to trigger the addition or subtraction process.

The character to be processed, taken from the memory and then stored in the register 18, is then transferred to a processing element 22 with the aid of an element 40 which is activated by a control signal F 23 from the generator 30. The processing element 22 can be an operator, for example an addition circuit, a comparison circuit or any other processing element of an edge unit. In order to facilitate understanding of the description, it is assumed that this processing means is an addition-subtraction circuit. The characters to be processed (ie to be added or subtracted) are introduced into the addition-subtraction circuit 22 one after the other. As soon as the operation has been carried out, the result is transferred to the register 18 via an element 42 which is activated by a control signal F 24 coming from the generator 30. The TO symbol, which defines the type of operation to be carried out (addition or subtraction), is taken from the memory before the operation is triggered, then stored in register 18 and finally by an element 41 that receives a control signal F from generator 30 25 is set in action, transmitted to a command decryptor 21. The operation carried out by the addition-subtraction circuit 22 is triggered by a control signal F 19, which comes from the generator 30 and arrives at the instruction decoder 21, which in turn is sent to the addition-subtraction circuit 22 depending on the type of operation to be carried out either supplies an addition control signal F 30A or a subtraction control signal F 30 S depending on the information obtained by deciphering the TO sign.

If two identifiers are used in the course of the same command, those identifiers are in contained in registers 27 and 28. The registers 27 and 28 can manage their content with the help of two organs 44 and 45, which by a control signal F 27 coming from the generator 30 simultaneously be put into action.

The auxiliary control generator 15 can be set into operation by a start-up control signal DC which comes from the generator 30. By sending a single control signal DC , the generator 30 triggers the delivery of a sequence of control pulses via the generator 15, which enable each storage or removal of a character or a group of characters from the memory. The use of an auxiliary generator of the type of generator 15 enables the number of circuits of the main control generator to be simplified, but it is also possible to provide a different structure in which only a single generator is used from which all the control pulses then originate, or on the contrary any other type of construction in which, in addition to the main control generator, as many auxiliary control generators are used as is determined by the diversity of the machine.

The "single character" connection register 18 can in principle have different edge units (Punch card scanners, punches, printers, locking devices, control arrangements, etc.) through connections be connected, which for simplification in F i g. 1 are not shown. These connections otherwise do not form part of the invention. In a corresponding manner, the register 17, depending on the Information processing requirements with different peripheral units or different organs, such as display or control organs, be connected by connections, which for simplification are not shown in the drawing.

Description and way of working
the storage elements

It should now be the structure and operation of the in F i g. 1 schematically indicated quick storage 11, this memory is only an example for explaining the invention represents.

F i g. 2 shows a detail of this memory with a group of four toroidal cores T 8, T 9, T 18, T19; In reality, this memory contains 240,000 toroidal cores for storing 40,000 characters. Each toroidal core consists of a magnetic material with a practically rectangular hysteresis loop and can assume two stable magnetization states, which are characterized by a positive remanent induction + Br and a negative remanent induction -Br . This makes it possible to record or extract binary information from each of them: The arbitrarily chosen value 0 corresponds, for example, to the state - Br, while the elementary value 1 then corresponds to the state + Br. . As the hysteresis loop shown in Figure 2a, applying a magnetic field + 2H calls a toroidal the transition of this ring core from state 0 to state 1 projecting so that it, an information is recorded, and applying a magnetic field - 2 H brings the toroidal back to state 0, generating an output pulse, while a + H or - H field does not change the state of the core.

In Fig. 2 it can be seen that four lines are passed through each of the four toroidal cores Γ8, T9, Γ18, T19 , two lines being used to select a toroidal core, while the third line Ll-I is used to extract a binary digit from the memory and the fourth Line Zl is an inhibition line. A horizontal line YO goes through the toroidal cores Γ 8 and Γ 9, a horizontal line Yl goes through the toroidal cores Γ18 and Γ19, a vertical line Z 8 goes through the toroidal cores T 8 and Γ18, and a vertical line X 9 goes through the toroidal cores T 9 and Γ19, while the lines Zl and Ll-I go through all four toroidal cores in sequence. So that the passage of the current through the line Y 0 is possible in one direction, one end of this line can be connected to the positive terminal of a current generator GY with the help of two power supply switches AEYBO and IAYBO, while the other end of this line can be connected with the help of two Ground switches MEYO and / MYO can be connected to ground. In the same way, the passage of the current through the line Yl in one direction is made possible by two power supply switches AEYBO and IAYBO , which connect one end of this line to the positive terminal of the generator GY , and by two ground switches MEYl and / MYl, which connect the other end

connect to ground. The negative terminal of the generator GY is in turn connected to ground. A group of two lines Y OA and YOB, which are connected to two switches MLYO and ALYBO , respectively, which are shown in the FIG. 2, allow the direction of the current in the line YO to be reversed. In the same way, the reversal of the current direction in the line Yl is made possible by two lines YlA and YlB , which with two switches MLYl and ALYBO in the in FIG. 2 are connected. In an analogous manner, a group of lines XSA, XSB and switches MLXS, IMXS, MEXS, IAXB 9, AEXB 9, ALXB 9 enable the current to pass through line X 8 in one direction or the other, with the power supply switches IAXB 9 , AEXB 9 and ALXB 9 are connected to the positive terminal of a current generator GX , the ground switches IMX 8, MLX 8 and MEXS are connected to ground and the negative terminal of the generator GX is connected to ground.

) and all of these elements are arranged as shown in FIG. In the same way, a group of lines X9A, X9B and switches MLX9, IMX9, MEX9, IAXB9, AEXB 9, ALXB 9 allow the passage of current through line X 9 in one direction or the other, with the power supply switches IAXB 9, AEXB 9 and ALXB 9 are connected to the positive terminal of the generator GX , the ground switches IMX9, MEX9 and MLX9 are connected to ground and all of these elements are in the form shown in FIG. 2 are arranged in the manner shown. One end of the line Zl is connected to ground, while the other is connected to a switch ZE . A write current generator GE, the negative terminal of which is connected to ground, has its positive terminal connected to the switch ZE via a write switch IE . A switch ZL, which corresponds to the representation of F i g. 2 is connected, is in the line Ll-I.

All of these switches are called electrical switches

■>, shown, but it is obvious that they too can be formed by any other device, for example a coincidence circuit, an electronic switch, a relay or the like.

The switches AEXB 9 and AEYBO are actuated simultaneously by a write control signal EC-I, which is symbolically represented by an arrow and comes from the control generator 15 of FIG. The switches MEZ 8 and MEX 9 on the one hand and the switches MEYO, MEYl and ZE on the other hand are actuated simultaneously by a write control signal EC-2 coming from the generator 15. The switches ALXB 9 and ALYB 0 are actuated simultaneously by a read control signal LE-I coming from the generator 15. The switches MLX 8 and MLX 9 on the one hand and the switches MLYO, MLYl and ZL on the other hand are actuated simultaneously by a read control signal LE-2 coming from the generator 15. The power supply switch IA YBO can be operated by applying a current, which is symbolically represented by an arrow YB 0 and from which in FIG. 1 shown registration and decryption organ 14 comes. In the same way, the power supply switch IAXB 9 can be actuated by applying a current, which is symbolically represented by an arrow XB 9 and comes from the registration and decryption element 14. The ground switches IMX 8, IMX 9, IMYO, IMYl can each be operated separately by currents which are symbolically indicated by arrows CX 8, CX 9, CYO and CYl and come from the decryption element 14. Finally, a current symbolically indicated by an arrow £ 1-1, which corresponds to the value 1 of the information to be entered into the memory, enables the circuit of the generator GE to be interrupted by its action on the switch IE.

If, for example, information of the value 1 represented by the arrow E1-1 is to be stored in the toroidal core Γ18, assuming that all toroidal cores are originally in state 0, the decryption element 14 emits the currents IBO, XB 9, CXS and CYl . Under the action of the current YBO the switch IAYBO closes. The current XB9 closes the switch IAXB 9, while the switches IMX S and IMYl close under the effect of the currents CXS and CYl, respectively. The organ 15 then emits the write control signal EC-I, which closes the switches AEYBO and AEXB 9 , and then the write control signal EC-2, which closes the switches MEZ 8, MEX 9, MEYO, MEYl and ZE .

Since the ground switches IMXS, MEXS and the power supply switches IAXB 9 and AEXB 9 are closed, a circuit goes from the generator GX via the switches IAXB 9, AEXB 9, the line Z 8 and the switches MEZ 8, / MZ 8 to ground. Furthermore, since the ground switch / MYl, MEYl and the power supply switch IAYBO, AEYBO are closed, a circuit goes in the same way from the generator GX via the switches IAYBO, AEYBO, the line Yl and the switches MEYl, / MYl to ground. Of the four lines Z 8, X 9, YO, Yl, only lines Z 8 and Yl have a current flowing through them, each of which generates a magnetic field + H in the toroidal cores through which it passes. As a result of the interruption caused by the switch IE under the effect of the current E 1-1, no current flows through the line Zl, so that the toroidal core ΤΊ8, which is the only one under the effect of a resulting field with the value + 2H , changes to state 1. If the binary value 0 were to be stored in this toroidal core, it would be sufficient that no current El-I acts on the switch / E. A current from the generator GE would then flow through the line Z1, which generates a field with the value - H in the four toroidal cores. This field —H would be superimposed in the toroidal core Γ18 on the field + 2H generated by the lines Z8 and Yl and thus result in a resulting field of the value - \ - H , so that the toroidal core Γ18 would remain in the 0 state.

To remove the binary value stored in the toroidal core Γ18, the registration and decryption element 14 first emits the currents YBO, XB 9, CY 8 and CX9 . Under the action of these currents, the switches IAYBO, IAXB9, IMXS and / MYl close. Then the organ 15 outputs the read control signal LE-I, which closes the switches ^ ILYßO, ALXB 9 , and then the read control signal LE-2, which closes the switches MLZ8, MLZ9, MLYO, MLYl and ZL . It is easy to see that only through the lines Z 8 and Yl currents flow whose

ono KQO λπ ς

Direction is opposite to the direction that would be required for recording. Correspondingly, the currents in the toroidal core T18 produce a resulting field of the value -2H. If the toroid was originally in state 0, nothing happens; if, on the other hand, it was in state 1, i.e. if it contained a binary value 1, the field changes from state 1 to state 0. As a result, a pulse is generated on the sampling line Ll-I.

It should be noted that the read control signals LE-I and LE-2 or the write control signals EC-I and EC-2 close the corresponding switches only during the times which are necessary for removing or entering a character or a group of characters from the memory .

Description of the machine

Set in Figs. 3a to 3k, 3m and 3p to 37 the semicircles or circuits with the sign + that have a point Semicircles and circuits, the semicircles without signs mixed circuits and the triangles control circuits or coincidence circuits. These circuits are well known and therefore are used not described. It is recalled, however, that a mixer circuit does not have a particular logic Function performs and that its task is to generate positive impulses which are different to its own Inputs are fed to be transmitted to their own output so that any retroactive effect an incoming pulse to the other inputs via one of these inputs is avoided. It is also then remembered that each coincidence or control circuit has two inputs of which the one input (pulse input) is marked by a dot, to it from the other input to distinguish, This coincidence circuit transmits the incoming via its pulse input Pulse to its output only when its other input (control input) has a positive voltage is brought of a certain period of time.

Structure of the memory array

The structure of the memory array 11 will now be described. Before making a detailed description of the machine, it must be remembered that the toroidal cores Γ8, T9, T18, T19 of FIG. 2 are all in the same plane of the memory. The memory 11 described as an example consists of thirty superposed toroidal core levels, each level containing 8000 toroidal cores which are arranged in rows and columns. The toroidal cores lying one above the other in the various levels form a row of 30 toroidal cores. Since each character in the memory is recorded in a six-digit binary code, six toroidal cores are required to represent the character in the memory. Therefore, a row of thirty toroidal cores can store five characters, and it can finally be assumed that the memory is made up of 8000 rows of five characters, these 8000 rows being comprised of 80 blocks, each of which is thus made up of a hundred numbers . In each level of each block, the toroidal cores are arranged at the intersections of ten horizontal lines YO to Y 9 and ten vertical lines ZO to X9 . In Fig. 3a a memory with 80 blocks is shown, of which only the nine blocks 11-50, 11-51, 11-52, 11-60, 11-61, 11-62, 11-70, 11-71, 11-72 are shown. Four half-selectors 12-1, 12-2, 13-1 and 13-2 are used to select a row. These half-selectors are shown in Figures 3a and 3b. The Z-voter 12 of FIG. 1 consists of the two half-voters 12-1 and 12-2, and the Y-voter 13 of FIG. 1 consists of the two half-voters 13-1 and 13-2. As shown in FIGS. 2 and 3a, the half-selector 12-2 consists of ten power supply switches IAXBO to IAXB 9, which are actuated by currents XBO to XB 9 , ten write switches AEXBO to AEXB 9 and ten read switches ALXBO to ALXB 9 ; it enables the connection of the positive pole of the generator GX with all the lines X belonging to the eight blocks whose reference numbers end with the same number, for example all the lines X of the blocks 11-02, 11-12, 11-22, 11- 32, 11-42, 11-52, 11-62 and 11-72. In the same way, the half-selector contains 13-2, as in FIG. 2 and 3a is shown, eight power supply switches IA YBO ^ - to IAYBl, which are operated by currents YBO to YBl% , eight write switches AEYBO to AEYBl and eight read switches ALYBO to ALYBl; it enables the connection of the positive pole of the generator GY "with all lines Y belonging to the ten blocks whose reference numerals are written with the same penultimate digit, for example with all lines Y of blocks 11-70, 11-71, 11- 72, 11-73, 11-74, 11-75, 11-76, 11-77, 11-78, 11-79. The half-selector 12-1 contains, as shown in Figs. 2 and 3a, thirty ground switches 7MZ0 to IMX 9 (which are operated by currents CZO to CX9 ), MEXO to MEZ9, MLXO to MLX9; it enables one of the ten lines ZO to Z 9 to be connected to ground in each block Half selector 13-1 thirty ground switches / ΜΓ0 to IMY 9 (which are operated by currents CYO to CY9), MEYO to MEY9, MLYO to MLY9; it enables one of the ten lines YO to Y 9 to be connected to ground in each block.

For the sake of simplicity, not all switches of the half-selectors are shown in FIG. 2 shown. If one of the currents ZBO to XB9, YBO to YBl, CZO to CX9 or CYO to CY 9 acts on each of the four half-selectors, all lines ZO to Z 9 and YO to Y 9 of the thirty levels of one of the eighty blocks in Brought into contact with the positive terminals of the generators GX and GY , while one of these row lines ZO to Z9 and one of these column lines YO to Y9 are connected to ground in each of these levels. Thus, at each level, a current goes through each of these last-mentioned lines, and a toroid row is selected. In Fig. 3 a and 3 b, the four half-voters are symbolically indicated by rectangles. To simplify the drawing, the generators GX, GY and GE, the switches ZL, ZE and IE and the ground connections are not shown in these figures. In a corresponding manner, to simplify the drawing, only the read lines between the four half-selectors and the memory are shown in these figures, but it is assumed that in reality the number of lines is doubled because of the lines used for writing. The over-

iraüuns the currents XBO to XB 9, YBO to YBL, CXO to CX9, CYO to CY9 serving lines are in certain parts of Fig. 3a and 3b summarized such that it four sets of lines Λ / 103-2 M 104-2 M 103-1, M104-1, all of which come from the decryption unit 14. Six lines £ 1-1 to £ 1-6 are used to record the six binary digits representing the code combination of a character in the memory, while six lines Ll-I to L1-6 are used to extract this code combination from the memory. The recording of five characters in a memory row takes place simultaneously with the help of thirty lines El-I to £ 1-6, £ 2-1 to £ 2-6, £ 3-1 to £ 3-6, £ 4-1 to £ 4-6 and £ 5-1 to £ 5-6, while the removal of these characters simultaneously with the help of thirty lines Ll-I to L1-6, L2-1 to L2-6, L 3-1 to L 3-6 , L 4, -1 to L 4-6 and L 5-1 to L 5-6 succeed. These lines are combined in such a way that they form two line sets M101 and M102. The line set M101 ends at a group of thirty coincidence circuits 3111 to 3116, 3121 to 3126, 3131 to 3136, 3141 to 3146, 3151 to 3156, which form the transmission element 31 of FIG. For the sake of simplicity, only the coincidence circuits 3111 to 3116 and 3151 to 3156 are shown in FIG. 3b, which are used to transmit the code combinations of the first and the fifth character. The same mode of representation is selected in Fig. 3a for the thirty coincidence circuits 3211, 3212, 3213 ... 3254, 3255, 3256, which form the transmission element 32 and from which the line set M102 branches off.

Registration and decryption organ

In Fig. 3 b, 3 c and 3 h, the organs whose reference number begins with 14 belong to the registration and decryption device 14.

The address of a character to be taken from memory consists of five decimal digits, which are encoded according to the well-known binary code, which is referred to as the "binary-encoded decimal code" or 8-4-2-1 code. Each decimal digit of the address is represented in this code by a combination of four binary digits. As can be seen in FIGS. 3c and 3h, the one-digit number of the address can be stored in its binary-coded form in four flip-flops 14 £ 71, 14 L-2, UUA and 14 U 8. The numeric digit can be stored in four toggle circuits 14Dl, 14 Z) 2, 14 D 4, 14 D 8, the hundreds digit in four toggle circuits 14Cl, 14 C 2, 14 C 4, 14 C 8 and the thousands digit in four toggle circuits 14Ml, 14 M 2, 14 M 4, 14 M 8. Two additional flip-flops 14 DM1 and 14 DM 2 are sufficient to store the ten-thousand digit, which is never greater than the decimal digit three, because the address is always between 00000 and 39999. These flip-flops ίο together form a selection register called the address storage register RAM; they can by a control signal F 18, which is from the in F i g. 3 a shown control generator 15 comes to be reset to zero. Each of the decimal digits contained in encrypted form in the flip-flops of the register RAM is decrypted by organs which are determined by the functions shown in FIG. 3 b, 3 c and 3 h illustrated AND circuits 1410 to 1457 are formed. These AND circuits are arranged in such a way that only one of the AND circuits 1410 to 1419 emits a positive voltage at its output, this voltage appearing at the output of the AND circuit 1410 when the circuits in the flip-flops 14 E / 1, 14 E / 2, 14Z74, 14 U 8 contained one digit is the digit 0, while it appears at the output of the AND circuit 1411 if this digit is 1, at the output of the AND circuit 1412 if this digit is 2, and finally at the output the AND circuit 1419 when this digit is 9. In an analogous manner, the AND circuits 1420 to 1429 are used to decrypt the tens digit, the AND circuits 1430 to 1439 to decrypt the hundreds digits, and the AND circuits 1440 to 1449 to decrypt the thousands digits. An OR circuit 1400 arranged at the output of the AND circuits 1410 to 1414 supplies a positive voltage at its output via a line 1460 whenever the ones digit between 0 and 4 is contained. An OR circuit 1405 arranged at the output of the AND circuits 1415 to 1419 supplies a positive voltage at its output via a line 1465 whenever the ones digit between 5 and 9 is contained. The AND circuits 1450 to 1457 effect a special decoding of the voltages which are supplied by the outputs of the flip-flops 14 DM1, 14 DM 2 and from the lines 1460 and 1465. The decryption performed by these AND circuits corresponds to the following table:

address Tens One And circuit, Zihntausnder j thousands Hundreds D. U whose output is a
positive voltage DM _M C. 0 to 9 0 to 4 leads ⁰ ! 0 to 9 0 to 9 0 to 9 5 to 9 1450 ⁰ i 0 to 9 0 to 9 0 to 9 0 to 4 1451 ^{1 !} 0 to 9 0 to 9 Obis9 5 to 9 1452 *; 0 to 9 0 to 9 0 to 9 0 to 4 1453 ; ^: 0 to 9 Obis9 0 to 9 5 to 9 1454 r; o to 9 0 to 9 Obis9 0 to 4 1455 i ; 0 to 9 0 to 9 Obis9 5 to 9 1456 : ο to 9 0 to 9 1457

^ '*' ^{which result} from the decryption of the address contained in the RAM register, sent to ^the half-voters 12-1,12-2,13-1,13-2.

21 22

Command memory circuit circuits 2OjBXI to 20EK5. then one

Pulse transmitted when a character is in memory

The command memory 19 recognizable in FIG. 3η is to be entered. The circuits20 LKl consists in particular of two flip-flops 1951 to 20 LK 5 or 20 EKl to 20 EKS and 19 B 2, which work so that the first in the 5 pulses come from two coincidence circuits state 1 when it goes from the Main tax 20LK or 20 EK. These two circuits are generator30 via a line OL receives a read command from the assembled Fig. 3h and 3η, while the second goes to state 1, as can be seen with the AND circuits when they are sent from the generator 30 via a line OM 19LK, 19EK of the command memory 19 connected, receives a word command; this main control gen- io Since the coincidence circuits are generally a rator 30 in FIG. 3 ζ shown. A positive pulse from the provided with a point A voltage appears at the output of an AND circuit gear only könnn transmitted when the other 19LK when only the flip-flop is 19 Bl in the input to a positive voltage, detects the 1 state. A positive voltage appears when a pulse sent from the control generator 15 to the output of an AND circuit 19 EM when there are 15 circuits 20LK and 20EK only the flip-flop 19B 2 is in state 1. F 12 either only via one of the two circuits A positive voltage appears at the output of one transmitted or blocked by both circuits AND circuit 19LM when the two toggle switch is activated. If a group of five characters in the obligations 19 Bl and 1952 are in the state 1, while memory to be input brings the zero A positive voltage at the output of an AND 20 actuating pulse FCZ the five flip-flops 19 EK, appear in the circuit when both Toggle state 0. Each of the OR circuits 2005, 2016, circuits are in state 0. The two flip-flops 2027, 2038 and 2049 are on the one hand with one circuits 1951 and 19 B2 can be reset to zero by one of the five coincidence circuits 20 LKl to the control signal FC 20LK5 coming from the control generator 15 and on the other hand by one of five each. 25 negation circuits 2005Λ, 2016A, 2027 A,

2038 Λ, 2049.4 each with one of the five coincidences

Dial indicator circuits 20EK1 to 20EK5 are connected. There

⁰ only the output of one of these Or-

The selector indicator contains in particular five OR circuits leading to a positive potential, receiving circuits 2005, 2016, 2027, 2038 and 2049, the 30 only one of the five circuits 20LKl to 20LK5 in the manner shown in Fig. 3h at the output of and only four of the five circuits 20 EK1 to AND circuits 1410 to 1419 of the registration and 20 EK S at their inputs a positive potential, decryption organ 14 are arranged. One so that in the case of taking a character from positive voltage appears only at the output of the memory of the circuit 20LZ a pulse OR circuit 2005 each time the one transmits, which is therefore one of the five toggle digits of the address 0 or 5 , whereby this number brings the number to state 1. For example, if there is an address in the four Kipp ™ registers RAM in its binary-coded form which ends with the circuits 14 £ / 8, 14! 74, 14 U 2, 14Ul of the register number 7, only the output of the OdersterlL4M is stored is. A positive voltage circuit 2027 brought to a positive potential only appears at the output of the OR circuit 2016, 40 and the pulse supplied by the circuit 20LX if this number is 1 or 6. If this digit 2 is only transmitted via the circuit 20 LK 3, so or 7, the positive voltage only appears on the fact that it only the flip-flop 2053 in the state 1 output of the OR circuit 2027. When this brings. In the case of input of a character in the item 3 or 8, the Spannng appears at the initial storage finally transmits only the circuit path of the OR circuit 2038. Finally appear 45 20EK a pulse in a manner analogous to four of these voltage only at the The output of the OR circuit brings five flip-flops to state 1.
2049 if that digit is 4 or 9. A series If the flip-flops 2051 to 2055 in the

five flip-flops 2051 through 2055 that are in state 1 carry their normal outputs F i g. 3 g are shown, the 2010, 2020, 2030, 2040 or 2050 enables a potentiative guide the selection of characters that have either 50 voltage while their complementary outputs between the quick storage 11 and the register 2010/4, 2020.4, 2030 Λ, 2040.4, 2050.4 a negative

16 or between register 16 and the register voltage. If these flip-flops ster 18 or between register 18 and the are in state 0, the out registers are swapped 16 or finally between the register input voltages instead. As shown in FIG. 3 g can be seen

17 and register 16 are to be transferred. 55, the five normal outputs are each connected to For this purpose, these flip-flops are connected to an input of one of the five OR circuits 201, either individually or all together in 202, 203, 204 and 205, while the state 0 or in brought the state 1, depending on the complementary outputs with the inputs according to whether a character or a group of characters in one of the five groups of coincidence form the memory 11 is to be entered, or 60 lines 46EU to 46E16, 46E21 to 46E26, whether a character or a Character group from this 46 E 31 to 46 £ 36, 46 E 41 to 46 E 46, 46 E Sl until memory is to be removed. The setting 46E56 are connected, each having a Beder flip-flops is performed by a zero setting was part of the organ 46 E forms. Each of these groups impulses FCZ or through impulses that either have the task, depending on the state of the in FIG. 3 h shown coincidence circuits 65 connected flip-flop the transmission of a 20LK1 to 20LK5 are supplied, which then allow or prevent one of the five characters, pulse transmitted if the extraction of a character in the form of pulses is to be carried out either by the overhead, or by Coinciding organ 36 or by the transferring organ 37

23,

come to register 16 for input.

On the other hand, a line 19 L connected to the normal output of the trigger circuit 19 B1 ends at the inputs of the five OR circuits 201 to 205. This line 19 L carries a positive potential whenever the trigger circuit 19 B1 is in state 1, ie each time when a character or a group of characters is to be taken from memory. The outputs of the OR circuits 201 to 205 are each connected to the inputs of one of five groups of coincidence circuits 46 L 11 to 46 L16, 46 L 21 to 46 L 26, 46 L 31 to 46 L 36, 46 L 41 to 46 L 46 or 46 L 51 to 46 L 56, each of which forms part of the organ 46 L. Each of these groups has the task of allowing or preventing the transmission of one of the five characters coming from the organ 31 in the form of pulses, depending on the state of the output of the OR circuit connected to it.

If a character is removed from the memory, the line 19 L carries a positive voltage, so that all the outputs of the OR circuits 201 to 205 carry a positive potential. In this case the five characters, which are in the same memory row as the desired character, are taken from the memory ^ and transmitted via the organs 31 and 46 L. ' These five characters are stored in register 16 and then transmitted to organ 35. So that only the desired character is allowed through and the other four characters are blocked, five AND circuits 2010, 2020, 2030, 2040 and 2050 shown in FIG Flip-flops 20 Bl to 20 B 5 is connected. A line M 10 LK is connected to the other input of each of these AND circuits and is brought to a positive potential each time a character is to be taken from the memory for input into the register 18. i; -: ·

. . ■ Main register of the 'machine

Each character (letters, digits, various other characters) is stored in memory after a six digit Binary code stored. The code chosen is a mixed code generated by the connection of the 1-2-4-8 binary code with two additional digits 16 and 32 is formed. For example, the decimal digits, the capital letters of the alphabet and various other characters encrypted in the following way:

Table I.

sign Encrypted 16 depiction 4th in the Place ■ characters Encrypted 16 Representation in 4th the Place 32 8th 2 1 32 8th 2 1 Between O O O O space O O O O O O O (zero) 1 O O O O O A. O O O O O 1 1 1 O O O O 1 B. O O O O 1 O 2 1 O O O T-H O C. O O O 1 T-H 1 3 1 O O 1 1 1 D. O O O T-H O O 4th 1 O O 1 O O E. O O O T-H O 1 5 1 O O T-H O 1 F. O O O 1 1 O 6th 1 O O 1 1 O G O O O O 1 1 7th 1 O O O 1 1 H O O 1 O O O 8th 1 O 1 O O O I. O 1 1 O O 1 9 1 1 1 O O 1 P. O 1 O O O O Δ 1 1 O O O O Q O 1 O O O 1 T-H 1 O O O 1 R. O 1 O O 1 O j 1 1 O O 1 O S. O T-H O 1 1 1 K 1 1 O T-H 1 1 T O 1 O 1 O O L. 1 T-H O 1 O O U O 1 O 1 O 1 M. 1 1 O T-H O 1 V O 1 O 1 1 O N 1 1 O 1 1 O W. O 1 O 1 1 1 O 1 1 O O 1 1 X O T-H 1 O O O Z 1 1 1 . O O O Y O T-H O 1 T-H 1 O 1

With this selected code, which is not reserved for the invention and only as an example is to be seen, the code combination of the decimal digits always contains the binary digit 1 in the position 32 and the binary digit 0 in the position 16, and these two digits are followed by the one encoded in the 8-4-2-1 binary code Representation of the decimal number. For the remaining characters (letters and various Characters), the encryption uses all other combinations. The table above contains only the encryption of some characters, although the remaining combinations for encryption are in reality other characters are used, such as +, -, =,>,% etc.

For example, the + character is encrypted using the combination 111011 ^ and the = character is encrypted using the 101101 combination. The first digit of a combination corresponds to digit 32, the second digit to digit 16, the third to digit 8, etc. ' ^:

The five characters taken from memory in the course of a cycle require storage thirty flip-flops in the registers, namely six flip-flops per character, since each flip-flop

25 26

circuit only a binary digit of the code combination organ 35 consists of five groups of coincidence

can save a character. circuits 3511 to 3516, 3521 to 3526, 3531 to

The in Fig. Register 16 shown in FIG. 3f consists of 3536, 3541 to 3546, 3551 to 3556, of which only five groups of flip-flops 16B11 to two groups are shown in FIG. 3k. Any die-16 Z? 16, 16 B 21 to 16 526, 16 B 31 to 16 5 36, 5 ser groups with the output of one of the AND-16541 to 16 B 46, 165 51 to 16556. Each group circuits 2010, 2020, 2030, 2040, 2050 connected flip-flops can store a character that. If one of the five is removed from the memory and each toggle switch in a group can store a number of characters from one of the digits 1, 2, 4, 8, 16 and 32, registers 18, which are stored in register 16, only one will take up . For example, the toggle io of these AND circuits store a positive 16521 to 16526 binary digits at their output, so that only one of the five groups of digits 1, 2, 4, 8, 16 or 32 of the code combination of coincidence circuits is dated from Organ 33 of the second character. In FIG. 3f, only the two groups of toggle-switching impulses representing the impulses that represent the toggle switch are to be used and the code combinations of the characters are simply allowed to pass through. This begen 16511 to 16516 and 16551 to 16556 indicate that one of the groups of coincidence switches, which allows the pulses to pass through for the storage of the first or the line, which are used for the fifth character, but there is a register that represents a code combination of a character, dial-16 is actually made up of thirty flip-flops. To represent the four other groups, the impulses are more clearly represented and to simplify the description, which represents the code combinations of the four other bonds, the flip-flops in FIG. 3f represent 20 characters. Six coins shown in Fig. 3m shown lying down, with their inputs at the cidenzschaltungen 3601 to 3606 form the organ top of the flip-flop 36 representing these lie. The normal inputs and the normal six coincidence circuits through one of the gene outputs are on the right half of this control pulse F 15 EK in activity corner. A control coming from generator 15 is set; they then cause the transmission of the signal F12 enabling the resetting of the thirty characters contained in register 18 to the flip-flops register 16 to zero. 16, this sign in the form of pulses

The in Fig. 3 m shown register 18 is transferred, which after passing through the

from six flip-flops 1851 to 1856, which 30 organ 46 E to the flip-flops of register 16

the binary digits of the digits 1, 2, 4, 8, 16 or 32 arrive.

store the code combination of a character. Thirty coincidence circuits 3716, 3715, 3714

can. These flip-flops can be implemented by a ... 3754, 3753, 3752, 3751, of which only twelve in

Control signal F 12 LK are reset to zero, Fig. 3s are shown, form the organ 37. If

which has previously been output by the generator 15, 35 a group of five contained in the register 17

if a character taken from the memory is to be entered into the memory,

should be entered in register 18. these thirty coincidence circuits through one

The register 17 shown in FIG. 3e consists of the control pulse F15 EM coming from the generator 15 in the same way as the register 16 of thirty toggle switches; they then cause the transfer switching 17511 to 17 B16, Π B 21 to Π B 26, 4o supply of these five characters in the form of pulses from 17531 to 17 B36, 17 B 41 to 17546, 17551 to register 17 to register 16. These pulses go 17556 and can therefore store five characters. In order to simplify the coincidence which forms the organ 46, FIG. 3 e only the toggle circuits through.

lines 17511 to 17516 and 17551 to 17556 The register 23 shown in FIGS. 3q and 3r is shown, which is used to receive the first or 45 is used to receive a character taken from the memory. The flip-flops of the direct address consisting of five characters, with the register 17, can be reset to this direct address between 00000 and 39999 by a control signal F02, which is determined by the control signal shown in FIG. 3 ζ hold is. As the time shown in this register comes main control generator 30. Threes can only be decimal digits, the binary coincidence circuits 3311, 3312, 3313 ... 50 digits of digits 16 and 32 of a code combination 3354, 3355, 3356, of which only twelve in FIG 8-4-2-1 are shown, form the transmission member 33; To differentiate between the code combinations of the decisie, the task of the code combinations of the mal digits is sufficient. Therefore, the register consists of characters contained in register 16 in the form of; 23 out of 18 flip-flops. The ten thousand digit pulses are transmitted when they receive a control pulse F16 coming from the generator of the direct address is in two flip-flops ratorl5. 23 DM 2 and 23 DMl stored, the thousands - The characters transmitted in this way are digit is sent to organs 34 and 35 in four toggle circuits 23 M 8, 23 M 4. The organ 34 23 M2, 23Ml is stored, the hundreds digit is in consists of thirty coincidence circuits 3411, four flip-flops 23 C 8, 23 C 4, 23 C 2, 23Cl ge-3412, 34J3. . . 3454, 3455, 3456, of which only 60 stores, the tens digit is shown in four toggle switches. the code - the ones digit is finally stored in four toggle switch combinations of the characters representing pulses gen 23 t / 8, 23 U 4, 23 £ / 2, 23171. Im only going through if the line MlOLM compares with the toggle circuits of the register 17 leads to a positive potential, ie if a previously 65 from Fig. 3e is to be noted that the normal group of five characters, taken from the memory and then stored in the register of the flip-flops 17512, 17511, 17524 16, follows 17521, 17534 to 17531, 17544 to 17541, which is to be stored in register 17. The 17554 to 17551 each correspond to the normal inputs

27 28

of flip-flops 23 DM 2, 23 DMl, 23 M 8 is recorded to a six-digit code, while 23Ml, 23 C 8 to 23Cl, 23 D 8 to 23Dl and it is recorded in register 23 in the 8-4-2-1 code 23 U 8 to 23 C / 1 correspond. Furthermore, since each of them is, with every transfer from register 23 toggle switches of register 23 in the case of transfers to register 17, an additional binary digit must always be a pulse either at one or 5 position 32 to the 8-4-2-1- Combination of each character received at the other input, it is not necessary to be added. This addition takes place in both cases, before entering a new direct address, for example by means of additional coincidence circuits, the flip-flops of this register are set to zero - 3916, 3926, 3936, 3946 and 3956, which reset the control. Each incoming pulse F 10 received at register 23 and the transition of the Kippnew direct address is namely recorded therein under Lö- io circuits 17 B16, 172226, 17 £ 36, Π Β 46 and schung the previous address. 17 B 56 bring about state 1.
The transfer of a direct address from the register

17 to register 23 takes place with the help of a first address changing device
Group of coincidence circuits 3812, 3811,

3828 ... 3854, 3852, 3851, which send the direct paint inputs of the flip-flops of the register address, for example by increasing by 1 quickly 23 control incoming pulses, and can be changed with the help of the address change of a second group of coincidence circuits organ 26, for example from a group of Halb-3812,4, 3811.4, 3828.4 ... 3854.4, 3852.4, 3851.4, addition circuits can be formed in the in which are arranged in the manner shown at the complementary inputs of the 20 Fig. 3χ. These Flip-flops of the register 23 incoming Im- Illustration shows five half-addition circuits control pulse. These two groups of coincidences- 2650, 2640, 2630, 2620 and 2610, each with half-circuits form the transmission member 38 of addition circuit in a manner known per se Fig. 1; they receive a pulse F09, the correspondingly arranged AND circuits and the transmission of the di-OR circuits contained in register 17 is formed, which the "parallel" right address to register 23 triggers. Addition of two binary coded decimal

The in the assembled F i g. Carry out 3 ν and 3 w digits. These half addition circuits

The registers 24 and 25 shown are for recording purposes are not described in detail because they

any direct between 00000 and 39999 do not form part of the invention. Any of them

Address determined. These registers are in the same 3 ° receives via lines Ul, U 2, U 4 .. .DMl,

Structure like register 23 and DM2 contain the binary code combination of a decimal

thus eighteen flip-flops each, namely digit. These lines come from the normal ones

the register 24, the flip-flops 24 DM2, outputs of the corresponding flip-flops of the

24 DMl, 24 M 8 .. .24U4, 24U2, 24Ul and the register 23. Since it is in the half-addition

Register 25 the flip-flops 25 DM 2, 25 DMl, 35 connections is often necessary to add negation circuits

25 M 8 .. .25 U 4, 25 U 2, 25Ul, where the meaning is used, it is more practical to use the values

tations of the given reference signs obviously turn, which by the state of the complementary

are. A first group of coincidence circuits outputs of these flip-flops are shown. to

5012, 5011, 5028 ... 5054, 5052, 5051 and one for this purpose connect lines UlA, U2A,

second group of coincidence circuits 5012,4, 40 U 4 A ... DM IA, DM2 A the complementary output

5011.4, 5028.4 ... 5054 A, 5052/4, 5051.4 enable the flip-flops of register 23 with the

borrowed the transfer of the inputs of the half-addition circuits contained in register 23, as in

direct address to the register 24. This Koinzi- F i g. 3 q, 3 r and 3 χ is shown. The two lines

denzschaltungen form the transmission organ 50 Ul and UlA end at the two inputs of a

and receive an OR circuit 2601 coming from the generator 30, and there always one or the other

Control pulse FOl. In the same way, two other of these two lines form a positive voltage

tere groups of coincidence circuits 5112, 5111, leads to the OR circuit 2601 at its

5128, ... 5154, 5152, 5151 and 5112.4, 5111.4, output always has a positive voltage, which the

5128.4. . . 5154 A, 5152,4, 5151,4 represents the transferring digit 1 to be added to the direct address.

supply organ 51; they enable on the basis of one of the 50 places. The half adder circuit 2650, which this

Generator 30 coming control pulse FOl the value 1 to be added and the binary digit of the direct

Receives the transmission of the direct address contained in register 24, the operation of the addi-

Address to register 25. Finally, two form these two digits. The result is in

in Fig. 3 q and 3 r recognizable further groups of encrypted form corresponding to the 8-4-2-1 code

Coincidence circuits 5212, 5211, 5228 ... 5254, 55 on the. Lines 26 U 8, 261/4, 26 U 2 and 26 U1

5252, 5251 and 5212.4, 52UA, 5228.4. .. 5254.4 issued. When the in the half addition circuit

5252.4, 5251.4 the transmission member 52; if the digit entered 2650 has the value 9, that is

possible due to the control pulse F 01 the output result 0000, during a carry

Transfer of the direct RU contained in register 25 to half adder circuit 2640

Address to register 23. 60 becomes. This performs the operation of adding the

In Fig. 3 j are coincidence circuits 3912, 3911, carry RU (if present) and the

3924, 3923, 3922, 3921 ... 3954, 3953, 3952, 3951 over the lines Dl to D 8.4 incoming

recognizable, of which only a few are shown. Tens digit of the direct address. The get-

These circuits belong to the transmission organ tene result is on lines 26Dl to

39 and enable, on the basis of an output from generator 65 26D8A , while a possible over-

30 coming control pulse FlO the transmission carry RD to the half-addition circuit 2630 over-

a direct address contained in register 23 will carry. Half adder circuit 2630 performs

to register 17. Since each character in register 17 is included in the addition of the carry RD (if this is

den ist) and the hundreds digit of the direct address. The result is output on lines 26Cl to 26C8A, while any carryÄC is transferred to the half-adder circuit 2620. This then adds the carry RC (if it is available) to the thousands digit of the direct address. The result is output on the lines 26M1 to 26M8A, while a possible carry RM is transmitted to the half- addition circuit 2610. This finally carries out the addition of the carry RM (if this is available) to the ten-thousand digit of the direct address. The result is output on lines 26 DM1 to 26 DM 2 A. Whenever one of the half-addition circuits 2650, 2640, 2630, 2620 forms the sum 9 + 1, it delivers the result 0 and transfers a carry to the half-addition circuit, which performs the operation with the decimal digit of the next higher number of digits.

If a carry RM is transferred to the half addition circuit 2610 and this has to perform the addition 3 + 1, the result obtained is 0. So if the original direct address was 39999, the half addition circuit 2650 performs the addition 9 + 1 and returns 0 as the result while a carry RU is being transferred to the half adder circuit 2640. Due to the following additions, each of the half-addition circuits 2640, 2630, 2620 outputs the result 0, while a carry is transmitted each time to the following half-addition circuit. The half addition circuit 2610 then performs the addition 3 + 1 and supplies the result 0, so that the direct address changed by all the half addition circuits finally becomes 00000.

Of course, the arrangement described is only an example. It can be replaced by any other fast-working address changing device. In the described arrangement, the address changing element forms the direct address increased by 1 for each direct address contained in the register 23 through the state of the lines 26 Ul, 26 UlA, 26 U 2, 26 U2A ... 26 DM 2, 26 DM 2 A. This modified direct address can then be transferred to register 23 with the aid of a first group of coincidence circuits 4912, 4911, 4928 ... 4952, 4951 and a second group of coincidence circuits 4912 A, 49X1A, 4928 A ... 4952 A, 4951 A will. These two groups form the transmission element 49 and receive a control pulse FIl coming from the generator 30. The aforementioned coincidence circuits are shown in FIG. 3 q and 3 r shown. Each time a pulse FIl is sent to the organ 49, the direct address contained in the register 23 is increased by 1.

of the instruction from register 18 to the instruction decryptor, in which it is stored and decrypted. It is assumed here that the TO character transmitted to the command decoder 21 is either the + character or the - character. Depending on the decryption carried out, the instruction decoder sends either a pulse F 3OA, which controls an addition, to the addition-subtraction circuit, or a pulse F 30 5, which controls a subtraction, if the TO character transferred to it is the character -. The pulse F 30 A or the pulse F 30 S is not sent to the addition-subtraction circuit until the moment in which the decoder 21 receives a control pulse F19 from the generator 30.

The normal outputs of the flip-flops 1851 to 1854 are connected to the inputs of coincidence circuits 4001 to 4004, while the complementary outputs of these flip-flops are connected to the inputs of the coincidence circuits 4001Λ to 4004 A. These coincidence circuits form the organ 40 and effect the transmission of an encrypted decimal digit from the register 18 to the addition-subtraction circuit when they receive a control pulse F 23. The decimal digits to be added or subtracted are thus successively transmitted to the addition-subtraction circuit. After either the pulse F 30 A or the pulse F 30 5 has been received, the two decimal digits are either added or subtracted, and the encrypted result is obtained with the aid of the in FIG. 3 k recognizable coincidence circuits 4201 to 4204 and the one in FIG. 3 m recognizable coincidence circuits 4201 A to 4204 A are transferred to the register 18. Two additional coincidence circuits 4206 and 4205 ^ 4 are used to bring the flip-flop 18 5 6 into state 1 and the flip-flop 18 B 5 into state 0, so that the result coming from the addition-subtraction circuit in register 18 in a six-digit code. The coincidence circuits 4201 to 4204, 4201/1 / f to 4204 ./4, 4206 and 4205 Λ together form the ^ organ 42; they set the flip-flops of the register 18 as soon as they have received a control pulse E 24 coming from the control generator 30. A pulse F 26 coming from the generator 30, which plays the role of an inhibition signal, is used to delete the TO character located in the decoder 21, ie to reset to zero the circuits that enable this character to be stored inside the decryptor.

Identification register

Instruction decryptor and addition-subtraction circuit

The instruction decryptor 21 and the addition-subtracting circuit 22 shown in Fig. 3s will not be described in detail because they do not form part of the invention. Coincidence circuits 4101 to 4106, which belong to the element 41, enable the transmission of the TO symbol under the action of a control pulse F25. The registers 27 and 28 are shown in the assembled FIGS. 3 ρ and 3 u. Register 27 consists of flip-flops 27B 11, 27512 ... 27525, 27526, and register 28 consists of flip-flops 28511, 28512 ... 28525, 28526. The flip-flops 27511 to 27516 or 28511 to 28516 can store the first character belonging to an identifier. If, for example, the identifier is formed from the characters G 3, these flip-flops can store the character G. the

Toggle switches 27521 to 27526 or ■ 28521 /! ■ ;. up to 28526 can store the second character of the identifier. The characters of an identifier stored after the removal from the memory 11 in succession temporarily in the register 18 and I Danir successively transferred to the register 27th This erfotet with the help of coincidence circuits 4311 to 4316. 4311 A to 4316A, which receive a control pulse F 21 A coming from generator 30 or with the help of coincidence circuits 4321 to 4326, 4321Λ to 4326 A, which receive a control pulse F 215 coming from generator 30 . Since the flip-flops of these registers always receive a pulse at one or the other input during transmissions, it is not absolutely necessary to reset these flip-flops to "zero. The registers 27 and 28 can exchange their contents:" Impulse F27, which is based on coincidence switches 4511 to 4516, 4511.4 to 4516Λ, 4521 to 452V). 4521.4 to 4526 A, 4411 to 4416, 4411Λ to 4416.4. 4421 to 4426, 4421Λ to 4426.4 acts.

Locking eggs

The encryption egg 29 has the task of converting an identifier contained in the register 27 into a binary-encrypted decimal intermediate address, the intermediate address being between 0000 and 7995, for example, and ending with either 0 or 5. If, for example, the codes in register 27 are only ..; G 2 is contained, the intermediate address which corresponds to the conversion of this identifier by the encryption device 29 is 0670. The identifier contained in the register 27 : T is assigned by the encryption device 29 to the intermediate address 4915. As an example, it is assumed that the identifiers used in the invention are formed from two characters selected from the forty characters listed in Table I, which was previously given in connection with the encryption of the characters. As this table shows, the characters used to form the identifiers are all 26 letters of the alphabet, all decimal digits from 0 to 9, three special characters (A ,: and.) And the space (or lack of characters). By combining these forty characters, you have 1600 different identifiers, each identifier being made up of two of these characters. Table I also shows that when these characters are encoded, the 8-4r2-1 combinations are decimal and that, therefore, in digit 8, the number 1 is on average only two times out of ten; comes, while the digit 0 is present in the same place on average eight times out of ten times. This peculiarity can be disruptive when converting the identifier into an intermediate address, because ■ the binary digit in position 8 of the second character of the identifier is used to form the binary code combination of the thousands digit of the intermediate address. In this way it can happen that two different identifiers are converted into the same intermediate address. For Vermei ¹ this drawback dung to change before forming in the intermediate address of the second character identifier in such a manner that a transition is made from the 32-16-8-4-2-1 code into a code in which the original in the binary digit located in position 8 is present on average every second time, for example in a 32-16-5-4-2-l code. The code combinations of the characters then correspond to the following table II.

Tabel!!

sign Encrypted 16m depiction 0 in the Place sign Encrypted 16m depiction 4m in the Place 32 _m ⁵ m 0 ² m ¹ B! ³² m 5 m ² m Between 0 0 0 0 space 0 0 0 0 0 0 0 (NuIl) 1 0 0 0 0 0 A. 0 0 0 1 0 1 1 1 0 0 0 0 1 B. 0 0 0 0 1 0 2 ' 1 0 0 0 1 0 ^; C. 0 0 0 0 1 1 ■ 3 1 0 0 1 1 1 D. 0 0 0 0 0 0 ■ 4 1 0 0 0 0 0 E. 0 0 1 0 0 0 5 1 0 1 0 0 0 F. 0 0 1 1 0 1 6 ^] 1 0 1 0 0 1 G 0 0 1 0 1 0 ■ 7 1 0 1 0 τ-I 0 H 0 0 T-I 0 1 1 8th 1 0 1 1 1 1 I. 0 1 1 0 0 0 9 1 1 1 0 0 0 P.
/ ■ ν 0 1 0 0 0 0 ■ '■ Δ :. ., 1 1 0 0 0 0 O 0 1 0 1 0 1 1 1 0 0 0 1 R. 0 1 0 0 1 0 j 1 1 0 0 1 0 ■ J. 0 1 0 0 1 1 k ■■ ' 1 1 0 T-I 1 1 U
ν 0 r-l 0 0 0 0 ' ^:: L ·' 1 1 0 0 0 0 >
W. 0 1 1 0 0 0 - M ". 1 1 ■ r: ■ 0 0 0 IT 0 1 1 T-I 0 1 N ^; 1 1 1 0 0 T-I v 0 1 1 1 0 O 1 1 1 0 1 0 X 0 1 1 1 1 Z 1 1 1 1 τ-I 1 ; 0 1 0 0 , 1 1 0 0

Index m ₂ ei _{gl aDj that the Stälea relate to the 3} 2-i6-5-4-2-l code.

33 34

The logical equations for this transformation are as follows:

l _m =

= T-2 "-4-S + 1-8

16 _m = 16

32 _m = 32

This transformation is carried out by a group of control generators
AND circuits and OR circuits ^2910-1 S Fig. 3η shows a rectangle that symbolically 2924 performed in F i g. 3 d are shown. Auxiliary control generator 15 represents. This generator These circuits form the Verschlüsseier 29. The serves Menden due to a komdurch conversion delivered by the generator 30 intermediate address start pulse DC one of the identifier contained in the register 27 staggered time is thereby generate pulse sequence obtained which either the that first the binary digit in position 16 ^{z0 flip-flops or on the coincidence circuits of} the first character of the identifier and acts in so that all RAM required for the removal or the flip-flops 14 U 1 and 14 U 4 of the register input of the characters in the memory is sent, so that those in the rocker arm operations are coordinated. The generator 15 lines 14Ul, 14 U 2, 14 U 4, 14 [/ 8 stored, for example, consists of a delay line combination either the decimal digit 0 or the ³ 5 with intermediate taps, possibly with graduated decimal digit 5, which represents the units digit of the th pulse formers so that the line forms pulses in the intermediate address. Outputs the binary digits at the times which are defined as a function of the positions 1, 2, 4, 8 of the first character of the identifier to be carried out operations. To avoid a reflection of the pulses at the end 14 D 8 of the register RA M are sent into the flip-flops 14Dl, 14 D 2,14 D 4, so that it contains the 30 of the line to form the delay line at its tens digit of the intermediate address. The binary end is an echo suppression arrangement which suppresses the reflections in digit 32 of the first character of the code, for example the RAM described in the statement in the flip-flop 14 C1 of the register of German patent specification 1058 099. After reshaping the second order. The impulses supplied by the generator 15 character the identifier 35 contained in the register 27 emerge one after the other from the generator in the 32 _m -16 _m -5 _m -4 _m -2, "-l _m code are the binary- the direction of the arrow specified sequence from: F12, digits in the digits l _m -2 _m -4 _m in the toggle switch- LE-I, LE-I, F 14 ... F17, F18. The last pulse gen 14 C 2, 14 C 4 or 14 C 8 of the register RAM is sent in two different directions, so sent so that it is in the flip-flop that at the same time a pulse FCZ, the reset 14Cl stored binary digit Hundreds of 40 of the flip-flops 20 Bl to 20 B 5 form to zero er the intermediate address. possible, and a pulse FC that resets

Finally, the binary digits in the digits of the flip-flops 1951 and 19 B 2 are set to zero

5 _m , 16 _m , 32 _m in the flip-flops 14Ml, 14M4, acts, are delivered.

14 M 2 of the register RAM , so that it contains the main control generator 30, for example

Form thousands digit of the intermediate address. It refers to a pulse generator 30G, which is shown in FIG. 3z

it goes without saying that all flip-flops are shown and in the same way as the generator

Register RAM have been reset to zero, 15 is formed. A push button that does not come with a

before any binary digits are fed to them, the source of positive pulses is connected,

the. The assembled F i g. 3 c, 3d, 3h, 3i, symbolically represents a known measure for delivery

3 p, 3 u show that the 5 ° elimination of a single start pulse for the generator in register 27

The identifier held by the locking egg in a 3OG. The generator then delivers in the

Intermediate address is transformed, which with the help of the sequence indicated by the arrow is a sequence

of the coincidence circuits 47 U1, 47 U 4, 47Dl, of pulses, some of which lead to the mixed switching

47 Z) 2, 47 D 4 ... 47 Ml, 47 M 2, 47 M 4 which reach the lines 3002 to 3015, which in Fig. 3 s form transmission element 47 and one from Genera- 55 and 3y are shown and it make it possible to receive several control pulse F22 coming from gate 30, to combine them in lines to form a single one. To which the register RAM is sent. This intermediate pulse address transmitted by the mixing circuit 3002 is contained between 0000 and 7995 and on the one hand comes to a further mixing circuit always ends either with the number 0 or with the 3001 and on the other hand to a delay line number 5. FIGS. 3d and 3i still show a 60 30 /? which supplies a noticeably delayed pulse to the group of Kolnzklcnzschaltungen 48 171, 48172, circuit 3001. This measure enables

48 U 4 ... 48 M 8, 48 DM1, 48 DM 2, which form the transfer element 48 via the doubling of each via the circuit 3002. When this coincidence-transmitted pulse, whereby two time counter-circuits receive a control pulse F 01-2 and F 01-3 coming from the generator 30 offset pulses F 01-2 and F 01-3, they cause the transmission, which is transmitted via the circuit 3001 in register 23 contained direct the. The addresses from the circuits 3003 and 3001 to the register RAM, whereby these direct pulses are recorded with FOl-I and FOl beaddress between 00000 and 39999 is included.

35 36

, "",. the resetting of the register 18 acts to zero.

How the machine works _{: the rest of the time, after arriving at the Ko} .

incidence circuits 20EM, 20LX and 20 EX only

The method of operation described is now to be transferred from the circuit 20LX. Because in the machine, by explaining the example chosen in the course of every 5, the unit's digit of the work steps occurring in the Operation register is RAM contained direct address 6, the will be. The operation of the machine is positively best output of the AND circuit 2006 so that with reference to FIGS. 3a-3z understood transmitted over the Schaltung20LX pulse to but optionally, the FIG. 1 can herangezo- lengths the coincidence circuits 20LXl to 20 LKS in which the path of the information comes io, but is only informed by the circuit 20 LK2 over the course of the various work steps, so that it can be followed by the flip-flop circuit 20 B 2 over and over. brings the state 1, while the rest of the toggle before each removal of a command from the memory. circuits20 Bl, 20B3, 20B4 and 20B5 in the Zucher are the flip-flops 19 Bl and stand zero. The output line 19B2 and the registers 17 and RAM therefore initially carry a positive voltage 15 2020. Since the flip-flop circuit is in the state zero and the command decoder 21 1951 is in the state 1, the line 19 L carries a contains no character. The direct address of the last positive voltage, so that the outputs of the OR sign of the last command used, circuits 201 to 205 have a positive voltage in register 24. So that the direct address of the lead and the coincidence circuits of the organ first character of the following command is received is, »o 46 L all coming from the transmission organ 31, this direct address must be able to transfer pulses into the register 23. The generator 15 is brought and counted further. After the In- then the pulses LE-I and LE-2, which set the gear through the push button P, the Genera- the corresponding switch of the half-selector 12-1, gate 30 G emits a pulse FOl ^, which after the over- 12 -2, 13-1 and 13-2 close. Then a recording is selected by the circuit 3002 in two pulses 25 series, and the five F 01-2 and F 01-3 contained therein is doubled. The in the form of characters are taken from it and arrive at a pulse FOl via the circuit 3001 via the organ 31; Register 23 selects these five characters for transmission element 46 L. The correspondingly delayed pulse F 01-3 is passed on. These code combinations arrive from the circuit 3001 in the form of a further im- this organ is transmitted in the form of pulses in the manner of pulses FOl, which, after completion of the, that the presence of a pulse, the binary preceding transmission, the transmission of the digit 1 of a combination and the If there is no Imdirect address from register 25 to register 23, pulses represent the binary digit 0. As the Koinzi triggers. The delay of the delay line 35 because circuits of the organ 46 L are able to 3Oi? is determined from the outset so that these then carry all the impulses fed to them to the second transmission only at the moment, those coming from the organ 31 and can, in which the first transmission can be regarded as the end of the impulses representing the five characters. The generator 3OG transmits organ 46 L, they turn off the toggle switch and then a pulse F11-1, which sets the counting 40 of the register 16 in such a way that the state of the direct address contained in the register 23 represents the code combinations of these characters. That solves. The new direct address is then the address five characters are thus stored in register 16, the first character of the following command, ie the one during the ring cores of the memory row in which they address a T.O character. As an example, it is assumed, returned to state 0, that this direct address is 12386. 45 are. The generator 15 then emits a pulse F16 The generator 30 G then emits a pulse OLl which, after arriving at the transmission member 33, represents the read command which is in the toggle output of the five characters contained in the register 16 circuit 19 Bl des Instruction memory 19 is stored in the form of pulses to the transmission organs. The output of the AND circuit 19LX leads 34 and 35 triggers. Since the output of the andthen a positive voltage. A line M10 LM no 3OG emitted pulse F 20-1 coming from the generator 50 circuit 19LM triggers the transmission if positive voltage is carried out, the organ 34 blocks all of the direct address from the register 23 to the register borrowed pulses. Since the line coming from the output RAM of the registration and decryption organ 14 is the output of the AND circuit 19LX. After decryption, this direct MlOLX leads to a positive voltage and the setting of the switches of the half-selector 55 output of the flip-flop 20 B 2 coming from the address Lei-12-1, 12-2, 13, -1, 13-2; This involves device 2020 also carries a positive voltage, the switches, whose reference numerals with the book, the output of the AND circuit 2062 starts with a positive letter / starts, such as IAX1, IAX 2 , etc. The positive voltage from while the outputs of the undrator 30 G then emits a start pulse DC-I, which is not transmitted positively to the generator 15 in circuits 2061 and 2063 to 2065. From this 60 tive tensions result. Thus only the impulses allow the generator 15 successively the coincidence circuits 3521 to 3526 the through impulses F12, LE-I, F14 ... F18, FC and FCZ . The impulse F12 is sent in three different directions, so the character whose direct address is sent, so that it is register 16 12386 on the one hand, can be reset to zero in the form of these impulses in the register and on the other hand transferred to the 65 18. The remaining signals coming in the form of pulses, coincidence circuits 20EM, 20LX, 20EX and from organ 33, are passed through 1901. After transmission by the coincidence circuits 3511 to 3516, 3531, the circuit 1901 is referred to as F12 LX and is 3532 ... 3555, 3556 blocked. Then the

Generator 15 from the pulses EC-I and EG-2 , which close the corresponding switches of the half-selectors 12 ^ 1, 12-2, 13-1, 13-2. During the time in which these switches remain closed, the generator gives

15 from a pulse F 17 which, after arriving at the transmission element 32, enables the five characters previously removed from the memory to be re-entered into the memory, namely into the memory row in which they were contained before they were removed. '

It should be noted that the. State of the multivibrators of the register 16 is not changed in the course of the ■ re-entry of the five characters into the memory has been so that the register 16 still contains the code combinations of these characters. This remark also applies to the status of the flip-flops in the other registers. The registry

16 is therefore later reset to zero by another pulse F12. A pulse F 18 emitted by the generator 15 resets the trigger circuits of the register RAM to zero. Then the flip-flops 20 B1 to 20 S 5, 19 51 and 19 B 2 are reset to zero by the pulses FC and FCZ emitted by the generator 15. At the end of these operations, the character contained in register 18 is the TO character of the command. This character is, for example, the sign H-, and it is assumed that the command to be taken from the memory consists, for example, of the character + NG 9 H. The command therefore contains a + character and two identifiers made up of the NG and 9 H characters. A control pulse F 25 emitted by the generator 30 G acts on the transmission element 41 and thereby triggers the transmission of the TO character from the register 18 to the command decoder 21, in which it is stored and then decrypted. The generator 3OG then sends a pulse F 11-2 to the organ 49, which causes the direct address contained in the register 23 to continue to be counted. This direct address is therefore 12387. The generator 3OG then emits a pulse OL-2 , which brings the flip-flop 19 B1 to state 1. After the direct address 12387 has been sent to the RAM register on the basis of a pulse F 20-2 supplied by the generator 30 G, it causes the switches of the half-selectors 12-1, 12-2, 13-1, to be set again after being decrypted. 13-2. Then a pulse DC-2 is sent from generator 3OG to generator 15. Following the same procedure as before, which is based on FIG. 3 a to

3 ζ can be easily traced, five characters are taken from memory and stored in register 16. Among these five characters is the second character of the command to be taken, ie the character N. On the basis of a pulse F16 supplied by the generator 15, these five characters reach the organs 34 and 35. Only the character N is used by the coincidence circuits 3531 to 3536 transmitted while all remaining characters are blocked. The character N thus arrives at register 18, in which it is stored. This character is the first character of the identifier _{NG of} the command. The generator 15 then emits the pulses EC-I, EC-2, F 17, F 18, FC and FCZ , which the re-entry of the characters contained in the register 16 into the memory and the resetting of the register RAM and the flip-flops 19 £ 1 , 1952 and 20J51 to 2055 allow to zero, and then a pulse F 21 A-I is emitted by the generator 30 G so that the character N in the register 18 is transmitted to the flip-flops 21B11 to 27516. Another pulse F 11-3 triggers the counting of the direct address in register 23, which then becomes 12388. Three pulses OL-3, F 20-3 and DC-3 emitted one after the other by the generator 3OG cause a sequence of operations which are similar to the operations just described, and in the course of which the second character G of the identifier NG of the command is taken from the memory and is then stored in register 18. A pulse F 21B-I emitted by the generator 30 G enables this character G to be transmitted from the register 18 to the flip-flops 27521 to 27526. At this point, the register 27 then contains the identifier NG. Of the. Generator 3OG then emits a pulse F11-4, which causes the direct address in register 23 to be counted on, which then becomes 12389. Then allows a pulse F 03-1, the transmission of the identifier from the NG, register 27 to register 28. It is then possible to bring the identifier 27 H 9 the command into the register *. This process takes place on the basis of the pulses F 20-4, OL-4, DC-4 and F 21 A -2, which cause the character 9 to be removed from the memory by the same method as before and finally in the flip-flops 27511 bis 27516 is stored, also on the basis of a pulse F11-5, which continues to count the direct address so that it becomes 12390, and finally on the basis of the pulses OLS, F 20-5, DC-5 and F 215-2, which cause that the character H is removed from the memory and finally stored in the flip-flops 27521-27526. Then all characters of the command have been taken from the memory; the command decoder contains the + sign, register 28 contains the identifier NG, and register 27 contains the identifier 9 H. The direct address 12390 contained in register 23 is the address of the last character of this instruction, and a pulse FOl-C causes that this direct address, which is not used now, is transferred to register i 24. The generator 30G then outputs a pulse OL-6 which represents the read command which is stored in the flip-flop 1951, and then a pulse OM-I which represents the word command which is stored in the flip-flop 1952. The output of AND circuit 19LM carries a positive voltage, and therefore line M10 LM also carries a positive voltage. The generator 30 G then sends a pulse F 22-1 to the transmission element 47. The identifier 9 H contained in the register 27 is converted by the locking egg 29 into an intermediate address which, according to the wiring made between the register 27 and the element 47, has the value 1790 Has. Under the action of a pulse F 22-1, this intermediate address is stored in the RAM register. After its decryption, it then effects the setting of those switches of the half-selectors 12-1, 12-2, 13-1, 13-2 whose reference symbols begin with the letter /. The generator 30 G sends a start pulse DC-6 to the generator 15. From this pulse on, the generator 15 successively emits the pulses F12, LE-I, LE-2. . . F18, FC and FCZ . Following the same procedure as before

39 40

five characters are taken from the memory, the pulse F11-6 emitted by the generator 30 G causes it to be stored in the register 16 and then the further counting of the direct address in the register 33 is sent to the organs 34 and 35 via the organ. Since the Lei 23, which will then be 19023. A series of impulses device MOLX does not have a positive voltage, OL-8, F 20-6 and DC-8, which appear one after the other to produce no positive voltage at the outputs of this generator, then causes the AND circuits 2061 to 2065, and therefore block a character which in the selected example denotes the circuits 3511, 3512, 3513. . . 3554, the first operand, from the memory ent-3555, 3556 all the pulses supplied to them. It is taken there and stored in register 18. If the line M10 LM carries a positive voltage, in the present case this operand is the ones digit, the circuits 3451, 3452. . . 3415, 3416 io of the first number. A five lower pulse F 23-1 supplied to them in the form of pulses by the generator 30 G causes the transmission of this character to pass through. Therefore, these five operands are stored in register 17 from register 18 for addition subtracts. It has already been tion circuit 22. Subsequently, the generator mentions that the five characters which on the basis of 3OG emit a pulse F 01-5, which are selected after doubling an identifier, a direct address 15 development by the circuits 3001, 3002 and 30i? and it is assumed in the present case two successive exchanges of the names that the direct hold of registers 23, 24, 25 taken from the memory triggers so that the closing address, which is contained in register 17, 18941 loaned the register 23 the direct address 18941 is derived. A pulse emitted by the generator 30 G holds, the register 24 holds the direct address 12390 ent-F09-1 enables the transfer of this direct 20 holds and the register 25 holds the direct address 19023 address in the register 23. Then a dated contains. A pulse F 02-1 emitted by the generator 30 G, the same generator emitted pulse F 02-1, the pulse F11-7 causes the counting in the Re- * register 17 back to zero. Finally, the register 23 gives the address contained, which then becomes 18942. Generator emits a pulse FOl-D, which then causes a sequence of successive transmission of the direct address 18941 from the 25 pulses OL-9, Register23 to Register24 emitted by this generator and the direct address F20-7 and DC-9, which contains a character, which triggers the 12390 from register 24 to register 25. In the example chosen, the second operand represents, the reason for an Im- coming from the generator 30 G is taken from the memory and the registers 27 and 28 are stored in the register 18, pulses F 03-2 swap.

its content, so that the register 27 receives the identifier 30. In the present case, this second operand is the NG , while the register 28 contains the identifier one-digit of the second number. A pulse F 23-2 9 H stores. The identification contained in the register 27 then enables the transmission of this operand NG is converted by the encryption device 29 into an intermediate from the register 18 to the addition-subtraction address, which is based on the circuit 22. As soon as the addition-subtraction between the register 27 and the Organ 47 in front of 35 circuit in possession of the two wirings to be processed has the value 1565. Is two operands, a given pulse F19 successively emitted by the generator 30 G from the generator 30 G is sent to the command decoder pulses OL-7 and 0M-2, which send the read command and which represent the word command according to the decryption of the in the Kippschal- character + a pulse F 30 A can go through, lines 1951 and 1952 stored. Below the 4 ° This pulse has the addition-subtraction effect of an Im circuit coming from the generator 30 G and triggers an operation through which the intermediate address 1565 is added to the address 1565 in the Re- the two operands. Then ^ gister RAM is saved. On the basis of a signal from the Ge, the result is transmitted to the register 18 by means of a start pulse DC-7 supplied by the generator abnerator 3OG -I, LE-2. . . F18, FC and FCZ , which after the addition-subtraction circuit records the removal of the carry, if necessary using the method already described. After the generator of five characters from the memory and its storage 3OG has emitted a pulse FO1-B, a backup is effected in register 17. These five characters, interchanging the contents of registers 23, 24, form a direct address, for example 19022 50 25, so that the direct address is 19023 in the register. The generator 3OG then gives a pulse 23 is introduced. It should be remembered that this F 09-2 from the transfer of this direct address 19023 is the address of the first operand. Address in the register 23 causes, and then the result of the operation, which in the register 18 a pulse F 02-2, which the register 17 is at zero, is now put back into the memory at the place. At this point in time there is the following 55 brings, which the first operand occupied. To the situation: The register 23 contains the direct address. The purpose of the generator 3OG is a pulse 19022, the register 24 contains the direct address F 20-8, which causes the direct address 18941, and the register 25 contains the direct 19023 is brought into the register RAM and address 12390. If the data to be added then a start pulse DC-10. Since neither the multiple digits, each preceded by a special read command nor the word command character "end of data", which are in the memory, the flip-flops 1951 and is recorded and the boundary between two 1952 in the state zero, and therefore If the out character groups lead, for example, two digit groups passage of the AND circuit 19BK as well as the lines or numbers, the direct address MlOBX is a positive voltage. As soon as sen 19022 and 18941 are selected in such a way that they receive the address 6 ₅ generator 15 the pulse DC-10, he outputs these special characters so that they 1 emit a pulse F12 which must be added by circuit 1901 so that the direct address of the is blocked, but is preserved on the one hand by the circuit to be processed characters. One is transferred from the 20EK and the other is the register

41 42

16 resets to zero. Since the direct address contained in the register RAM five characters practically not deleted in the register 16 has the one digit 3, have been; However, since the lines M 10 LM are the output of the OR circuit 2038 and MOLX is not at a positive potential at a positive voltage, and accordingly, the organs 34 and 35 block all of them, the output of the negation circuit 2038.4 5 leads supplied pulses. This will eventually result in no positive tension. The effect of the pulse F 16 from the circuit 20 EK is canceled, and the incoming pulse is from the circuits five characters remain in the register 16. The generator 20EKl, 20EX2, 20 EK 3, 20 EX 5 transmits and 15 then gives the pulses EC-I and EC-2, which thus brings the four flip-flops 2051, 2052, in the half-selectors 12-1, 12-2, 13-1, 13-2 the corresponding 2053 and 2055 into state 1. Since the line io speaking Adjust switch. Then 19 L releases no positive voltage, the output of this generator output pulse F 17 gears of the OR circuits 201, 202, 203, 205 on the transmission of the five characters from register 16 are brought to a positive potential, so that all Koinzi- to memory off. The generator 15 then outputs a current circuit of the organ 46 L with the exception of the pulse F 18, which resets the register RAM to zero circuits 46L41 to 46L46 from the organ 31 15, and then can pass on the pulses FC and incoming pulses. The organ FCZ, which the flip-flops 1951, 1952 so-46 L, can then reset four of the five from the memory such as 2051 to 2055 to zero. Transfer of the accepted characters. Since the output of the addition process can be repeated, whereby it 2040.4 of the flip-flop 2054 is on a positive then with the two digits of the immediate potential, only the coincidence switch 20 overriding value, ie with the tens 46 E 41 to 46 E 46 which is carried out by the body of 36 grain digits of the two numbers. The incoming pulses are transmitted, while the rest of the extraction and processing of these digits as well as circuits of the organ 46 E all pull them - the re-storage of the result is carried out in blocked pulses. The organ 46 E can then, in the manner already indicated, only transmit a single character due to the re-transmission. The generator 25 fetch the pulses, for example through education

15 causes the closing of the corresponding switches in generator 3OG can be triggered by emitting the pulses LE-I and a corresponding loop from the elements of the LE-2. The Beden half-voters 12-1, 12-2, 13-1, 13-2. Then the end of the operation can, for example, select the memory row which is reached with the character that contains a special character "data of address 19023, and the five in this 3 ° end" are determined, the characters contained in the memory in the memory row go is recorded on the basis of each piece of information, or by a pulse F 14 supplied by the generator 15 by any other appropriate means. The gene to organ 46 L. All these characters are then sent by the rator30G from a pulse F 26, which organ 46 L transmits, with the exception of the character that is used to store the TO character in the memory at address 19023. This 35 instruction decryptor resets to zero, so that character is thus deleted in the memory, while these organs later retrieve the TO character of the following instruction, the four remaining characters stored in register 16 after its removal from memory. A pulse emitted by the generator 15 can take.

F i g is transferred by the coincidence circuit 1903. 3 ζ is the generator 30 G with additional wear because the output of the OR circuit 19EX 40 intermediate taps are shown, which carries a positive voltage when connected. This impulse, which is designated with the appropriate lines for the delivery of impulses FlSEK , arrives at the organ 36, which is used for the execution of various operations and triggers the transmission of the information contained in the register 18, for example for the transferred character to the organ 46 E the end. It should be remembered that data is carried between two edge units. It should be remembered that this character is the result of the addition made by recording data or instructions in memory. This character is only used by the circuits 46 E 41 to 46 E 44 for the transmission of results to a printer and or for other analog operations. Example is then stored in register 16 at the point that a pulse ElO to trigger the over-softener would have to contain the character that had been blocked by transferring a variable from register 23 to the register, circuits 46 L 41 to 46 L 44 used 50 17 will.

is. The generator 15 then emits a pulse F 16 for monitoring purposes, which transmits the five characters of the register 16 to the organs, such as key generators or key organs 34 and 35. In this operation control organs of the registers described above, the state of the flip-flops of the register is added, but these organs are for the purpose of association.

16 has not changed, and one can say that the 55 fold is not shown in the drawing.

In addition 9 sheets of drawings

Claims (5)

Patent claims: 1. Arrangement for the storage and processing of data in a data processing machine, with a memory with direct access which contains several rows, each row of which contains the same number of storage locations for the recording of data with one character per storage location, and with dialing devices for the memory locations, the memory containing program instructions which are selected under the control of addresses coming from a first address register (program address register) and successively transmitted to the selection devices via a second address register and a selection register, and each of which has a character identifying an operation to be carried out and contains at least one indirect address, and wherein the memory further contains direct addresses, which can be selected by the selection devices on the basis of the indirect addresses and then taken from the memory, so that they can then be used for the selection of the also in the memory to be processed, characterized in that each direct address stored in the memory (11) takes up all memory locations of the same memory row, that each of the indirect addresses (identifier) contains a fixed number of characters which are at most half as large as the number of A sign of a direct address is that an intermediate register (16) is connected to the output of the memory (11) on the one hand and to the second address register (23) on the other hand, the capacity of which is equal to the maximum number of characters that can be contained in a complete memory row that a first identifier register (27) is provided, the capacity of which is equal to the number of characters forming an identifier and which is connected on the one hand to the intermediate register (16) so that it receives an identifier forming part of an instruction taken from the memory, and on the other hand it is connected to the selection register (RAM part of 14) so that this identifier can be used the selection register and from this to the selection devices (12, 13) of the memory for selecting a direct address, and that the direct address is then taken from the memory, successively to the second address register (23), to the selection register (RAM) and is then transmitted to the selection devices (12, 13) of the memory for selection of a variable to be processed. 2. Arrangement according to claim 1, characterized by a control generator (30), the electrical Pulses to control the successive execution of the various operations for processing the data generated, and dv.rch an address changing device (26), the is connected to the second address register (23) in order to store the information in the second address register (23) record the standing address in order to enlarge a unit and the address changed in this way under the control by the control generator (30) back to the second address register (23) transfer. 3. Arrangement according to claim 2, characterized in that each of the characters forming an identifier, which is located in the intermediate register (16) as a result of a removal from the memory (11), before being passed on to the identifier register (27) in a connection register ( 18) is transmitted from the capacity of a character that the connection register is connected to the output of the intermediate register (16) via a first group of logic circuits (35) which are under the control of a selection indicator (20), which in turn is connected to the output of the selection register (RAM) is connected, and that the selection indicator (20) is designed so that it selectively controls the logic circuits (35) so that only the transfer of the character from the intermediate register (16) to the connection register (18) is permitted is that it was originally recorded in the memory (11) at the memory location which corresponds to the address contained in the selection register (RAM). 4. An arrangement according to claim 3, characterized Ge- _(- indicates that a second tag register "· (28 is provided) which is connected to the output of the first tag register (27) via a second group of logic circuits (44), in that the second identification register (27) in turn is connected to the output of the second identification register (28) via a third group of logic circuits (45), and that the second and third groups of logic circuits are controlled by the control generator (30) in such a way that that, in response to a received pulse, they cause the content of one identifier register (27, 28) to be transmitted to the other identifier register (28 or 27) at the same time, so that two identifiers are part of the same command taken from memory (11), can be temporarily recorded in the two identification registers (27, 28) before they are successively transferred via the selection register (RAM) to the selection devices (12, 13) of the memory will wear. ' 5. Arrangement according to claim 4, characterized in that a third address register (25) is provided, which is connected to the output of the first address register (24) via a fourth Group of logic circuits (51) is connected and its output to the second Address register (23) is connected via a fifth group of logic circuits (52), that the first address register. (24) to the output of the second address register (23) via a sixth group of logic circuits (50) is connected and that the fourth, the fifth and the sixth group of logic circuits is so controlled by the command generator (30) be that on a received pulse, the simultaneous transmission of the Trigger content of each of the address registers to the address register that is at its output connected (24 to 25; 25 to 23; 23 to 24) so that the two direct addresses that one after the other on the basis of the identifiers contained in the two identifier registers (27, 28) taken from the memory (11) and via the intermediate register (16) to the second address ΙΜΐΒ'ίΓιίιΜΜΓ · '""·''" ¹ -" τι mfriaUfT "'-""" - · - "- ■ * ■ - " · < - ■ - 3 4 registers (23) have been transferred, temporary stores, registers, counters, recording devices in two of the three address registers (e.g. 23 genes, etc.). One of the central unit can be added and 25) stored, while the added general high-speed recording device the remaining address register (e.g. 24) then contains an address, also called "high-speed memory", with a large one, which is intended for the 5 operating speed serves as a buffer later selection of the characters of the following command to enable data recorded in the arrangement for all memories (11) exchanged in the machine. In the case of machines with a stored profile, this memory also contains the program 6. Arrangement according to one of the preceding commands. Any two edge units can exchange data Removal of the data character enables each identifier to contain two characters in or out of the high-speed memory, or characters that are delayed at least as little as possible by a code. It is shown in combination with six binary digits, 15 is therefore essential that on the one hand the fast and that the transmission of an identifier contained in the first memory has sufficient data capacity for the identifier register (27) to store the data and that the selection register (RAM ) on the other hand, the seier (29) stored in this memory takes place via an encryption, which converts this identifier into commands and data in the shortest possible time from the intermediate address that can be converted from binary codes. The high-speed memories can be formed by dated decimal digits and either, for example, be magnetic core memories in which the binary-coded decimal digit "0" or the storage locations for the acceptance of characters in the binary-coded decimal digit "5" ends. serve a predetermined binary code so that each at a defined location in the memory 25 drawn characters occupies a certain number of binary digits for its representation and the so stored characters in the memory in a The invention relates to an arrangement for memory three-dimensional structure in the form of rows, runa and processing of data in a data columns and rows are distributed, each row, processing machine, with a memory with 30 columns or rows a predetermined number of binary direct Access that includes multiple rows of sites. The location of each character in which each row has the same number of memory memories is defined by a size that is called address cells for recording data with one, each memory location containing one character per memory location and with selection associated with it Address is defined. In the case of a first device for the memory locations, where the memory type of memory contains, each row only contains at most program commands which, under the control, contain a character, so that a selection made according to an address determined from a first address register Prosram address register) selects incoming and subsequent characters that are located at the other through this address via a second address register and a position defined. In the case of a second category of selection registers, 40 of memories transferred to the dialing devices all memory rows contain addresses to be selected, and each of which has the same number of memory locations, each memory location identifying an operation to be carried out being able to contain only one character, and characters and at least one indirect address ent- it is sometimes desirable to have a system, and the memory furthermore has direct addresses with which a selection made by the selection means on the basis of 45 addresses, not only that of the indirect addresses, is selected according to a predetermined one and then results from the character that can be taken in a row at the location defined by this memory, but also all subsequently enable the selection of the variables to be processed which are also contained in the memory and are in the same row . Accordingly, all the data-processing machines in this row, in particular 50 characters, can be taken from the memory at the same time, the electronic computing devices contain numerous. If only the functionally independent units identified by the address, such as punched card characters, are to be selected, locking or punched tape scanners, magnetic tape devices and organs are used, which allow the desired character to pass through magnetic disk devices that are not synchronized with one another and all other characters are blocked and with different speeds. The sequence of operations that can work on records. These units, which are ^now demand g or removal of a character in the standing or referred to as peripheral units are from the fast memory and for simultaneous, operate according to the instructions of a gespei- recording or withdrawal of several need in the program and cherten data 60 are required to be transmitted continuously with the same series of characters arranged in the memory of the central organism, form a cycle,
perform, which is also called information on machines with a stored program and, depending on the work commands, qualitative, the work commands in the quick memory are entDaten or represent sizes to be processed. keep. Every instruction of the program consists in the all-according In a well-known technique, these machinations are made up of several characters, among which are nen therefore built around a central unit, which are 65 one or in general two characters, for the coordination of the data transfers which define the type of operation that the is responsible and for this purpose is to be triggered via a command (addition, subtraction, excess knowledge Number of organs of various kinds (aid, settlement, etc.). The rest of the command