DE1441099C - Phase sensitive rectifier circuit - Google Patents

Description

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The invention relates to a phase-sensitive rectifier circuit using transformers and transistors for converting an AC voltage signal into a direct current, the a load resistance flows through and its direction through the phase * of the AC voltage signal im Comparison to the phase of a reference voltage is determined and its size proportional to the amplitude of the AC voltage signal, in particular door control or regulation.

It is known that transistors have symmetrical properties; H. Emitter and collector can basically swap their functions. A number of circuits have also become known, in which the symmetrical properties of the transistors are used to advantage will. Phase-dependent rectifier circuits have also become known in which a Direct current flowing through the load resistance according to size and direction due to size and phase position a control voltage can be changed. Such phase-dependent rectifier circuits are used, for example, in control and regulation circuits.

F i g. 1 shows such a phase-dependent rectifier circuit. The secondary windings 3, 4 and 4, 5 of the transformer U ₁ together with the rectifier transistors T ₁ , T _{2 form} the elements of a bridge circuit. The transistors are each of the same conductivity type, i.e. either npn or pnp transistors. The transistors are operated both normally and inversely; this is indicated in the circuit symbol by the fact that both the collector and emitter electrodes are drawn as arrowheads. However, the function of the circuit does not depend on the fact that symmetrical transistors are used. Any desired transistors can also be used in which α normal is not equal to u inverse, where α means the current gain of the transistor in the base circuit. The transistors are controlled via the secondary windings 11, 1Γ of the transformer P ₂ . If there is no signal voltage U _{1 / s} , both transistors are controlled in one half-cycle when the reference voltage U _{112 is} positive. The electrode at point 10 of transistor T ₁ and the electrode at point 10 'of transistor T ₂ become the collector electrode; the base electrodes of the transistors T ₁ and T ₂ are each given a negative control potential via the resistors R ₁ and R _{2, respectively.} The collector currents of the transistors T ₁ and T ₂ can be made the same with the help of the resistors R ₁ and R _2. In the following half-cycle of the reference voltage (without signal voltage) with a negative reference voltage U _1/2 , both transistors T ₁ and T _{2 are} blocked. The electrode of transistor T ₁ located at point 10 and the electrode of transistor T ₂ located at point 10 'become emitter electrodes; since the base electrodes are connected to the emitter electrodes via windings 11 and 11 ', both transistors are blocked. The load R _L , which can be represented by coils of relays, magnetic amplifiers, electromagnetic clutches, armature or excitation windings of DC motors, etc., is in the neutral branch of the bridge between the center tap 4 of the secondary ⁶ S winding of the transformer Cf ₁ and the connection point 10 of the two transistors T ₁ and T ₁ . Since the bridge is balanced during both half cycles of the reference voltage l / j _{/ 2} (during a] half-wave are blocked, while I of the other half-wave lead both transistors'. Same collector current of both transistors), flows in the absence of the signal! '. voltage no load current. j

The disadvantage of this circuit is that the voltage across the load resistor | the necessary blocking of one transistor! counteracts. This can be seen as follows: '' If the reference voltages t / _3/4 , l / _{4/5 are} positive and <the control voltage U _{101n is} negative, the control j | voltage CZ ₁₀ '/] i' positive, the _{bridge circuit controlled by Tran-: j SiStOrT 1 is} live; on; l resistance R _L drops a voltage, where point 10 ;! is positive against point 4. Transistor T ₂ is operated in such a way that the electrode connected in point 10 is the emitter and the electrode connected in point 10 'is the collector of transistor T ₂ . The bias voltage ^ of the emitter due to the voltage drop across the load resistor R _L actually counteracts the blocking j of the transistor T ₂ . In order to block the transistor T ₂ , there is a blocking voltage

necessary. This requirement is not always met. To prove it, one transforms the inequality. With negligible leakage inductance of the transformer U ₁ is

U ₁ ,

= U ₁

10/11

the voltage U _101n in turn can be expressed by the base current / _{B of} the transistor T ₁ , / _ß = - ^ and by the resistance of the control circuit (R _E + R ₁ ) :

β is the current gain in emitter circuit s and R _{E is} the input resistance of transistor T ₁ .

is by the equation I _L =

given.

If you insert this equation into the inequality, you get:

(R ₁ + R _K )

R ι ρ

For all load resistances that are greater - are

so transistor T _{2 is} not blocked.

Another disadvantage of this circuit is that if there is no control voltage during a half cycle of the comparison voltage U _112, both transistors! Conduct electricity. In addition to unnecessary heating of the transistors, there is also an undesired premagnetization of the iron core of U ₁ . In order not to overload the transistors, base resistors R ₁ , R _{2 are} provided. On the other hand, if the transistors are controlled, control power is unnecessarily destroyed in these resistors:

The object of the invention is to provide a circuit in which the disadvantages mentioned are avoided i will. I.

The phase-sensitive rectifier circuit is designed according to the invention so that the two ic Ends of a center-tapped secondary winding! of a reference voltage transformer, the js the reference voltage is supplied, with a tertiary-j winding each of this transformer via the collector-v

j-emitter path of each rectifier transistor ver-Ij are bound that the load resistance between the μ center tap of the secondary winding and the Through connection of the free connections of the tertiary windings lies that the base of each rectifier transistor with the collector each of a transistor complementary to the rectifier transistors is connected that also the emitters of these transistors with each other and with the center tap ler secondary winding of a signal transmitter to which the AC voltage signal is fed on the primary side is connected, with the base of each complementary transistor each at one end of the ! Secondary winding of the signal transmitter is performed and the center tap of this winding either with the through connection of the tertiary windings of the reference voltage transformer or with a center tap of the load resistor is connected.

In the circuit according to the invention, the disadvantages mentioned are avoided in that the The rectifier transistors are controlled via transistors complementary to them. Load circuit and control circuit of the respective blocked rectifier transistor are switched off by the collector blocking resistor of the transistor upstream of it decoupled; the voltage drop across the load resistor can therefore do not influence the blocked rectifier transistor.

The invention is illustrated by means of the FIGS. 2 and 3 illustrated embodiments explained in more detail.

In the following, the circuit according to FIG. 2 considered in the two possible phase positions of reference voltage U _{l / 2} and S control voltage (AC voltage signal) l / _19/20 and when there is no control voltage (^ 19/20 = 0).

1. If Ui ₁₂ and U _{19120 are} positive, points 3, 5, 7, 9, 15, 17 are positive, and the electrodes 5 of transistor 7J and 9 of transistor T ₂ are operated as emitters; the transistors T ₃ , T ₄ accordingly receive a collector voltage of the correct polarity via the emitter-base path of the transistors 7i, T _2. Transistor T _{3 is controlled} by the voltage t / 15/16. Its collector current / _C3 is equal to the base current I _Bl of transistor T ₁ . Transistor Ti is operated in collector circuit; he has a current gain

P- =

= ßi -Hl. The current gain of the emitter

'egg

2. If l / j / 2 is positive and t / _{19/20 is} negative, electrodes 5 and 9 are the emitters of transistors T ₁ , T ₂ . The transistors T ₃ , T ₄ receive a collector voltage of the correct polarity via the jsmitter diodes of the transistors T ₁ , T _2; However, since the control voltages Ui ₅₁ I ₆ and Un _{/ l8 are} negative, transistor T _{3 is} blocked and transistor T _{4 is switched off} . In this phase transistor T ₂ is operated like transistor T ₄ in emitter circuit, so that the current gain of the two directly coupled and cascaded transistors T ₂ , T _{4 has} the value

■■■■ -. ■ · ■ - ■ · ■■ · ■■ /,

'C2

has. Through the load resistor R _L , a current flows from point 6 to point 16. In the following half-wave, with the phase position between U ₁ 2 and U ₁₉₁₂₀ remaining the same, transistors T ₄ , T _{2 are} blocked and transistors TJ, T _{1 are} controlled so that the current flows through R _L from point 6 to point 16.

_{3. If} the control voltage U 19120 = 0 and there is only one reference voltage U _h2 with an alternating positive and negative sign at terminals 1/2, the base and emitter of transistor T _{3 are} via winding 15/16 and the base and emitter of transistor T ₄ . connected to one another via the winding 17/18. The transistors T ₃ , T ₄ are therefore blocked in each case; the base circuits of the transistors T ₁ , T ₂ are separated so that these two transistors are also blocked in the absence of a control voltage ^ i9 / 2o = 0.

In this embodiment, the transistors T ₁ , T _{2 are} in the one phase position (U ₁₁₂ , U ₁₉₁₂₀ each have the same sign) in the collector _{circuit, in the other phase position (LZ 1 2} , 1 / _19/20 each have an unequal sign) in the emitter circuit operated. The voltage gain in the collector circuit is calculated from

r _h + iHr _e
the current amplification off

the power gain P _k is the product of the current and voltage gain:

circuit operated transistor T ₃ is 7 ^ = ^,

and / _C3 '== J ₈₁ ; the current gain of the two directly coupled and cascaded transistors T ₁ , T ₃ therefore has the value

In the emitter circuit the voltage gain is ₌ (iR _L

55 the current gain

A current / therefore flows through the load resistor R _L , from point 16 to point 6. Transistor T ₄ is blocked by the voltage I / _17/18; the base circuit of transistor T ₂ is thereby separated, so that transistor T _{2 is also} blocked. It can be seen that in the following half-wave with constant phase position between U _1/2 and U _19/20, the transistors T ₂ , T ₄ conduct current and the transistors T ₁ , T _{3 are} blocked, so that the current through the load resistor flows again from point 16 to point 6.

-T-) = ß

and the power gain

in the equations IZ ₁ , Z ₁ mean input voltage and current, U ₂ , I ₂ mean output voltage and current, β the current gain in the emitter circuit, R _{L denotes}

Load resistance, r _h the base resistance and r _e the emitter resistance.

It can be seen from the equations that the voltage and power amplification of the emitter and collector circuit are only the same for values R _L <ε r _e. For values R _L » r _e and // · R _L » r _b , the power gain in the collector circuit becomes P _K ~ β <P _t:.

Now the current gain of an inversely operated transistor is generally smaller than that of the normally operated; the difference between the power gains P _K and P _t · (with a large R _L ) can therefore be compensated for by operating the transistors T ₁ , T ₂ inversely when they operate in the common emitter circuit and operate normally when they are in the common collector circuit work. For this purpose, only the emitter electrodes of the transistors T ₁ , T ₂ need to be connected to points 5 and 8, respectively.

In the circuit according to FIG. 3, the load resistance R _{1 is} halved, and the emitter electrodes of the transistors T ₃ , T ₄ and point 16 of the winding 15/18 are connected to the center tap 21 of the load resistor. While in the circuit of the first embodiment according to FIG. 2 the transistors T ₁ , T _{2 are operated} in one phase position of the reference and control voltage (both with the same sign) in the collector circuit and in the other phase position "(both voltages have unequal prefixes) in the emitter circuit, the operation of the transistors T _1. T ₂ in the circuit of FIG. 3 is the same in all phase positions between control and reference voltage. There is always a resistor R _{1, z} in the load circuit and a resistor R, ₂ in the control circuit of the transistors T ₁ , T ₂ , so that the same current gain is assumed in both operating directions, in both modulation cases

same gain. 1st., ': S »r, .and' -, '·» r _h .

This results in a voltage gain of approximately size 2 and a power gain of approximately size 2 (i. The mode of operation of the circuit can also be understood with the aid of the description of the first exemplary embodiment according to FIG. 2.

Claims (1)

Patent ^claim:; Phase-sensitive rectifier circuit using transformers and transistors to convert an AC voltage signal into a direct current, which flows through a load resistor and whose direction is determined by the phase of the AC voltage signal in comparison to the phase of a reference voltage and whose size is proportional to the amplitude of the AC voltage signal, especially for Open-loop or closed-loop control, characterized in that the two ends of a center-tapped secondary winding (5, 6, 7, 8) of a reference voltage transformer (V ₁ ) to which the reference voltage (U _1/2 ) is fed on the primary side (1, 2) , each with a tertiary winding (3/4, 9/10) of this transformer via the collector-emitter path of a rectifier transistor (T ₁ , T ₂ ) verbun that the load resistance (R ₁ ) between the center tap ( 6, 7) of the secondary winding (5, 6, 7, 8) and the through connection of the free connections (3, 10) of the tertiary windings (3/4 and 9/10) is that the base (11, 12) of each rectifier transistor (T ,, T ₂₎ each one connected to the collector of the rectifier transistors (T _1, T ₂₎ complementary transistor (T _3, T ₄₎ is that the emitters of these transistors (T ₃ . T ₄ ) are connected to one another and to the center tap (16, 17) of the secondary winding (15, 16. 17, 18) of a signal transmitter (Uj) to which the AC voltage signal (U _{iq 20} ) is fed on the primary side (19, 20), wherein the base (13,14) of each complementary transistor (T ₃ , T ₄ ) JeWCiIs is led to one end of the secondary winding (15, 16, 17, 18) of the signal transmitter (t? i) and the center tap (16. 17 ) this winding (15, 16, 17, 18 either with the through connection of the tertiary windings (3 4 and 9 10) of the reference voltage transformer (P ₂ ) or with a center tap (21 in Fig. 3) of the load resistor (R ₁ ) is connected. _v For this purpose I sheet drawings