DE1437698C3 - Method and device for transmitting information represented by binary signals - Google Patents

Description

The invention relates to a method for transmitting information represented by binary signals between a central data processing unit and several connection units, such as input and Output units communicated by transmission lines on a time-division basis with the memory of the central Processing unit can be coupled, using transmission control data contained in the memory (Transfer control words) indicating the type of transfer operation and the addresses of the Specify the data to be transmitted, and a device for carrying out this method.

Known methods and devices for data transmission between a central data processing unit and several input and output units use separate control and transmission circuits, which are put into action by a program command of the data processing machine and thereupon an information transmission to or from a selected connection unit or at Carry out multiplex operation to or from several line units. Doing so must take precautions be taken that at the point in time at which the processing unit requests the transfer, too the relevant line units are ready for transmission. This is done on the one hand with a strict synchronous operation between processing unit and connection unit is achieved. Here, however, the Working speed determined by the relatively slow input and output units, so that Processing unit waiting times cannot be avoided. In addition, control circuits are necessary that establish this synchronous operation and monitor it continuously. According to other methods, buffer memories are allocated to the transmission control unit in which the to transferred data to a transfer request be cached until the relevant line unit is ready for transmission. or, when this sends the data until the central processing unit is ready. This is a significant one Expenditure on "" storage and control means is necessary. There usually a plurality of input and output units work together with a central processing unit, is also a control for the distribution of the Buffer memory space on the various line units according to the amount of data as well as a monitoring of the sequence and the belonging together of the buffered on a multiplex basis Partial information required. In connection with these procedures it is also known to use a to be transferred to a control data group to be assigned to the data group during the Transmission precedes and in the receiving station control circuits according to the respective type of transmission adjusts. Furthermore, it is known in this method to use command words, among other things also data transfers between a central processing unit and those connected to it Control input and output units to assign special control words in the program memory. When calling of the relevant command word is called up by the address data contained in this Control word. The command word and the assigned control word jointly determine the selection of the transmitted data and the type of transmission (e.g. German patent 11 51 686). In these procedures a considerable amount of memory required for storing the control words, which increases with the increase in the the amount of data handled or the program length grows. In this context is also already has been proposed to assign a first control word to a specific transmission channel Addressing a list of the addresses of the data words to be transmitted and a second control unit for storing successively addresses taken from this list. The latter control word is used to address the Data words that are to be transmitted via the assigned channel. Meet the above disadvantages also to such a modified arrangement. It is at

Data processing systems also known to store operational status data from input and output units in an area of the memory of the data processing system assigned to the relevant unit in the form to collect a status word (German Auslegeschrift 11 51 397). When an error occurs, uses the collected status data to start a correction subroutine while the actual data transmission remains unaffected by the status words ι ο

The object of the present invention is to provide a method for data transmission in both directions between a central processing unit and several connection units to indicate which one should be avoided of the disadvantages mentioned, a data transmission under direct control of the central processing unit Allowed and yet waiting times for this unit and the additional effort for extensive transmission buffer memory and this avoids associated control circuits. According to the invention, this is done by accessing one of a connection unit or a request delivered by the central processing unit into the central processing unit Contained memory area permanently assigned to the relevant line unit (line unit control word) is called, which has a first sub-area for receiving address data to be transmitted Information, a second sub-area for the inclusion of address data for an operation transmission control data relating to the relevant initiation unit and a third sub-area for receiving status display and control signals the associated line unit includes, and that by calling this memory area through Transfer control data addressed to the relevant sub-area from the memory of the central Data processing unit are transferred to the called line unit storage area under whose influence then the transmission takes place in a single or several transmission cycles.

Another advantageous embodiment of the method according to the invention is characterized in that the line units are repeatedly scanned for the presence of a transmission request and that determines the address of the requesting line unit when there is a transmission request and with this the assigned standard control word for controlling the transmission is read out.

Another advantageous embodiment of the method according to the invention is characterized in that depending on the machine program (problem program) of the central data processing unit one of the line units is selected by looking for the unit control word assigned to this line unit that this unit control word is checked for a busy or ready state and that at Presence of a ready state control data from other storage locations of the central processing unit in the unit control word for controlling the Connection unit are transmitted.

Another advantageous embodiment of the method according to the invention is characterized in that each unit control word at least one stored in a memory of the central processing unit Transfer control word is assigned to the unit control word by a command of the Machine program (problem program) is called and the control and address data for the to contains transmitted information or partial information, and that depending on the ready state the connection unit assigned to the called unit control word, the content of the transmission control word is used to fill the standard control word.

Another advantageous embodiment of the method according to the invention is characterized in that the transmission control words regardless of the content of the unit control words during the course of the Machine program can be called up and loaded.

Another advantageous embodiment of the method according to the invention is characterized in that a concatenation identifier is stored in the transmission control word, which indicates a linkage to a further transmission control word assigned to the same unit control word, and that at the end of the transfer operation determined by a transfer control word, the concatenation identifier is queried and dependent on this another transmission control word is called and in the assigned unit control word for further control the relevant connection unit is transferred.

Another advantageous embodiment of the method according to the invention is characterized in that the different transmission control words linked by a concatenation identifier Control types of operations.

A main advantage of the method according to the invention is that the data transmission from the central processing unit to one of several connection units or vice versa under control of the contained in the central data processing unit with only a small microprogram control unit Expenditure on additional circuit means can be carried out, with the time of transmission or their preparation within the current problem program both from the central data processing unit as well as from a connection unit can be chosen as desired and the possibility is given to set up a complete separate transmission program within its sequence does not require re-entry into the problem program.

The invention also provides an advantageous device for carrying out the method according to the invention before. In the case of a central data processing unit, which has a main memory, a microprogram read-only memory, has a computing unit and a plurality of data and address registers, some of which are used as Data input and data output registers are used for the transmission lines to the connection units, This device consists in the fact that the microprogram read-only memory contains information transfer routines and routines assigned via these routines Outputs with a transfer register arrangement is in connection, which is used to control the connection paths between the main memory, the data and address registers and the arithmetic logic unit and for Control of the data transmission paths to the connection units is used and has the memory stages, which are connected to all connection units common control signal lines and the type of Mark data on the data transmission paths as well as control states related to this data.

An advantageous embodiment of the device according to the invention is characterized in that the Connection units connected to a scanning circuit

and have selection circuits which are responsive to scanning signals generated by the scanning circuit and when the line unit in question is in the ready state, the scanning circuit becomes ineffective make as well as a transmission of the address of the relevant connection unit to the central processing unit cause.

Another advantageous embodiment of the device according to the invention is characterized in that the sampling circuit does not include a series connection of the line units on which a sampling pulse one after the other passes through all line units that the selection circuits when a sampling pulse occurs in the series link in the case of a ready state interrupt the series link and in the case an occupied state forward the scanning pulse to the next line unit and that from the last Connection unit a return line to the central processing unit is provided through which the returning sampling pulse a repetition of the sampling is initiated.

Further advantageous developments of the invention are characterized in the remaining subclaims. It shows

F i g. 1 is a simplified block diagram of the connections between a central processing unit and a number of input and output units,

F i g. 2a, 2b, 2c a block diagram of the data processing unit according to FIG. .1,

F i g. 3a and 3b a block diagram of a coupling unit according to the invention, as it is in connection with the central processing unit according to FIG. 1 is used,

4 those used by the method according to the invention Control word formats and

F i g. 5 is a block diagram of a selector channel as it is in the central processing unit according to FIG. 1 is used.

The central data processing unit used in the example shown is shown in FIGS. 2a, 2b and 2c shown. The memory 2204 (FIG. 2c) is used to hold data that are sent to or from I / O units are transmitted, for general use, of commands, etc. Except for the memory itself, the Contains adjustable cores with a rectangular hysteresis loop, are sensing amplifiers 2206 for out of the cores extracted information is provided, and lock drivers set the cores as the Request data on bus 2208.

A decoding circuit 2207 selects the eight-bit byte in memory 2204 which is to be used Data bus 2257 is to be transferred.

An M register 137 and a / V register 138 are the Memory address registers which are used to select a byte memory location from which information should be read or written. Each register 137 and 138 holds one byte or eight bits. Through Setting a number in the M / V register reads a specific memory location from the core memory.

A / register 134 and a / register 135 (Fig. 2b) normally function as instruction counters for the Data processing machine. This register combination, in which the / register contains the higher and the / Registers contain the lower digits, usually contains the address of the next instruction word byte, which can be taken from the memory 2204. Depending on the one from the central processing unit The function to be executed can, however, be the content of the // register in memory 2204 at a (CW burst memory) designated location and the // register for finding an operand address be used.

A {/ register 142 and a V register 143 have one Capacity of one byte each. The [/ register contains the high-order byte and the V register contains the lower-digit bytes. The t / V register usually contains the address of the operand that is stored in the

ίο data processing machine is to be evaluated. A T register 141 is also an address register and is normally used to select certain ones Areas of memory called general purpose registers.

The Γ register, which only holds one byte, addresses the lower memory locations. The general purpose register will indicated by the higher-order bits in the Γ register, while the bytes in the general purpose register are indicated by the two lowest bits are designated so that in a general purpose register with a total of four bytes or 32 bits each byte can be selected individually.

The //, UV and T registers are connected to the MN bus 104, 105. During the normal process, the address contained in these registers is transferred to the MN register by a microinstruction word from a specific address register, and a memory location is read out by the following microcontrol command.
A D register 132 (Figure 2b) is a general purpose register and is commonly used in various operations to hold a byte of data while the central processing unit is processing other data in combination therewith in order to draw a logical conclusion from the resulting combination.

A G register 133 is used to store the operation code byte. The 5 register 140 contains eight Latch circuits 50 to 57 which are used to set a specific condition or control function display in the machine and generate signals as well as machine operations by selecting Influencing microinstructions.

In general, each interlock circuit in the 5 register 140 serves a specific function, namely:

50 True Complement Lock Circuit.

51 “Execute code and data channel request w-interlock circuit.

52 "Answer not equal to zero" -
Interlock circuit.

53 Carry Over Latch.

54 Z high = zero.

55 Z low = zero.
56 and 57 general purpose switches.

5 8 Decode Latch.

The L register 136 is generally used to store the length of the memory too extracting field, d. H. the number of bytes it contains. It also becomes the L register however, used as a general purpose register in which data can be stored in any logical or arithmetic operation should be used.

An arithmetic and logic unit 699 (FIG. 2c) is connected between a /! Register 130 and a β register 131; it receives data from the A and β registers and performs an arithmetic or logical operation. The ALU unit 699 uses a circuit already described elsewhere

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arrangement a true complement operation with a data byte supplied from the B register 131. She also has the ability to do either to process the higher or lower part of the byte contained in the B register. the Output information from the ^ register is fed to the ALU unit 699, and is on this page ensures that either the higher or lower part of the byte in the Λ register is processed will. This part of the ALU unit 699 also contains a circuit arrangement for direct reception of the character, d. that is, the higher-order bits in the higher-order digits and the lower-order bits in the lower digits appear, or crossed reception, leaving the four higher digit bits in the four occur in lower places and vice versa.

The transmission controls provided at the output of the ALU unit 699 provide the status interlocking circuits in 5 register 140 so that the sequence of subsequent microinstruction words thereby being affected. According to the table above, the latch circuit 52 indicates that the Data supplied to ALU unit 699 are equal to 0. In the event of a carryover in the ALU unit, a Status latch circuit 53 set. The status interlock circuits 54 and 55, when set, indicate that the outputs of the four higher-order bits are equal to 0 or that the output signals of the four lower-order bits are equal to 0 are. The status lock circuit 50 is a true complement lock circuit and can can be set as a result of an operation in the ALU unit 699.

The register 139 (FIG. 2c) acts primarily as a buffer for memory 2204. Information is read from the sense amplifiers 2206 and transferred to the / ^ register 139. From the λ register, data are transmitted via the / 4 collecting line 100 to the ALU _: unit 699 and to the registers specifically designated in each case of the above-mentioned registers. In addition, data from the λ register can be transferred to the B bus 100 and into the B register 131.

In any case, the data in the central processing unit is first entered in the register 139 transfer. From the output of the register, information about the blocking bus line 2208 transferred back to memory 2204.

In the course of a typical operation of the central processing unit, each one is read out anew at the beginning Command transfer the address in the // register 134,135 into the MTV address register 137, 138, and at on a subsequent round-trip, the address in memory 2204 is selected and the data is written to the /? - Register 139 entered. From the Ä register 139, the data via the .A bus 100, the ALU unit 699 is transferred to the Z bus 103 and into the G register 133. During this time it is the address in the // register is incremented and another address is selected in the memory as well as the data byte to the / J register and then perhaps to the L register to one of several Display conditions.

In further // cycles, data is transferred to the Γ register, which is a general purpose register in memory to be selected and to which the contents of the t / V register 142, 143 are added to make a to represent certain memory address.

In each instruction cycle, the output of the ALU unit 699 is activated by means of the status register latch circuits which in turn contribute to the control of the next address memory location in the read-only memory 150, from which the next following microinstruction word is selected. As already mentioned, becomes the G register 133 which is multiple bit latch circuits also used to select the addresses of microinstruction words in the

ι ο read-only memory 150 to control.

The H ^ Y register 144, 145 (FIG. 2a) selects the address in the read-only memory 150 which is read out in order to control the machine. The HW and // A 'registers 148, 149 and the CW and CY registers 146, 147 are used in conjunction with the read only memory 150.

The selector channel 151 shown in FIG. 2a is an output of the central processing unit and is described in detail below. An output 2257 of the memory 2204, an AT collecting line 2274, a Λ collecting line 100 and the lock manifold 2208 connected.

The multiplex channel 152 is connected to the central processing unit by the data bus 2310. The input from multiplex channel 152 is shown as manifold 2312 connected to / 4 manifold 100. Information flows from the memory 2204 to the Ä register and from there to the output line 2310. Information is therefore on line 2312, in the / 4 register 130, in the ALU unit, in the i? Register and on the locking Collector line 2208. The data of the control circuit are transmitted via the ^ -bus line 2274 and the control lines labeled PI and PT. The information from the multiplex channel 152 is transmitted to an input-output unit 153 which does not belong to the central processing unit.

In Fig. 1, reference numeral 1631 generally designates a central processing unit of the foregoing (F i g. 3a to 3b) described type. This unit is provided with a multiplex channel (Fig.3a and 3b), the by a coupling unit consisting of data output lines 1601 to 1609, data input lines 1611 to 1619, address output command output and output operation control lines 1621 to 1623, Address input, status input and input operation control lines 1624-1626, select output and Select input lines 1627 and 1627 'as well as interlock and special control lines such as Output operation input, input operation input and interruption suppression lines 1628 to 1630, to several input and output units 1633, 1634 and 1635 is connected via a single I / O control unit 1636 or a multiple I / O control unit 1638. the Data output and data input lines are used to transfer data between the central Processing unit 1631 and the I / 0 units, such as the input and output units below Should be mentioned for the sake of simplicity. The control lines transmit control signals. Output timing and input timing lines 1610 and 1620 connect the central processing unit and control units for timing purposes. A clock output line 163Γ controls the timing unit of the control unit when the central processing unit is waiting or stopped. The central processing unit 1631 with the control units 1636 and 1638 is through the select output and select input lines 1627

and 1627 'connected in series. The select output line 1627 periodically receives pulses from the central processing unit to interrogate the I / O control units in series and thereby a select certain or one of the I / O units to enable the channel in the order of precedence that. determined by their distance from the central processing unit to be seized.

Multiplex channel switching

The multiplex channel circuit is shown in FIGS. 1 and 2a to 2c shown schematically. Details of the arrangement are shown in particular in FIG. 3a and 3b shown.

The output signals of the F register 139 (FIG. 2b) are transmitted to the data output lines (to the I / O unit) 1601 to 1609 (FIG. 1). A data output control signal 2302 (FIG. 3a) effects the switchover, which makes it possible to route the output signals of the /? Registers R 0 to R 7 and RP via the gate circuit 2311 to the data output lines bit 0 to bit 7 and bit P. The data input lines 1611 to 1619 (FIG. 3a), which are connected to an I / O unit, run directly to the transmission circuit 562 in FIG. 2c. A control signal “A = PI” for the circuit 562 causes the transmission from the data input lines of the coupling unit to the A bus 100.

The PA register 2300 (FIG. 3a) consists of several interlocking circuits, five of which are switched on by the coincidence of the line PA = K 582 with each of the lines K 0, K I _1, K 2 or K 3 and / or KP . The individual ^ lines come from the K decoding block 595 in FIG. 2 B. They result from the CK-Te'ü of the microinstruction word, which is decoded in the ^ decoder. Four of the five mentioned latch circuits, which are controlled or switched on by the ^ lines, generate the following four signals.

K 0 switches on the interlock circuits, the output of which is the data output control 2302. The output of the latch circuit switched on by Ki is the address output line 1621. The output of the latch circuit switched on by K 2 is the command output line 1622. The output of the latch circuit switched on by K 3 is the output operation control line 1623.

The output signal of the latch circuit 2321 switched on by line KP prepares two AND circuits 2322 and 2323, one of which is switched on with the selection input line 1627 'and the other with the multiplex latch circuit 2303. The output signals of these AND circuits are logically linked in the circuit 2324 in OR form and switch on a second interlocking circuit 2325 with the designation "query control", the output of which is the dialing control line 2301.

A sixth latch circuit in PA register 2300 is turned on by the simultaneous energization of the output burst 344 and input 1626 lines. The output of this latch is the PT3 input control signal on line 1626. The select output on line 1627 passes through the I / O units connected to the channel and if none of these units is requesting service, it returns as the select input on line 1627 '. This signal travels through a delay device and turns off the select output signal on line 1627. When turned off, the select output signal turns off the select input signal and, after a delay, turns the select signal back on. This polling of the output devices continues until that output device disconnects the select output line and the input mode-in signal on line 1629 returns to the channel, which also disconnects the select output select input circuit.

The ίο coming from the channel PT lines (F i g. 3a and 3b) extend to the position denoted by "Transfer PT to A" transmission circuit 579 in F i g. 2 B. A signal "A = PT" at the control input of this circuit causes the transmission from the FT lines to the Λ collecting line 100. These are the following P7 * lines:

FTO, line 1624, is the address input and comes directly from the I / O unit via the cable of the coupling unit.

PTi, line 2306, is the time division multiplex request signal and comes from the channel circuitry in FIG. 3a.
PT2, line 2301, is the interrogation control / signal and is the output of the cascade of latches in PA register 2300 described above.

PT3, line 1626, is the input operate signal generated in PA register 2300 by the latch circuit described above.

PT4 is the multiplex channel mask signal and is the output of the FL latch circuit

2500 in PB register 2304 (Fig. 3b). This register is described below. PT5 is called "re-entry troubleshooting" and is the output of the FL interlock circuit

2501 in the Pß register.

PT6, line 1629, is the input mode on signal and comes from the I / O unit via the cable of the coupling unit.

PT7, line 1625, is the status input signal and also comes directly from the I / 0 unit via the Cable of the coupling unit.

The PB register in Figure 3b consists of several latch circuits of the FL type. These latches require the coincidence of a negative signal on the line ending in the arrow and a positive signal on the line entering just below the arrow. A description of the mode of operation follows on the basis of the FL interlocking circuit 2502 / I / O data.

The input marked with an arrow at the top left of this block comes from an inverter 2503 that is fed by the ATP line. The inverter output thus supplies a KP signal. The lowest input comes from the output line 0100 of the X-field decoding circuit 2504. In order to switch on the FL latch circuit 2502, the signal 0100 and the signal KP are therefore necessary. To obtain the signal 0100 from the K-field decoding circuit 2504, three input signals are required, namely the one on the "Α-time" line, the one on the "PB = K" 15 & i line and the one on the K2 line. The other interlocking circuits in PS register 2304 are set or turned on in the same manner except for the top three latches. Here the negative input signals are individually separated via three

Inverters generated in lines R 7, Ri and R O. The FL latches in PS register 2304 are turned on and off by the microprogram control signal "PB-" s in addition to the required combination of the / ^ lines from the / CD decoder circuit 595 (FIG. 2b). The outputs of these FL latches are used to control various functions that are necessary during channel operation and are described below:

Three different channel mask lines or operations are stored in the first three interlock circuits 2505, 2506, 2500 , namely the signals "direct data channel mask", "selector channel mask" and "multiplex channel mask". The "direct data channel mask" signal is fed to the direct data channel via line 2507 , the "voter channel mask" signal runs to the voter channel via line 2271 , and the "multiplex channel mask" signal is sent to the PTA line. These mask output signals are used to generate the interrupt suppression signal in the respective channels in order to prevent the I / O units from interrupting the central processing unit. Latch 2508 in Pβ register 2304 provides a "channel interrupt " output on line 2272. The output of this latch is fed to selector channel controls 2275 in Figure 5b. The next latch circuit 2509 is the multiplex latch circuit with output line 2303. It is switched on during a time division multiplex operation by certain microprogram words and is reset after the time division multiplex operation. The output signal of this interlock circuit informs the central processing unit that a time division multiplexing operation is in progress and also prepares the interrogation control in the ΡΛ register 2300. The output signal of the interlocking circuit 2501 is the so-called "re-entry error search" signal PT5, which informs the central processing unit that it should continue to work in a certain way during the priority control processes. The output of the next latch circuit 2510 is called "output mode on-off". It causes the output service on line 1628 to be turned off, thereby informing the I / O unit that the channel is out of service. By switching off this blocking line (output mode on), a basic reset operation is also carried out within the I / O unit itself. The last latching circuit 2502, the output of which is the I / 0 data line 2305, is switched on during an exchange of data with the central processing unit in order to inform the central processing unit that the memory location just addressed in the main memory is either data for the I / O Send unit or receive data from the I / O unit.

General description of the coupling unit
(Fig.l)

60

With the help of the in F i g. 1 I / O coupling unit shown enables a uniform method for connecting I / O control units to channels. she consists from a group of lines that are time-division multiplexed to carry all information for to transfer the operation of I / O units. This information consists of device addresses, Control signals and data. The coupling unit can have up to eight I / O control units and up to 256 directly operate addressable I / 0 units.

The possibilities of the coupling unit to carry out a time division multiplex operation make it possible that any number of the 256 units can work simultaneously via a single coupling unit; d. i.e., parts of various Messages can be nested via the coupling unit to or from different I / O units or the complete message can be transmitted in a single operation of the coupling unit be transmitted. The mode of operation is determined by the respective channel and the relevant I / O control unit definitely.

The data exchange between the central processing layer and the I / O units is carried out by the in FIG. 1 and 3 shown coupling unit allows. The coupling unit comprises a data output line which contains eight data transmission lines and a parity line with the reference numerals 1601 to 1609 , a data input line which consists of eight data lines and a parity line 1611 to 1619 , and ten control lines 1621 to 1630.

Structure of the information

The information on the data input and data output lines are arranged so that the Bit position 7 of a line always contains the low-order bit within an 8-bit byte. The highest digit Bit is in position 0 and the bits in between are in descending order of position 1 to 6.

If a byte transmitted via the coupling unit consists of fewer than eight bits, the bits must be used in the highest-digit adjacent bit positions on the bus. So if a central processing unit or an I / O unit only transmits the six bits of the ßCD code via the coupling unit, bit B in bit position 2 (line 1603) of the bus, bit A in bit position 3 etc. and bit 1 in bit position 7 (line 1608) is used. If a central processing unit or an I / O unit transmits information on only four lines of a bus or receives it on only four lines, the bit positions 4, 5, 6 and 7 must be used. All unused lines of the data input or data output bus must include the lower bit positions, ie bit position 0 and the adjacent bit positions. The parity bit of each byte must appear in the parity bit position. Unused lines must emit logical zeros at the receiving end. ₍

Command byte

When the command output line 1622 is energized, the information on the data output line is referred to as the command byte. A channel issues the command output signal in order to initiate, continue or terminate an operation in an I / O unit.

Only during a preliminary selection sequence (when the channel is addressing the unit) is decryption of the command byte required by the control unit. The byte is the same at all other times zero (correct parity), even if it should not be checked for parity by the control unit. the lower bit positions indicate the type of operation,

while the higher bit positions represent a modification code which extends the basic operation at the level of the control unit.
The actual modification codes and each

The operating modes set or the control carried out for them are named in the functional description of each control unit for the device in question.
The command byte is structured as follows:

Bit positions 0 1 2 3 4th 5 6th 7th Check I / O (continue *), (stack *), (stop *) P. 0 0 0 0 0 0 0 0 Bottling 1 M. M. M. M. 0 1 0 0 Read backwards P. M. M. M. M. 1 1 0 0 To write P. M. M. M. M. M. M. 0 1 Read P. M. M. M. M. M. M. 1 0 steer P. M. M. M. M. M. M. 1 1 P. Explanation:

* = Not decoded or parity checked by the control unit. M = bits of the modification code.
P = parity bit.

General mode of action

The I / O operation to be carried out via the coupling unit is determined by the eight-bit encrypted command issued during the introductory Selection sequence of the device is given.

The lower bit positions of this command byte indicate the type of operation. The higher bit positions (Modification code) extend the basic operation at the "level" of the control unit or the Connection and do not affect the sequence of basic operations on the coupling unit.

The basic operations or commands are: reading, reading backwards, writing, controlling, sensing and I / O checking.

The read command directs the execution of a data transfer from the control unit to the I / 0 channel on, namely the data from the labeling source of the I / O unit that is currently in operation attained.

The read back command initiates an operation in the same way as the read command, only the data bytes are transferred to main memory in the reverse order than when reading through the channel transfer.

Write operation

The same sequence flows through the I / O coupling unit of signals for performing a write operation as for a read operation. During a write operation the data is sent from the I / O channel to the I / O control unit sent to be recorded or compared by the selected I / O unit. The operation is not initiated at the device level until the first byte of data is received; h., not before the output operation control signal falls to the input operation control signal in the first data cycle there.

35

40

Control operation

The control operation is exactly the same as the write operation, except that they are handled by the I / O control unit command modification bits received are decoded to determine which of several possible Functions should be performed. The function can be addressing on the second Act level, for which several bytes of data may be necessary to complete the control operations. In

In cases where the relevant control function can be completed immediately (control operation immediately), the end, "unit released" and other associated status signals can be given during the initial selection sequence. If the control operation is not "control operation immediately," at least one round of data transfer is required.

The timing in the I / O control unit for the bytes transferred during a control operation is normally done so that the byte rate for this Operation is not faster than normal read or write speed for the same device. very slow or manual key operated devices can benefit from this limitation excluded what is individually determined. Another acceptable procedure for that Timing of byte transfers during data multiplexing consists of the Restrict selection rounds to single-byte transfers on every other output selection signal.

Pick-up operation

The sensing operation proceeds exactly as it has been described for the read operation, only the Data derived from status indicators rather than a record source. The during a Bytes transferred to the sampling operation are normally timed in the I / O control unit so that the byte speed for this operation is no faster than the normal read or write device for the same unit. Very slow units or units with manual keystrokes can go from this restriction can be exempted from what is to be determined individually. That is also acceptable Procedures for timing byte transfers specified above for control operations.

Check I / O

"Check I / O" is a command that sequentially sends the addressed I / O control unit and the addressed Checking the I / O unit for outstanding status information. An I / O check operation is performed on the first level, where you encounter pending status information. If there is no outstanding status information is present along the checked I / 0 path, a zero status byte (display for »available unit«) for the selected I / O unit is sent to the I / 0 channel for processing. If the level of the I / 0 units

709 611/411

ten is reached during the I / O check operation and Waiting for status information, all outstanding status bits for the selected I / O unit become the I / 0 channel transfer.

The "Check I / O" command can encounter a busy status at any I / O level. In this In this case, only a busy bit in the status byte is transmitted back to the channel. The busy state becomes defined differently with regard to »check I / O« than for other programmed commands (see »busy«).

The signal sequence for executing "Check I / O" is almost the same as for any other introductory signal Selection process. The difference is that no operation is initiated for the selected device will.

Sequence controls

Sequences are not controlled by a command, but by the order of the Coupling unit transmitted signals determined. The various consequences that can occur are the following: continue working, stopping, stacking, data suppression and status suppression.

Keep working

Whenever the command output line responds to an address signal at any time other than responds during an introductory dialing sequence, it means "keep working". The signal »continue working« indicates to the device that it should continue the normal operating sequences in the coupling unit.

To stop

If there is a command output signal in response to an input operating signal is generated, that means "stop".

The stop signal tells the I / O unit that that the channel is just finishing the current operation. When the stop signal is received, the I / O unit will continue to operate to its normal end point without any further input operating signals to send to the I / 0 channel. The unit remains occupied. She has to send an end signal when her necessary Status information is available. During data operations, the command output signal is in response to the input operating signal in the cycle after the last data byte. When the output select line is or is switched off after this sequence, the signal »input mode on« can be on I / O units drop out that meet the »time-out« conditions, which are explained below, cannot meet.

Pile

If a command output signal occurs in response to a status input signal, this means "stacking". The Stack signal strings the "Status" signal on the I / O control unit or the I / O unit until it is in a following status cycle is assumed with an output operating signal. After the occurrence of the Stack signal, status cycles are initiated under the control of the suppression output signal.

Data suppression

When the suppression output line is energized during the initiation of data circulations, means each "data suppression". Data suppression is only displayed for operations whose Transfer rate can be adjusted without exaggeration. Buffered and Start-stop operations. For these types of I / O units, the I / O control unit is designed in such a way that the Input operate signal cannot rise when the suppression output signal is energized. The data suppression does not apply to the first data byte of each selection sequence.

Status suppression

The status suppression only relates to "Attention" or previously stacked status signals. the Status suppression is displayed whenever the suppression output line is active during a Select scan sequence is energized. The status suppression signal prevents the I / O controller from receiving a Selection sequence initiates.

Chained command control

The chained command control is always displayed when the suppression output line 1630 is energized and the output service line receives a signal from the status input line Chained command control indicates that another command for the same I / O unit will be issued immediately (the exact time depends on the I / 0 channel) after the current operation has ended. None other operation, such as B. Unit exchange or attention (busy), may intervene as long as the Concatenation is displayed. If a chained command control at the end of an ongoing Operation (status "Unit released") has been displayed, the display is valid until a new selection is made is hit or until the suppression output falls. In addition, every new Selection of any I / O unit connected to an I / O control unit with the status »chained Commands «deleted in the I / O control unit.

Disconnect the coupling unit
(Stop input and output)

The disconnection of the coupling unit is always indicated when the address output line 1621 is excited if the output selection line is switched off, while an I / O unit is connected to the coupling unit connected (input operation-on-line energized). The command »disconnect coupling unit« cancels the forced burst mode of operation. For this sequence, the I / O unit that is currently connected to the Koppe'einheit is connected, disconnected. Any mechanical movement in progress will be up to continued at a normal stop point Each generated status signal becomes the corresponding channel for the channel Time fed. The coupling unit disconnect control results from an I / O stop command, the is currently being carried out on the I / 0 channel. Any abnormal operation of the I / O unit must be identified by the status signal action required will be displayed and the sensing information will provide more details on the Surgery.

Optional provision

An optional reset is indicated whenever the suppression output line 1630 is energized and the output mode on line 1628 drops. Under these conditions the signal is on the input mode on line 1629 terminated, and the currently operating I / O unit is shut down and you

Status signal reset. Any mechanical movement currently in progress will if possible continued to a normal stop point. The I / O unit that worked via the I / O coupling unit is the only one to be reset, even with I / 0 control units with multiple I / O units. The conduction path of the I / O unit in question is throughout this Operation in the busy state.

General provision

A general reset is indicated whenever the output operation on line 1628 and the suppression output line 1630 are not energized at the same time. Under the circumstances, it will Signal on input run on line 1629 terminated and all I / O controllers and those attached to them connected I / 0 units are reset together with their status signal. Each in progress any mechanical movement will continue to a normal stop point.

Description of a complete I / O operation

The exact signal sequence for a complete I / O operation is described below. This includes the preliminary selection, data transfers and closing operations for the two basic ones Operating modes, namely data multiplex transmission and burst or group operation.

Data multiplex transmission
(Temporal nesting of the data)

Multiplexing the I / 0 operation is the normal mode of operation for slow I / 0 units. However, all I / 0 units are set up in such a way that they work in burst mode, if that is the I / 0 channel requests. Selector-like I / O channels force burst operation by following the initial selection keep the output select line energized.

Preliminary selection (data multiplex operation)

In order to initiate any I / O operation, the channel transmits the address of the desired I / 0 unit on the data output line and then increases the voltage of the address output line 1621. Each I / O control unit connected to the channel tries to decipher the given address . In order to be recognized, the address must have the correct parity and only one control unit must be able to recognize a given address. When the address output line 1621 is energized and the voltage on the incoming select output line 1627 rises, the selected controller energizes the input mode-on line.

If the channel is designed to multiplex data, it will turn off select output line 1627 during the initial selection sequence. Conversely, by holding the input mode on line 1629 energized, a controller may force the channel to operate in burst mode. After the signal on the address output line 1621 has subsided, the address of the I / 0 unit is transmitted to the data input lines, and at the same time a signal is present on the address input line 1624. After the channel has checked the address, it transmits the command to the data output line and energizes the command output line 1622. The selected I / O control unit then replaces the address with status information on the data input line and replaces the address input signal with a status input signal on line 1625. The input mode on line 1629 remains energized throughout this process the status information is communicated to the channel that the command has been accepted or rejected. If the channel accepts this status information with the select output signal and the select output line 1627 is turned off at the I / O control unit, the energization state of the input mode on line 1629 decays if the I / O control unit does not force the burst mode The selection phase ends after the desired connection between the channel and one of its I / O control units and I / O units has been established. When the I / O control unit sends a signal on the "intervention required" line 1617 with its status input signal to the channel, e.g. B. after an invalid command, if the channel accepts this status signal, it responds with a signal on the output operation control line 1627 . If the channel cannot handle this status signal, the command output line 1622 responds to the status input signal and the status is stacked as described below under the completion operation.

The channel is disconnected and fulfills other I / O needs while the selected one is on I / O control unit prepared to transmit the required data to or from the channel

If the current path of the I / O unit is busy, the I / O control unit responds with a busy bit only in the status byte. If the I / O controller has a pending status, it will talk to you Busy bit (display for a busy rejection of the new command) and the »pending status« - Signal on. If the command is »Check I / O« and the current path of the I / O unit is not occupied, there will be no Busy bit included in the status byte because the "Check I / O" command is not rejected. When the current path of the I / O unit is free, the control unit delivers a zero status signal. If the command is a control command that is specified and executed with the information contained in the command byte and both the channel and the control unit could immediately release again speaks the control unit with the final status signal.

Data transmission (data multiplex operation)

When the selected I / O unit needs to be serviced, the following operation takes place. The next time the output selection line on the I / O control unit is energized and no I / O selection νοτι channel is attempted, the I / 0 control unit transmits the address of the I / 0 unit to the data input line and signals to both the address input line 1624 as well as the input mode-in line 1629. In data multiplexing, the signal on the output select line 1627 from the channel is terminated after the voltage rise on the address input line 1624. When the channel has recognized the address and is prepared to send or receive the data, a command output signal is transmitted to the I / O control unit instructing it to continue working. The I / O control unit then replaces the address of the I / O unit on the data input line with the required input data, if it is read or removed, and causes a voltage drop

the address input line 1624 and a voltage rise in the input operating line 1626. The process is the same when writing or controlling, only there is nothing on the data input line: If the channel has accepted the input data or has output data available, it speaks to the I / O control unit with an output run signal on line 1623 . The control unit then switches off the input service line and the input service-on line if the output selection line at the control unit is switched off. The output operation signal decays after the end of the input operation or input operation on signal on the channel. The channel then energizes select output line 1627 in search of another I / O controller to be serviced.

The processes operated above * are repeated for each new data byte until the end of the operation is reached.

20th

Closing procedure (data multiplex operation)

The termination process can be initiated either through the I / O unit or through the I / O channel. When initiated by the I / O unit, the end of the operation is terminated in a signal sequence. If the process is initiated through the I / O channel, the I / O unit may still need time to complete the Reach the point where the correct status information is available; in this case there is a second Signal train necessary to carry out the closing procedure. One of three situations can exist if that Closing procedure is initiated:

1. The I / O channel detects the end of an operation before the I / O unit reaches its end point. In these circumstances, the next time the I / O controller needs to be serviced, it will make a selection and energize its address input line 1624 in preparation for data transfer. The I / 0 channel then generates a signal on the command output line 1622, which means "continue". The I / O control unit excites the input service line 1626 - after the command output line 1622 has been switched off. The I / O channel then generates the command output signal, the meaning of which is "stop". The I / O controller shuts down the input service line 1626 and continues to operate to its normal endpoint without requesting further service. When the I / O unit reaches its normal endpoint, the control unit obtains a selection and energizes the address input line 1622. The I / O channel then generates a command output signal. When the command output signal subsides, the I / O control unit transfers the status byte (with an end bit) to the data input line and energizes the status input line. The I / 0 channel then generates the output operate signal when it is not necessary to stack the status byte. This then terminates the data division multiplexing operation and causes the channel to continue with the periodic scan.

2. The I / O channel and the I / O unit recognize the end of an operation at the same time.

3. The I / O unit recognizes the end of an operation, before the I / 0 channel reaches the end.

In situations 2 and 3, which can exist when the graduation process is initiated, everyone stands Status information available on the I / O control unit. The light sequence is the same as above is described when the I / O device reaches its normal endpoint.

Stack status information
(Data multiplex operation)

If it is necessary to string status information, the I / 0 channel speaks to the status input signal the command output signal. The command output signal causes the control unit to activate the relevant Status to stack or to line up. The status remains stacked as long as the suppression output signal is excited. When the suppression output dies down, the control unit sends the status information at every opportunity until they are accepted (output run signal).

Data group transfer
(Data transmission in groups)

The group operation of the I / 0 operation is the normal operating mode for fast-working I / 0 units. These units force group operation (by keeping the input operation on line energized), if they are connected to channels that normally operate in data division multiplexing (multiplexing channels); medium-speed I / O. units that can normally work in either mode, such as it is determined by the data speed of the channel are provided with a manual switch to to be able to select the appropriate operating mode. The switch setting is overridden when group operation is forced through the I / 0 channel. A coupling unit shutdown signal sequence is set the status of a control unit, in which group operation is forced, overrides

Introductory selection (group operation)

A preliminary selection for group operation is almost the same as that described above for data division multiplexing. The difference is that if the channel is designed to operate in group mode, the output select line 1627 is not turned off after the input mode on line 1629 is energized. Because the output select line remains energized, the I / O control unit remains connected to the channel and no further addressing is required for data transfer as long as the output select line is energized. The selected I / O controller maintains its input mode on line 1629 energized as long as the output select line is energized. If the control unit is designed for group operation, it will keep the input operation on line energized to achieve the same result.

Data transfer (group operation)

In group operation, no address is required for data transmission to or from the channel. When a data byte is ready to be transferred to or from the 1/0 channel, an input operate signal is sent to the channel on line 1626 and the data byte is transferred to the data input line if it is an input operation. When the channel has accepted the input data or has data available for output, data is transferred to the

40

Data output line is transmitted, and the channel transmits a signal on the output service line 1623. This process is repeated for each data byte as long as the input mode on line remains energized.

Closing procedure (group operation)

The termination procedure is almost exactly the same as the termination procedure for data multiplexing, but no addressing is required to initiate stop sequence control. If after receiving the Stop signal, the output selection line 1627 is switched off, the I / O control unit can disconnect from the Disconnect the coupling unit by switching off the input mode on line 1629. In this case the final status signal is fed to the channel as it is for the Data division multiplexing mode has been described.

Conversely, if the input mode on line 1629 at the I / O controller remains energized when the I / O unit reaches its end point, the I / O control unit sends its end status signal to the channel, and if the channel accepts this status signal, it generates the output operation signal and the input operation-on line is turned off if the select output line is turned off. This will make the I / O operation finished and the I / O unit ready for a new one Choice made free.

Stack status (group operation)

If any status information cannot be processed, the channel then generates the Command output signal instead of the output operating signal, resulting in a stacking of each status input signal is effected in the I / O control unit. When the output selection signal falls before the command output signal falls, the I / O control unit turns off the input operation on line, thereby disconnecting it from the coupling unit. Conversely, if the select output circuit remains energized, the I / O control unit sends its status signal again

Externally initiated status

In the description above, all of the status information applied to the I / 0 signal was the result any previously initiated command. In deviation from this, there are two externally initiated Status sequences that have no relation to any previous command initiated by the program to have. The first is "Caution" and usually occurs in console or messaging devices on. The other externally initiated status sequence is always generated when the corresponding I / O unit passes from the "not ready" to the "ready" state. ["Not ready" here always means that one Unit is not mechanically ready and into a "ready" state due to operator intervention can be brought. The "Not Ready" state could occur as a result of the following: (1) Loading / unloading conditions on magnetic tape; (2) the card devices have run out of cards, or the Filing device is full; (3) the printer has run out of paper; and (4) error conditions where operator intervention is required.] The state is defined for each I / O unit and expressed in the sensing information.

Status byte format

When the status input line 1625 is energized, the information appearing on the data input line is referred to as status byte. This has the following format:

Position of parity Manifold danger P. Leap 0 1 occupied 2 Diploma 3 I / O unit released 4th Intervention needed 5 state of emergency 6th 7th

The status byte is transmitted to the I / 0 channel in five different situations: (1) during the introductory Selection process in response to the command output signal, (2) for the purpose of delivering the completion status information at the end of the data transfer, (3) for the purpose of issuing the "I / O unit released" signal and any related status signals to the I / O channel (the I / O unit remains occupied until the I / 0 channel accepts the "unit cleared" status signal), (4) for the purpose of issuing the attention signal to the I / 0 channel and (5) for the purpose of renewed delivery of a previously rejected status signal, if that is allowed.

Status bits

The condition under which any type of I / O control unit the respective status bit is generated is defined in the function targets for the I / O control unit. the Bits are defined as follows:

danger

The attention bit indicates that some asynchronous condition has occurred, as it did for the I / O unit each is defined. The attention bit cannot cause a busy rejection for a new command, if a chaining is indicated (see control of chained commands). For I / O units that need more as a channel path in common, the attention status bit is assigned to the channel or channels supplied as it is defined in the functional description for the relevant unit.

Leap

A jump bit with a "unit released" bit at the end of an operation means that the operation is successful under the condition specified in the original command byte has been executed. The jump bit tells the channel that it is the next chained command must skip. The channel only executes this function if all channel conditions are met. The Jump bit only occurs for operations that have been specially commanded, this jump bit indicator to create. The condition under which an I / O unit displays this jumping condition is functional Description given for the relevant unit.

occupied

(, 5 The busy bit only occurs during an introductory Selection sequence indicating that either the I / O control unit or the I / O unit is not for the Initiation of a new command available

709 611/411

stands because of a previously initiated operation or because of a pending status signal.

The availability for the initiation of a new command depends on it in certain cases whether the new command reads "Check I / O". The following situations illustrate the busy status for a specific I / O unit:

(1) after the initiation of any command and before the termination occurs: occupied for all new commands (the busy bit alone);

(2) after the completion signal has been issued, but if this has not been accepted by the I / 0 channel is: new commands with the exception of "check I / O" (busy bit plus termination status information);

(3) after accepting the completion signal from the I / 0 channel has been accepted, but the signal "Unity made free" has been accepted, but the signal "Unit vacated" has not occurred: occupied for all new commands (the occupied bit alone);

(4) the signal "unit made free" has been generated, but is either not yet for I / 0 channel transferred or rejected by the channel: new commands with the exception of »I / O check «(busy bit plus» unit released «- status signal);

(5) I / O control unit switched with two coupling units to a specific coupling unit (only the busy bit);

(6) switchable I / O unit selected for a specific I / O control unit, occupied for all commands via I / O control unit for which the I / O unit is not selected (only the busy bit);

(7) Attention bit (no chaining) has been generated and not accepted by the I / 0 channel, new one

'Commands with the exception of "Check I / O" (busy bit plus attention status signal).

Diploma

The completion bit indicates that the selected I / O unit has now been disconnected from the coupling unit and so that the channel can be cleared for operations on others. The I / O unit remains occupied until their "unity set free" signal has been accepted by the channel.

Unity made free

The "unit vacated" bit indicates that the I / O unit has completed any operation or that the unit has detected a transition from "not ready" to "ready". One I / O unit that is more is common as a channel path and for which a "unit vacated" bit has been generated because this unity has passed from the “not ready” to the “ready” state, must be a “unity Free "status byte to all channels that have selected this unit while they are in the" Not ready «state was.

Intervention needed

The "intervention required" bit indicates that the command cannot be executed or that the Operation encountered a condition during its execution that requires intervention either by hand or by the program.

The data check bit indicates that the I / O controller or the I / O unit has detected an error in the data transmitted to or from the I / O unit, or that one or more data bytes have been lost due to "overflow".

A sensing operation is necessary to find out the reason for the "intervention required" status signal.

The sensing information should, if possible, be between Errors in devices and errors caused by the program can be distinguished.

state of emergency

The exception state bit indicates that a condition which does not ordinarily occur has been detected. However, this can be a normal condition, such as B. the detection of a tape brand act. The State of exception bit has only one meaning for each I / O unit and a specific command.

Data output line

The data output line consists of nine lines 1601 to 1609 from the channel to all connected I / O control units. It is used to transfer addresses, commands and data to the I / O control units. The data output line consists of eight ^ information lines and one line for the W

odd parity. *

The type of information transmitted via the data output line is determined by the identification control lines leading to the outside. If the address offset line 1621 is energized during the initial selection sequence, the data output line indicates the address of the I / O unit in which the I / O channel wishes to initiate an operation. If the command output line 1622 is energized during the initial selection sequence, the data output line indicates a command. When the output service line 1623 is energized and has been energized in response to an input service signal during the execution of a write or control operation, the data output line contains information the nature of which depends on the type of operation. For example, it contains data recorded by the I / O unit during a write operation. During a control operation it can contain a sequence code or an address within the I / 0 control

unit or the I / O unit. Λ

The time period during which information on the Datenausgangsieitung are valid is determined by the labeling control lines during the transmission of the address of an I / 0 unit is the information on the Datenausgangsieitung valid from the excitation of the address output line 1621 to the excitation of the Eingangsbetrieb- In line 1629 or select input line 1627. If the channel is transmitting another type of information, the information on the data output line is valid from the occurrence of the signal on the associated outward control line until the signal on the corresponding inward control line drops. In all of the above cases, the validity of information on the data output line and the timing of the signals on inward and outward control lines are measured at the cable connectors on the I / O channel.

The skew on the data output line, that is to say slight temporal differences in the occurrence of the signals on the data output lines 1601 to 1609, must be dealt with by the channel. The channel has to

Delay the emergence of the signal on the control lines leading to the outside by an amount that ensures that the information is on the data output line by no less than 100 nanoseconds appear in front of the signal on the control lines leading to the outside when they are attached to the cable connectors be measured at the sewer under the worst possible misalignment conditions. The channel must therefore cause a delay that causes the skew caused by its own circuitry and it must also cause a delay of at least 100 nanoseconds to avoid the to eliminate the misalignment caused by the cable. For most I / O control units, this time is also sufficient to compensate for the misalignment caused by the receiver of the coupling unit. When a If the I / O control unit causes more skew, the control unit has to do an additional one to eliminate it Cause delay.

Data input line

The data input line is a group of nine lines 1611 through 1619 including the parity line, which lead from all connected I / O control units to the channel. It is used to transfer Addresses, status information and data on the channel. An I / O control unit can only access information send and hold on the data input line when its input mode on line 1629 is energized.

Which type of information is to be transmitted over the data input line is determined by the inward leading identification control lines 1624, 1625, 1626, 1620. When the address input line 1624 is energized, the data-in line indicates the address of the I / 0 line that is being selected. When the status input line 1625 is energized, the data input line contains a byte of information indicating the Describes the status of the I / O unit. If during the Execution of a reading or sensing operation the input service line 1626 is energized, contains the Data input line Information, the nature of which depends on the type of operation. While a read operation it contains a data byte from the record carrier. During a sampling operation it contains a set of bits indicating the exact status of the I / O unit and the conditions under which the last operation completed.

The length of time during which the information on the data input line is valid is determined by the Identification control lines determined. Information on the data input line becomes valid 100 Nanoseconds after the excitation of the assigned inward control line and must be valid remain until the corresponding control line leading to the outside is energized. In any case it will be the validity of information on the data input line and the timing of the signals the control lines leading in and out to the cable connectors on the I / 0 channel measured. The delay of 100 nanoseconds between when the signal is on the Data input line becomes valid, and the excitation of the control line leading inwards, imposes it on the Channel on to eliminate the misalignment in the data input line. The channel must have a delay in the inwardly leading control lines that compensate for the misalignment caused by the channel switching, and must also have a delay of at least 100 nanoseconds to eliminate the cable from the drivers of the coupling unit and any control unit logic caused skew. For most I / O control units, this creates enough time to correct the misalignment of the information to eliminate, so that the inwardly leading control line through the control unit simultaneously with the transmission of the information on the data input line can be excited. If a control unit can cause even more skew, it must cause the additional delay to correct it.

Exit operation-on-line

The output mode-in line 1628 is a line that extends from the channel to all connected I / O control units and which is used for interlocking purposes. Except for the suppression output lines all lines coming out of the duct are only significant if the output mode on line 1628 is energized In each case, all input lines from the I / O control unit must drop out of the output mode on line 1628 fall off and the operation in question must be canceled

will. *

The shutdown state of both the suppression output and output operation on signals are used to reset all connected I / 0 units. If the I / O unit is not working in "Off Line" mode, it is switched off when it is switched off two signals of a duration that is sufficient to cause a response from the circuit arrangement of the I / O unit to get the provision. The meaning of the reset depends on the respective I / O unit. To ensure proper reset, both the output mode input and the suppression output line both must be switched off at the same time for a period of at least 6 microseconds.

Address output line

The address output line 1621 leads from the channel to all connected I / O control units. It fulfills two functions:

1. The selection of an I / O unit is initiated by the address output line I / 0 control line signals of the address output line inform this that the address on the data output line must be decrypted. The I / O control unit that recognizes the address must then energize its input-in line when its input select output line is energized. The address output line is energized at least 250 nanoseconds before the Output select line.

The address of an I / O unit can only be given on the data output lines 1601 to 1609 if the selection output and the input operation on lines are switched off on the channel. The eventual use of the address on the data out line at the I / O control unit is timed by the next energization of the select out line. The address out line must be energized after the address is on the data out line. Misalignment has been discussed in connection with the data output line. It must remain energized until either the select input or input run on line is energized. The address out line cannot coincide with

any other control line leading to the outside.

2. The address out line is used to separate operations from the coupling unit. Together with the switched-off state of the output selection line, the address output line informs the I / O unit that is currently connected that it should switch off its input mode on line, which results in a disconnection from the coupling unit. The address output line remains energized until the input mode on line is switched off. The input mode on line 1629 must drop out within 6 microseconds of receiving the command to disconnect from the coupling unit. Any mechanical movement in progress will continue to a normal termination point. The status byte is excited and fed to the channel at the appropriate time.

Select output line

The select output line 1627 leads from the channel to the I / O control unit with the highest priority and from any I / O control unit to the next lower I / O control unit in the order of precedence. This line, together with the selection input line, forms a loop for scanning the connected I / O control units. An I / O controller can only energize its input run on line on the rise of its incoming select output signal. If an I / O controller does not need a selection, it must immediately pass the signal to the next controller. After an I / O controller has passed the select output signal, it cannot energize its input mode in line until the next energization of the incoming select output line.

When initiating an operation through the I / 0 channel the address output line must be energized at least 250 nanoseconds before the select output line will.

When the channel is about to scan the attached I / O controllers, the select output line coming out of the channel is normally / energized. The channel must keep the select output line energized until either the select input line or the address input line is energized. When the selection input line is energized, the selection output line must be switched off and must not be re-energized until the selection input line drops. When an I / O controller is selected, it energizes its input mode on line 1629. The select output line must stop routing in order for the input mode on line 1629 to be turned off. However, after the select output line is turned off, the I / O controller must hold the input mode on line energized until the current burst is complete. For group operation, the channel will keep the select output line energized, usually until the operation is complete. An energization of the incoming select output line in an I / O control unit indicates that the control unit can be selected for connection to the channel by energizing its input mode on line 1629. If a control unit energizes its input mode on line 1629 , it must suppress the forwarding of the selection output signal to the next control unit. If the I / O controller does not want a selection, it must immediately pass the selection output to the next controller.

Select input line

The select input line 1627 leads from the I / O controller with the lowest priority to the Channel. It is the exiting selection output line of the relevant control unit and is set up for the Select output signal a return path to the channel. The same applies to the selection input line Definition as for a select output line exiting any I / O control unit.

Entrance operation-on-line

The input operation on line 1629 leads from all connected I / O control units to the channel and has the purpose of notifying the channel that an I / O device has been selected. You must have all input lines on the I / O control line with the exception of the selection input line steer. Therefore, she must remain aroused for the duration of the selection. The selected I / O unit is identified by the address byte transmitted over the data input line.

The energization of the input mode on line indicates that an I / O device is in communication with the channel stands. This connection can consist of one or a combination of the following signal sequences: Reaction to address on data output line, request for data on data output line, offer of data on the data input line or offer of the status byte.

The input operation on line can only be energized if the one leading into the I / O control unit The select output line is energized and the select output line leading out is turned off. The entry-mode-on-line can only be switched off after switching off the selection output line.

Once the input mode on line has been energized for a particular signal sequence, it must remain energized until all necessary information has been transferred between the channel and the I / O unit. The input mode on line must be switched off at the time of energization of the outward control line associated with the transmission of the last information byte, or thereafter if the select output line is not energized. For clustered devices, the input mode on line 1629 can be turned off if the select output line is not energized, or it can be turned off upon receipt of the stop burst control signal.

The signals on the data input line and on the control lines leading to the inside are only from Meaning when the input operation on line is energized. If this line is not energized, the must Channel ignore all signals on these lines. On the other hand, every I / O control unit must Provide locking signals to ensure that they only have signals on the data input line and the control lines leading in when the input mode on line is energized.

Address input line

The address input line 1624 leads from all connected I / O control units to the channel and informs the channel when the address of the currently selected I / O unit is on the data input line

has arrived. The channel speaks by means of a command output signal on the address input signal.

The energization of the address input line indicates that the address of the currently selected I / O unit is available on the data input line. The address input line must remain energized until Excitation of the command output line 1622. The address input line must end its signal routing. so that the command output line can be switched off. The address input line cannot be excited at the same time as another control line leading inwards.

Command output line

The command output line 1622 leads from the channel to all connected I / O control units and informs the selected I / O unit that a signal is on the address input, the status input or the Entrance management is available. A signal on the command output line indicates the selected I / O unit that the channel has given a command byte on the data output line. The command byte has a fixed format.

The command output line must be energized after the channel may be on the data input line existing information is accepted and the command byte is transferred to the data output line has given. It indicates that the information on the data input line is no longer valid and also indicates that a command byte is available on the data output line. The command output line must remain energized until the assigned address input, Status input or input operating signal. It cannot be outwardly at the same time as another leading control line must be excited.

If the command output line on the address input signal during an initial selection sequence responds, the command byte contains the executing operation command. To each other Time means the occurrence of the command output signal on the address input signal »Continue working«. The excitation of the command output line to the excitation of the input management line hin always means "stop". When the command output line responds to the status input signal energized, it means "stacking" and this indicates that the I / O controller has passed its interrupt conditions is to be maintained and to offer it again if the command output line drops out, if the Select output line still energized and the suppression output line is off or as soon as it can reach a selection when the suppression output line is switched off.

Status input line

The status input line 1625 leads from all connected I / O control units to the channel and informs the channel when the selected I / O unit has given status information on the data input line has. The status byte has a fixed format and contains bits that indicate the current status of the Describe the I / O control unit. The channel then generates the status byte has accepted or not, either an output operation signal or a command output signal.

The energization of the status input line 1625 indicates that a byte of status information is on the data input line is available (for misalignment, see description of the data input line). The status input line cannot be excited at the same time as another control line leading inwards. She must remain energized until the output line or the command output line is energized. She must be hers End signal routing so that the corresponding control line leading to the outside is switched off can.

Exit management

The output service line 1623 leads from the channel to all connected I / O control units and shares the selected I / O unit recognizes a signal on the input service line or the status input line With. A signal on the outbound service line tells the selected I / O that the Channel accepts the information on the data input line or accepts the information on the data output line has provided the data requested by the input operating signal.

When the output operation signal in response to the input operation signal during reading, backward reading or sensing or sent on the ^ status input signal, the output operation signal increase after the channel accepts the information on the data-in line. In In these cases, the excitation of the outbound management indicates that the information is no longer valid the data input line and that they do not have any information on the data output line assigned. When the output operation signal in response to the input operation signal during a Write or control operation is sent, the energization of the output service line indicates that the Channel has made the requested information available on the data output line. In this In this case, the signal must rise after the information has been transmitted on the data output line are (misalignment, see description of the data output line). The information on the data output line are always of the type requested by the input operate signal, and they will used in the course of performing the current operation. The output management line must be energized remain until the assigned input operation or status input signal drops out. she can not be excited at the same time as another control line leading to the outside.

When upon the energization of the status input line and during energization of the suppression output line the output service line is energized, this indicates to the I / O controller that the operation is chained. Further details are from the description of the suppression output line too remove.

Entrance management

The input service line 1626 leads from all connected I / O control units to the channel and notifies the channel when the selected I / O unit is about to transmit or receive a byte of information wishes. The nature of the information associated with the input operating signal depends on the Operation and the I / O unit. In response to the input operating signal, the channel must either be an output operating or generate a command output signal.

709 611/411

In the course of reading, backward reading and sensing operations, the input management is annoyed when Information is available on the data input line (for misalignment, see description of the Data input line). During write and control operations, the input service line is energized, when information is required on the data output line. She can't be at the same time as one other control line running inwards. The input management line must remain energized until to excite the output operation signal or the command output signal, depending on which of these Occurs first. It can only be switched off after one of these signals has appeared.

If, in the case of cyclic I / O units, the Channel not responded to the previous input operating signal in good time and something like that Has generated an overflow condition, the I / O unit must recognize this condition. In any case, the Incoming service line does not terminate its signaling unless the output service line is energized and it must not be energized unless the output service line has been turned off (see signal locking).

In the event of an "overflow" condition, the data check indicator and the "overflow" indicator are switched on. Whether the data transfers should stop or continue after an "overflow" condition is determined intended for each type of I / O unit in the functional instructions for that unit. for cyclic I / O units. must be the maximum allowable time interval between energization of the input service line and energizing the corresponding output operation or command output line be considered.

For I / O units with buffering, where the data speed can be set without »overflow«, a further restriction is imposed on incoming management. With such units, the Input service line can only be energized when the suppression output line is turned off. (For a more detailed definition, see the description of the suppression output line.)

Suppression output line

45

The suppression output line 1630 leads from the channel to all connected I / O control units and is used both alone and in conjunction with the control lines leading out to perform the following special functions:

1. Suppression of status information: When the suppression output line 1630 is energized, attention or status information previously stacked in an I / O control unit (energizing command output line upon energization of the status input line) is suppressed and no further attempt is made undertaken to present the status information to the channel while the suppression output line is energized. If the suppression output line is energized after the start of a status cycle, the status cycle signal sequence will proceed normally regardless of the suppression output signal.

2. Suppression of data transfer: For non-cyclic I / O units (e.g. units with buffering) that can wait for data transfers without "overflow", the input service line cannot be energized if the suppression output line 1630 is energized. I / O units that can "overflow" ignore the suppression output signal during data transfers. The suppression output line must be energized 100 nanoseconds before the previous output operation control signal falls in order to surely suppress later data.

3. Control of chained commands: If the suppression output line 1630 is energized when the output service line 1623 responds to the status input line, a chained command is displayed. If the suppression output line is energized for a "unit vacated" status byte, it will only indicate the daisy chain until the suppression output line is turned off or a new selection is made. The suppression output line must be energized 100 nanoseconds before the output service line responds.

Depending on the I / O unit, the operation, and the configuration, the display may require chained Commands a specific function control at the level of the I / 0 control unit. -

If a concatenation is displayed in the completion status ("unit released" signal pending) on a Γ / 0 control unit with several I / 0 units, the selected I / O unit must next have its "unit released" status byte if the I / O control unit is not addressed in the meantime. The suppression output line must be energized at least 100 nanoseconds before the output service line responds and must remain energized until at least the input service line is turned off. "

If a daisy chain is displayed on an I / O unit that has more than one I / O control unit or more than is common to a channel, the I / O unit must remain available until the chaining operation is initiated has been or the concatenation is no longer displayed.

4. Optional reset: If the suppression output line 1630 is energized when the output mode on line is switched off, only the I / O unit that is operating on the coupling unit is reset (see section Output mode on line). For this signal sequence, the suppression output line must be energized at least 250 nanoseconds before the output mode on line is switched off and must remain energized for at least 250 nanoseconds after the output mode on line is energized (for more information, see section Output mode on line) .

Clock output line

The clock output line 163Γ is only used between the central processing unit and an intermediate unit or between an intermediate unit and a downstream intermediate unit. It carries the signal which indicates when the central processing unit is stopped or waiting, and thus when the intermediate unit is allowed to change over from the switched-on to the switched-off state or vice versa.

Incoming timing line

The input timing line 1620 is only used between the central processing unit and an intermediate unit or between an intermediate unit and a

downstream intermediate unit used. Your signal is passed through to a timing device in the central processing unit, and causes this time measuring device to register the elapsed time, even if the central processing unit is stopped or waiting.

Exit timing line

The output timing line 1610 leads to all units and devices around their timing equipment to get up and running. The signal is always present when the client time measuring device the central processing unit is running.

Direct addressing of I / 0 units

The method for addressing I / O units described below applies to all of them directly addressable I / O control units and I / O units that are connected via the I / O coupling unit. The method of addressing via the I / O coupling unit is relatively independent of that of the central one Processing units used I / O channel selection scheme.

For direct addressing of connected I / 0 units An address byte consisting of eight bits (plus parity bit) is used via the I / O coupling unit. It should be mentioned here that the "access path" of each I / O unit at the time of the installation of I / O control units a specific I / O unit address consisting of eight bits is assigned. The expression "Access path" is used here because a particular I / O unit has more than one path in some Systems or more than one device with indirect addressing via the same Path can be reached.

I / O control units must have I / O unit addresses can be recognized according to the following rules:

All units connected to this channel must adhere to this format. The basic version of the channel provides only 32 unit addresses and therefore the above addressing scheme is used for this version

further expanded to the addresses 000 ΧΧΧΧοάζτ 10 XX ΥΥΫΥ .

The aforementioned limitation is a result of the need to keep a current record of the operation in progress for each operating unit. When an I / O unit requests service, its record is transmitted to the components of the channel, evaluated, updated and stored again after the required operation has been completed. These records are called unit control words and consist of 64 bits in eight adjacent byte locations in a part of the main memory 2204 (not specifically shown), the so-called ί / CW memory. The system provides 256 byte storage locations in the ί / CW memory. This results in 256: 8 = 32 unit control words (UCWs) in the basic multiplex channel.

In the case of multiplex channel operation, the central processing unit and the read-only memory 150 used to execute the multiplex function whenever an I / O unit requests service or when the channel needs to perform some control function. It actually becomes the central processing unit converted to the multiplex channel to perform the requested function and after it Degree returned to its original role. As a microprogram control of components the central processing unit for the function of the central processing unit exists and is flexible, very little additional effort is required to effect the channel function. the additional components are:

(1) I / O unit addresses must have the correct parity to have;

(2) I / O unit addresses become control units one by one allocated with several I / O units;

(3) Control units with only one I / O unit address any I / O unit address from 0 to 255 can be assigned;

(4) I / O unit addresses for I / O control units with multiple I / O units always begin with an address limit as has already been defined (Example: a control unit with two access paths to I / O units can have any starting I / O unit address which contains a zero in the lowest bit position);

(5) I / O control units may no longer have I / O unit addresses recognize when they are assigned for processing (example: a control unit that is used for If it is designed to handle ten I / O unit access paths, the addresses OOOO to 1001 in recognize the four lowest bit positions, however, the addresses 1010 to 1111 must be in these four Reject bit positions);

(6) I / O control units with more than sixteen I / O unit addresses can be designed to recognize addresses in multiples of sixteen.

Multiplex channel

The multiplex channel processes I / O units with the addresses (8 bits) 0 XXXXXXX or 10 XX YYYY, where X and Y can be any binary value.

1. An outwardly directed data path 2310 from the i? Register 139 (FIG. 2c) to the data output lines 1600 to 1609 (FIG. 3a) of the coupling unit for eight data bits + parity bits.

2. An inwardly directed data path 2312 ' from the data input lines 1611 to 1619 (FIG. 3a) of the coupling unit to the A register 130 (FIG. 2c) for eight data bits + parity bits.

3. A further inward data path 2312 which runs from a few selected lines in the channel comprising the four inward switching unit identifier control lines to the Α register (eight lines total, no parity line).

4. Two locking registers 2300, 2304 ( Fig. 3b) which, under the control of the read-only memory 150 , can be set to states which are indicated by the bits at the output of the "^" field.

5. A coupling unit interrogation circuit 2301, which acts as a transit time oscillator

6. A parity check circuit on the data input lines of the coupling unit

These facilities are shown in Fig.3a and 3b.

General description of the »Start I / O« command for the multiplex channel

If the central processing unit responds to an "I / O start" command in the command stream of the monitor program

gramms, the following steps take place one after the other:

"Start I / O" command

Bit positions:
/ 8th

/ 16

OP unit
Addr. B. O

The unit address bits of the "start I / O" command are examined and it is determined that the unit address is one of those contained in the multiplex channel (either 0 XXX XXXX or 10 XX YYYY). , ₅

The address of the corresponding unit control word in the i / CW memory built up.

Unit control word
/ 8/8/16/16 /

16

status
OS Code
& lOP

25th

The status byte and the identification and operation code byte of this unit control word are then examined in order to determine the availability of the addressed unit. If there is no indication that the unit is currently in use, the channel command word is accessed at the memory location specified in the "Start I / O" command. This address is that of the Op byte of the channel command to be executed, and this Qp byte is transmitted (every eight bits) via the data output line 1601 to 1609 of the coupling unit to the selected unit in a sequence of control signals and response signals via the coupling unit.

Channel command
/ 8/4/20/8/24 /

OP counter Code Data Addr.

45

Upon completion of this selection sequence, the channel is able to choose from the response signals to the unit determine whether there are any improper conditions that may indicate the initiation of the required operation impede. If not, it begins to assign a 64-bit unit control word for the unit generate and save.

Unit ^ control word
Bit positions:
/ 8/8/16/16 /

16

status
OS Code
& OP counter Data
Addr. New
CCW Addr.

55

60

The unit control word is stored in eight consecutive byte storage locations in the UCW TeW of memory 2204 , starting with a storage location whose three lowest address bits are equal to zero (called double word boundaries). All bytes of a single unit control word are therefore contained in eight byte blocks of the t / CW memory, the five (of eight) address bits of which are the same in the highest places. Bytes are selected from a single unit control word by appending the correct three lowest "byte address" bits to these five "base address" bits in order to select the desired part of the unit control word.

During the creation and storage of a unit control word, the status byte of the unit control word is set to zeros, the CCW Op byte and the identification byte are merged and saved as UCW Op byte , and the three counting, data address and » Next command address fields are extracted and placed in the corresponding memory locations in the t / CW memory 2204 . Since these latter three fields are shorter than the CCW and "I / 0 -startw" fields, the "I / 0 -start" execution microcontrol word checks that there are no count or address bits of importance above the sixteen lowest bits.

Every error detected by the microprogram during the half of the execution of the "I / O start" command is registered by setting the status bits of the active program command. If such an error is detected, the I / 0 operation is not carried out and the program continues to the next CPU instruction, which is always a "check status register" instruction. If no errors are found, the status register is set to zero and the operation is initiated by the addressed I / O unit. The program then advances to the next instruction while the I / O unit begins its work.

In principle, the same sequence of operations takes place for an "I / O start" command, its unit address byte specifies an I / 0 unit of the selector channel. The only difference is that instead of the Checking and loading of a unit control word the »I / 0 -startw-microprogram the elements of the selector channel checks and loads, which serves the same purpose as a unit control word.

Program command »Start I / O« for multiplex channel

The multiplexing operation will now be described below with reference to FIG. 2a, 2b and 2c as well as 3a and 3b im individually explained.

The instruction bytes selected by the instruction counter ZZ register 134, 135 , which contains the address of the next 8-bit instruction byte in sequence, are labeled // 1, // 2, // 3, etc.

In the first step XABAO of the operation, the address in the // register 134, 135 (FIG. 2b) is transferred to the M / V register 137, 138 and the / register 135 is advanced. In the second step XACAO , the address memory location contained in the MTV register 137, 138 is introduced into the /? Register 139 (FIG. 2c), regenerated again in the memory (FIG. 2b), by the ALU unit 699 for Z-bus passed on and transferred to G-register 133 (Fig.2b). The information byte is now back in the memory, namely in the R register 139 and in the G register 133. The microinstruction then selects step XADA .

In steps XADA and XAEA 8, another memory circulation is carried out, and the 8-bit byte from the relevant memory location is linked to the previous content of the L register after ORing

stored in L register 136 (Fig. 2c). This step is done to correct the address (or immediate operand) under the control of an "execute operation," which will be specifically described.

In the next two memory cycles XFCAO and XFDA , the next byte is transferred to the A register 139 (FIG. 2c), and its four highest bits are added to the number 000 0011 and the result is transferred to the T register 141 (FIG 2b) entered. When the four most significant bits of the adder output information are 0, the S 4 latch is turned on. When the four most significant bits of the adder output information are 0, the S 4 latch is turned off. This step is used to determine the next microstep which could contain the addition of the contents of the selected general-purpose register to the partial address in one operation. Next, the XFEA microinstruction is selected.

In this step XFEA , the four lower-order bits in the Ä register 139 (7/3) become the (/ register 142 (FIG. 2a) and the contents of the // address register 134, 135 become the MN register 137, 138 transfer.

In steps XFFA through XFGA 2 (page 1403) the / register 135 is advanced and the carry latch circuit in the ALU unit 699 (FIG. 2c) is switched on. In this step the // 4 byte is transferred from the /? Register 139 to the V register 143 (FIG. 2b). In the next step XFHDO (page 1403) the content of the / register 134 is added to 0, the content of the previously set carry latch circuit is also added to the content of the / register 134 , and the results are again transferred to the / register, with any output carry is set in the carry controls of the ALU unit 699 (FIG. 2c). This step advances the / register.

The command parts for this operation have now been decrypted and the results have been entered into the corresponding registers in the central processing unit as follows: The OP code is in G register 133 (FIG. 2b), the unit address of the I / The 0 unit is in the L register 136 (FIG. 2c), the four higher-order bits of // 3 are in the T-register 141 (FIG. 2b), the four lower-order bits of // 3 are in t / Address register 142 and the // 4 byte is in the V address register 143 as follows:

The lower-order bits have the following meaning with regard to the bit position:

Byte address bit position

11th 24-31 10 16-23 01 8-15 00 0-7

IGI

ITI

UV

OP 8 Unit add. 8th 4th 4 channel control 8

50

The i / V address register 142, 143 (Fig. 2b) contains the address of the channel control word. The four bits stored in the T register are not used for an "I / O start" operation, and in the microcontroller step XF] F the four higher-order bits of the L register 136 are added to 0000 0011, and the result is forcibly entered into the T-Register 141 introduced.

As previously discussed, the present system has a memory called CPU which may be part of memory 2204 and which contains a plurality of general purpose registers totaling four bytes or 32 bits. When addressing a general purpose register, an additional set of lower-order bits is used to select the byte to be read in the particular memory circulation.

The low-digit byte address contains the most significant digits. This step, which is necessary in the present operation, also eliminates unnecessary information. Based on the state of the latch circuits G 4, G 5 and G 6, which are set in accordance with the operation code, the step QABAO is selected as the next microinstruction.

In this step, the number 1000 1000 is forcibly entered in the T register. In the decimal system this means the number 88. This memory location in the CPtZ memory part is called »external mask«. Due to the status of 52 (not zero), a branch is made to step QACAO.

The V register 143 (FIG. 2b) is now checked using the I constants 0000 0111. During this check, the content of the V register is linked to the "mask" in an AND form. This will check whether. Bits are in the lowest three digits of the V register. These bits are available for a double word limit. The latch circuit S 2 is switched off when the adder output information does not consist of all zeros. The address in the T register 141 is now transferred to the M / V register 137, 138 , and a branch is made to step QADA.

In this step, the contents of the R register 139 (FIG. 20) are crossed over and then checked using the mask information 0001 0000. As a result, the bit position B1 in the “external mask” is checked for interruption priority from external signals. The next step is QAEA.

The address in the t / V address register 142, 143 is transferred to the MN address register 137, 138 (FIG. 2b) and the V register is advanced. The next step is QAFC3.

In this step the first byte of the CCWin is brought into the /? Register 139 . In this same cycle, this op code contained in the Α register is transferred to the D register 132 (FIG. 2b) by step PACCX.

The address K 09 is forcibly set in the MN address register 137, 138 , and the content of the / register 134 is transferred to the /? Register 139 by step PADB . The information extracted from the memory is disregarded and the contents of the / register now in memory are stored in this memory location. The next step is PAEB.

The address K 10 is forcibly entered in the M / V register, and the contents of the / register 135 are transferred to the /? Register 139 . The byte at address K 10 is transferred to the /? Register 139 (FIG. 2c), but is disregarded, and the contents of the / register are entered into storage location K 10.

In steps PAGB and PAHB , the CPty memory location K 12 is cleared, and the four higher-order bits of the op-code in addition to the

709 611/411

Constants 0001 in the lower digits are introduced into the CPtZ memory location K 12. This memory location is called Syllable Counting, PSW-Bh. The 1 in bit number 7 indicates that the // content is stored in the CP / T memory section, and the two higher-order bits of the opcode indicate the length of the stored command.

The next microprogram memory cycle PACC3 checks the L register 136, which contains the unit address, using the mask constant 1000 0000. The status latch circuit 54 is switched on if all four higher-order bits of the addition contents are zeros. This checks the unit address for the presence of a one in the highest digit. This test in connection with the next microprogram steps PACF to PAFDi examines both the highest and the second highest bit of the address for the presence of zeros or ones. These checks are necessary to indicate a multiplex operation with one I / 0 unit per I / 0 control unit represented by a 0 in the highest digit) or a multiplex operation with several I / 0 units per I / 0 control unit (represented by a 1 in the highest digit and a 0 in the second highest digit). An 11 in the two highest bit positions represents a selector channel unit address.

The op-code for the channel command word is now saved in the £> register 132. The content of the // - register has been saved in the CPCZ memory part, the four higher-order bits of the opcode have been stored in the PSW syllable count field, and the The address of the I / 0 unit to be selected has been checked for the type of operation to be carried out.

Now the address of the unit control word is determined from the specified unit address.

It is assumed that the previous tests performed by masking the byte in the L register have determined that the unit address is one of the first sixteen unit control words is in the t / CW storage part.

Step QAFD 1 controls the machine so that the four lowest bits of the L register 136 are added to 0000 0001 after crossing over to the higher digits and the result is entered in the T register 141 (FIG. 2b).

In steps QABFO and QACF, a byte is read out from the i / CW memory section addressed by the T register. The 5 register is cleared and the byte at the relevant memory location is transferred to the /? Register.

In step QACF, the content of the Α register is added to 0 and, as a result, a test can be made to see if its content is equal to 0. Since a "1" was added in step PAFDi , byte no. 2 is selected from the unit control word. This is the identification and op code byte. If the I / 0 unit is not occupied, ie, when it has completed its previous operation, the label field and the op-code are 0. A detailed explanation of the label and code unit in the multiplex operation is given later, where is on refer to the general description of this feature for input-output operations.

The constant 00001 is set in the / M coupling unit register 2300 (FIG. 3a) (step QADF). The fT bus receives signals for a mask 0010 0000 in step QAE] 1.

In the QAFF cycle , the value in the register is increased and the result is entered in the Α register. This roundabout branches off to 00000 to form a loop that causes a delay of about 500 nanoseconds to enable polling control and which branches off to increment the CCW address in T register 141 and the result can be brought back into the T register.

ίο In step AQGFO a byte is taken from the CPtZ memory location Ki5 by entering this address into the M / V address register. In the same step, the content of the L register is transferred to the /? Register.

In the next step QAAF , the information from the memory is checked and the information is stored in the /? Register in the memory location KiS. The value in the T register is increased and shows a £ / CW number 3.

The address of the second byte of the channel control value CCW is contained in the i / V address register. In step QBDB this address is transferred to the MN address register and the number 00001111 is subtracted from the four lowest bits of the D register. This serves

to check the D register, which contains the 3rd op code that is used in step QBEB . This is described below.

The second byte of the CCW is entered in the /? Register and the memory is regenerated. The ^ register is advanced by 01000 in preparation for the address of the sixth byte in the CCW. Based on the examination of the D register discussed above, the microinstruction word QBFBO is selected. The sixth byte of the CCW is addressed by transferring the address in the UV register to the MTV register. The Α register, which contains the second byte, is added to 0, and the output information of the adder is checked and the S 2 latches are switched on if they are not all zeros.

The next step is QBGB. The sixth byte is entered from memory into the /? Register and its contents are added to 0 to perform the same test as described above. The next step is QBHB.

The content of the L register is transferred to the /? Register, and in step QBJB , the ΡΛ coupling unit register 2300 is set using a constant 10001. As a result, the address previously contained in the L register 136 is output via the data output lines 1601 to 1609 (FIG. 3a) and the query control 2301 is switched on

In step QBKB , the / M coupling unit register 2300 is set using the constants 11001. This will again generate the address and turn on the polling control, and also energize the address output line 1621.

In the next step QBLB the register 2300 is set using the constant 11000, whereby the data output lines and the address output lines are energized, and next step QBKC is selected in which the L register is cleared and the carry latch is switched off. In step SBLB it was intended to keep the data output control line 2302 and the address output line 1621 energized, but to turn off the polling control 2301.

In step QCBB , the / T register is under

Checked using mask 0010 0010 with the first 0 indicating the status of the query control interlock circuit 2301 and the status of the inbound service on line 1629 (Fig. 3a). When the input operation-on-line 1629 is energized, 54 is reset. When the polling controller 2301 is on, will 55 reset.

The QCCBO step follows. The PA coupling unit register 2300 is now set using the constants 1101. The purpose of this is to bring the address of the I / 0 unit to the data output lines 1601 to 1609 and to excite the address output line 1621 and to switch the interrogation controller 2301 on again.

QCCBO was selected because neither S4 nor 55 was on in the previous control word during the marking operation. This indicated that polling controller 2301 was off and that input mode on line 1629 was energized. In step QCDH2 , the PA register 2300 is set using the constant 0001. This disconnects all control lines from the PA register 2300, which is called the selection output.

The PT output lines have been tested using the 10,000,000 mask. The purpose of this mask is to determine whether the control lines have a signal on the address input line 1624. If the address input line 1624 is not energized, the next microinstruction QCFDO transfers the contents of the L register 136 'to the λ register 139 and the carry latch is turned on. This loop forms for up to 500 nanoseconds, during which time the address input line is energized to cause a branch.

The branch to QCCDO now takes place, and in this step the content of the λ register is subtracted from that of the P / register 562 (FIG. 2c) with a forced input carry. The purpose of this is to compare the address of the I / 0 unit on the data input lines 1611 to 1619 (FIG. 3a) with the address stored in the /? Register 139. If there is a match, step QCHD is selected next. In this step, the contents of the i> register 132 are transferred to the Ä register 139 in order to route the op or command output instruction to the I / 0 unit.

The PA coupling unit register is set in step QCKD using the constant 10101. This is intended to keep the data output control line 2302 and the interrogation controller 2301 in the switched-on state and also to energize the command output line 1622. Step QCJBO is now selected.

In this step the PT register is checked using mask 1000 0000. The exam is directed to address input line 1624. A branch is made in this microprogram step set up in the program loop, as a result of which a time of around 500 nanoseconds can elapse, during which the address input line 1624 turns off and a branch to the next Program step effected. If the address input line does not arrive within this delay of 500 Nanoseconds is turned off, the branch continues to a "stop I / O" operation.

Assume that address input line 1624 is actually turned off before the end of the delay time. If this is the case, the command output line 1622 would have to be switched off by the microprogram step QCJB 1. This is done by setting the PA coupling unit register 2300 using the constant 00000. This switches off all output identification control lines. The PT output is checked by QDEBi using the 00000001 mask. This check applies to the status input line 1625 (FIG. 3a).

A similar delay loop of about 500 nanoseconds is now initiated, during which the status input line 1625 would have to be energized. When the status input line is energized, the next program step QDEBO transfers zeros to the P / lines. This checks the information (status byte) on the data input line 1611 to 1619 for all zeros. If the status byte of the I / 0 unit has found all zeros, the next steps will decrease the value of the V register 143 (Fig. 2b), the results will be placed in the V register, and a byte will go out read out the main memory under the addressing by UV; then the value of the V register is decreased again and placed in the V register. In the next step QDHB , the register'139 is checked using the mask 00000111. The latch circuit 52 is switched on if the adder output does not consist of all zeros. In this step there is a check for zeros in the low digits of the fifth identifier byte of the CCW (FIG. 4). If it is then determined that the I / 0 unit is not busy (i.e. the I / 0 unit status byte and CCW flags = 0) and that it is ready to begin an I / 0 operation, that runs Program QDHC to QEHB accordingly. The unit control word is brought up to date by transferring the count byte and the start address bytes from the channel control word CCW to the corresponding positions in the UCW , but before this operation is completed, the operation of the coupling unit is restarted. The PA switch register 2300 is set using the constant 00010, which energizes the output service line 1623 via the switch line. The PT output is checked using the 00000001 mask. This is done as before, that is, the 500 nanosecond loop gives the status input line time to shut down before continuing.

In the next microprogram steps QEKBX to QFLGO, the information is passed from the channel control word CCW (FIG. 4) into the unit control word UCW in order to complete the 64 bits of the unit control word. This also includes several steps in which the contents of the [/ V register are stored in the f / CW memory section in order to form the next CCW address.

The PT output is checked with the 00000010 mask. This becomes the state of the input operation on line 1629 detected If this line is disconnected, the PA coupler register 2300 is set using the constant 00000. This will make all output tag control lines switched off, and the preliminary selection of the I / O unit is now complete.

The next microprogram steps QFHE to AGJD return the central processing unit to its previous state by using the

Information from the CPtZ memory locations K 09 and K 10 into the / and / registers (FIG. 2b) and the Qp code from K 12 into the G register (FIG. 2b). The central processing unit has now been reset to the same point in the microprogram flow from which the "start I / O" program began.

Channel command word

The channel command word CCW specifies the command to be executed, any memory operation assigned to the command and the measures to be taken after the command has been completed. Channel command words can reside anywhere in main memory 2204, and a "start I / O" command can have more than one assigned to it. The channel accesses a channel command word in the main memory only once, whereupon the associated information is stored in the channel. The first channel command word is fetched during the execution of the "Start I / O" command. Each additional channel command word in the chain is extracted when the operation has reached the point where it is needed.

The CCW format is shown in FIG. 4 shown.

The fields in the channel command word are assigned to the following purposes:

Command code:

Bits 0 to 7 indicate the operation to be performed.
Count:

Bits 12 through 32 designate the number of 8-bit byte storage locations in the memory area.

Chain data address of CDA ^ identification:

Bit 32, if present, directs the concatenation of data addresses. It does that the memory operation defined by the next channel command word during the current operation is used. When this bit is a zero, the current control word is the last one for the operation.

Chain command (CQ identification: Bit 33, when it is a one and when the CDA flag is off, arranges the Chaining of commands. It does that with the next channel command word specified command is initiated upon normal completion of the current operation. When this bit is a zero or if the CDA flag is on, indicates the next Channel command word does not issue a new command.

»Suppression of incorrect length display« (S / L / ^ - identification:

Bit 34 monitors whether the program is informed of the wrong length or not. If this bit is a one and the CDA flag is switched off in the last channel control word used, the incorrect length display is suppressed. If the CC indicator is activated in the channel control word, commands are chained. The absence of the S / L / flag or the presence of both the SILI and CDA flags causes the program to be notified of the wrong length.

35

40

45

55 Spring license plate:

Bit 35, when it is a one, suppresses the transfer of information to the memory during a read, backward read, or sample operation. If this bit is a zero, the Operation normal.

Program-controlled interruption
(PC / j identification:

When bit 36 is a one, it causes the channel to run the program after taking the channel control word to interrupt. If the bit is a zero, the operation is normal.

Data address:

Bits 40 to 64 designate the storage location of an 8-bit byte in main memory. this is the first memory location that is accessed, in the memory area.

Bit positions 37 to 39 of each channel control word, with the exception of one which relates to a transmission in the channel, must contain zeros. If this restriction is not adhered to, the program test status arises. If the first designated channel control word does not contain the necessary zeros, the I / O operation is not initiated and the status bit of the CSW is stored during the execution of the "Start I / O" command. If this state is detected during the data address chaining, the I / O unit is informed by a signal that it should terminate the operation. If the absence of these zeros is detected during command chaining, the new operation is not initiated and an interrupt condition is generated on the I / O unit.

The content of bit positions 40 to 47 of the channel control word is not taken into account.

Command code

The command code in the channel control word tells the channel and the I / O unit which operation is to be carried out.

The two least significant bits or, if these bits are 00, the four least significant bits of the Command codes identify the operation for the channel. The channel distinguishes between four operations:

Forward output (write-control),
Input forward (reading, sensing),
Input backwards (read backwards),
Branch (transmission in the channel).

The channel ignores the higher-order bits of the command code.

Commands which initiate I / 0 operations (Writing, reading, backward reading, control and sensing), cause the transmission of all eight bits of the Command codes for the I / O unit. The higher bit positions in these command codes contain modification bits. The modification bits tell the I / O unit how the command is to be executed in detail. You can have the I / O unit do a comparison on the data received during a write operation, and also include states such as B. Recording density and parity. The modification bits give the control command

control function to be performed. The exact meaning of the modification bits depends on the type of I / O unit.

The command codes have the following meaning:

# # * * 0 0 0 0 Invalid Code M. M. M. M. 0 1 0 0 Feel * * * * 1 0 0 0 Transmission in the channel M. M. M. M. 1 1 0 0 Reading backwards M. M. M. M. M. M. 0 1 To write M. M. M. M. M. M. 1 0 Read M. M. M. M. M. M. 1 1 steer (* = Bit position ignored. M. = Modification bit.)

Whenever the channel detects the invalid code while a command is being initiated, the program test status is generated. If the first specified channel control word contains an invalid command code, the status bit of the CSW is saved during the execution of the »Start I / O« command. If the invalid code is encountered during command chaining, the new operation is not initiated and an interrupt condition is generated. The command code is not taken into account during the data address chaining.

Definitioji of the storage area

The area in the Main memory is defined by channel control words. A channel control word defines an area by using it the address of the first 8-bit byte to be transmitted and the number of 8-bit bytes contained in the area indicates. The address of the first byte appears in the data address field of the channel control word. The number of Bytes contained in the memory area are specified in the count field.

In the case of write, read, control and sampling operations, memory locations are in ascending order of the Addresses used. When information is transferred to or from the main memory, the The content of the address field is increased step by step and the content of the count field is decreased step by step. at of the backward read operation, data is stored in descending order of address, and both the The count as well as the address are gradually reduced. If in any operation the count reaches the value zero, the memory area defined by the channel control word is exhausted.

Each memory location provided in the system can be used for transferring data to or from a I / O unit can be used provided that the memory location is not protected. The channel control words can also be stored in any part of the available main memory can be specified. When the channel tries to save data to a protected location, the protection test condition is generated and a signal instructs the I / O unit to cease operation break up.

If the channel detects a memory location that is not intended in the system, the program test state is generated. If this condition occurs because the first specified channel control word contains a data address which is too small for the relevant system type, the I / O operation will not be initiated and the status request of the CSW will start while the »I / O is being executed «Command saved. Attempts to transfer data to or from a nonexistent memory location and the detection of an invalid CCW address during data address chaining are reported to the program with the interrupt status at the end of the operation. In both cases, the I / O unit is instructed by a signal to terminate the operation when the states are determined. If an invalid address is found during command chaining, the new operation is not initiated and an interrupt status is generated.

Concatenation

When the channel has carried out the information transfer specified by a channel control word, he can continue the activity initiated by the "I / O start" command by saving a new one Channel control word. Fetching a new channel control word after the previous one has been exhausted referred to as concatenation, and the channel control words belonging to such a sequence are used. as Referred to as "chained".

Concatenation usually takes place ntfr between channel control words that are in consecutive Double word storage locations are located. It progresses in ascending order of addresses; d. i.e., the address of the new channel control word is obtained by adding 8 to the address of the previous channel control word is added. Two chains of channel control words located in spatially separated memory areas can be linked for the purpose of chaining by means of the transmission in the channel command.

All channel control words in a chain relate to those specified in the original "Start I / O" command I / O unit.

There are two types of concatenation: the concatenation of data addresses and the concatenation of commands. It is controlled by the data address concatenation (CDS) and command concatenation fCQ identifier in the channel control word. These indicators identify the measures that the channel should take after the current channel control word has been exhausted. The following code is used:

CDA

CC

measures

O 1 1 O 1 1

No concatenation. The running CCW is the last. The operation is complete. When data is divided into blocks on the I / O unit, the beginning of the next block is set on the I / O unit

Command chaining

Data address chaining

Data address chaining

The setting of the CDA and CC indicators is effectively forwarded through the transmission in the channel command. If a "transfer in channel" command is fetched during the chaining, the following channel control word is used for the type of chaining specified in the channel control word that appeared before the "transfer in channel" command.

709 611/411

The CDA and CC identifiers are defined for channel control words that are assigned to all commands with the exception of "transmission in channel".

Data address chaining

During the data address chaining, the new channel control word fetched from the channel defines a new space for the original operation. The execution of the command on the I / O unit is not affected by this. The channel continues operation using the in the new channel control word defined memory area. The content of the command code field remains that of the new channel control word not taken into account, except when it designates a "transmission in the channel".

The data address chaining enables information to be rearranged when it is transmitted between main memory and an I / O unit. It also allows a block of information to be transmitted to or from spatially separated memory areas and is necessary for the jump operation.

If during a read, read back, or read operation of the program a data address concatenation prescribes a storage space in the data under the control of the preceding Channel control word have been stored, the channel takes the new content of the memory location. This applies to every piece of data that is under the control of the previous channel control word has been transmitted, including the last byte. The program can therefore make self-describing records use; d. i.e., it can concatenate into a channel control word that is under control of the previous channel control word has been read.

Command chaining

During command chaining, the new channel control word fetched from the channel gives a new one I / 0 operation on. If the I / O unit says »Unit free Done "signal, which indicates the completion of the current operation, the channel forwards the an operation designated the new channel control word. The normal completion of the previous I / O operation does not generate any break conditions. The new command applies for operations with data transfer always towards the next block.

The chaining of commands only takes place and the new operation is only initiated if no unusual conditions were detected in the previous operation. When a condition such as B. data check, incorrect length or exceptional condition has occurred, the sequence of operations is terminated and a condition for the I / O interruption is generated. In this case, the new channel control word is not obtained. Due to the wrong length, the command chaining is not suppressed if both the CC and the S / LZ indicators are activated in the channel control word.

An exception to the sequential concatenation of channel control words occurs when the I / O unit issues the jump condition with the "unit released" signal. The combination of jumping and "unit cleared" bits when the CC flag is present causes the channel to use the channel control word fetch and concatenate whose address in main memory is 16 higher than that of the previous one Channel control word.

The chaining of commands enables the program to carry out the transmission in an advantageous manner initiate multiple data blocks with a single »start I / O« command. It also allows certain auxiliary functions with a single command, such as B. Winding the tape at the time of initiation the data transfer. The chain of commands in connection with the jumping condition allows the channel to modify the normal sequence of operations to respond to signals from the I / O unit.

Multiplex routine

The purpose of the multiplexing routine is to allow the central processing unit to execute a Continue the problem program until an already selected I / O device provides information to the computer has to send or is in a status to receive information from the computer. In this case the I / O unit notifies the channel in the computer,

that it is ready to receive or transmit data. This is done in the I / O unit Set their control request interlock circuit. When the computer has the output devices queries by sending an output selection signal over the control lines, the I / O unit ready to send the input operation on signal back to the computer on the shortly thereafter the address input signal follows. After saving the register contents in the problem program have been used, the computer responds to the address input signal with a command output signal on. Usually follows a command output signal from the I / O unit via the Channel the input operating signal to which the computer responds with the output operating signal. This follows normally that the I / O unit has the input mode on signal ends, which marks the end of a byte in multiplex mode.

A large number of microprogram cycles are necessary to prepare the central processing unit to take control of the channel and to work as an I / O control device. The first microprogram step RABB addresses the CPiZ memory location .KOO. The information contained in the Ä register is stored in the CPt / memory location # 00. The memory location KQ \ is addressed and the information in the T register is sent to the /? Register and then to the memory location KQ \ .
The CP £ / memory contains registers that are reserved for storing the various CPU registers. These are addressed by the CrtA memory locations 908, 909, 910, 911, 912, 913, 914 and 195. These are the / -, / -, S-, V-, U-, G-, B- or L register. A stream of microprograms from & 4G5 to RACHO successively addresses and stores the registers in the CP £ / memory in reverse order (ie the content of the L register goes to the L memory in the CPLZ memory, D to D, U 'to U , V to Fund Szum S-CPtZ-Speicherplatz 910). Storage locations 908 and 909 (registers / and J) are not used in this operation.

In the microprogram step RAHD , the content of the data input lines 1611 to 1619 (FIG. 3a) is transferred to the 5 register. This causes the address of the I / O unit (which was previously contained in the data input line) to enter the 5 register. Then the content of the 5 register is stored in the L register. The lowest four bits of the S register then become the

highest bits of the T register 141 transferred crosswise. This corrects the address in the T register which will ultimately address the unit control word by transferring the four low-order address bits of the relevant I / O unit to the highest-order bits of T-register 141 . This selects the general unit control word assigned to the relevant I / O unit.

The next microprogram step sets the multiplex interlock circuit 2509 (FIG. 3b) in the channel, which in turn energizes the query control 2301 (the select output line 1627) to the I / O unit. The unit control word is addressed from the Γ register 141 , which contains the address of the I / O unit in the higher digits, and the lower digits are reset to 0. This addresses the first byte or the status byte of the unit control word. The contents of the jT register are then incremented in preparation for addressing the second byte of the unit control word. The first byte of the unit control word is transferred to the S register 140 . The second byte of the unit control word, which contains the operation bit and the flags, is then transferred to the G register 133 . The second byte of the unit control word is checked under mask 00001000. This checks the PCV flag, that is, the program control interrupt flag.

The PT output is checked using the 00001000 mask. This checks the channel for the suppression interrupt signal on line 1630. Assuming that neither the interrupt suppression nor the PCZ interrupt lines are energized, normal multiplexing continues.

The PA register 2300 in the coupling unit is set using the constant 00101. As a result, the command output line 1622 and the interrogation control interlocking unit 2301 are switched on, which in turn excites the selection output line 1627 and the command output line 1622 via the coupling unit to the I / O unit.

The next circulation checks the PT output using the mask 10000000. In this way, the channel input lines for the presence of the signal on the address input line 1624 from the I / O unit to be tested for the content of the D register 132 is in the form of a loop in the D-registers transferred back adding a one each time to create the 500 microsecond delay which allows the address input line 1624 ample time to shut down under normal conditions. If the address input line 1624 does not turn off during this prescribed delay time, the machine branches to a stop condition. If, on the other hand, the address input line 1624 switches off within this time, the microprogram branches to the next step in which the PA register 2300 in the coupling unit is set using the constant 00001. This turns off the command output interlock circuit 1622 , but keeps the query control interlock circuit 2301 on. This corresponds to the specification for the coupling unit that when the address input line is switched off, the command output line is also switched off. The third byte from the unit control word is then entered into the Ä register 139 and checked for all zeros. The third byte of the unit control word is the count for the higher digits. If it is assumed that the higher digits contain all zeros, the fourth byte of the unit control word, which is a count for the lower digits, is extracted and checked for all zeros. This count tells the central processing unit how many more information bytes are still to be transmitted via the coupling unit. If this count is, the next cycle of microprogram checks the PT output using mask 00010001. This checks a channel coupling unit for signals on input service line 1626 and status input line 1625 . If both signals are present, this indicates an error. The excitation of the input service line 1626 indicates a normal intermediate step for the exchange of information. The sole excitation of the status input line 1625 shows. a termination procedure from the I / O unit, that is, this is the last step.

Assume that the input service line 1626 from the I / O unit is energized. In this explanation it is assumed that a read condition has been generated for the multiplex channel, ie that information from the I / O unit has been accepted and stored in the memory space designated by the data address in the main memory of the computer.

The next microprogram step decrypts the relevant op code or the command from the G register 133. After a branch caused by this decryption of the command, the next program section addresses and takes the fifth byte from the unit control word and saves this byte (the one higher Position of the data address is) in the i? Register 139, where it is checked for zeros. After checking for 0, the highest digit of the data address is transferred to the K register 143 . In the next microprogram step, the sixth byte of the unit control word is read out, entered into the λ register 139 and checked for zeros. This sixth byte is the lower digit of the data address. The data address from the unit control word specifies the memory location in the main memory into which the information byte from the I / 0 unit is placed.

In the next microprogram cycle, the sixth byte or the lower digit of the data address is transferred to the i / register 142 . The V and tZ registers now contain the complete data address or memory location in the main memory for the data of the I / O unit.

The next microprogram step sets the PS register 2304 in the coupling unit using the constant 01001, and this turns on the I / 0 data latch 2305 in the channel.

The next microprogram step RCJD 1 addresses the main memory from the register UV and transfers the information from the P / lines to the Ä register 139. This means a transfer from the data input lines 1611 to 1619 from the I / O unit to the Ä- Register, and this data is then stored in main memory in the location indicated by the data address from the unit control word. The next microprogram cycle causes the PA register 2300 to be set in the coupling unit with the aid of the constants 00011. As a result, the output mode interlocking circuit 1623 and the interrogation control interlocking circuit 2301 are switched on.

tet, and thereby in turn the signals on the output service line 1623 and the select output line 1627 generated to the I / O unit.

The next microprogram step turns off the I / O data latch circuit 2305. The following microprogram step RDDCO checks the / T output using the mask 00010000. This checks for the presence of a signal on the input service line 1626. In normal operation, the input service line 1626 must be turned off upon receipt of the signal on the output service line 1623 from the central processing unit. As before, a microprogram step is turned on to form a loop with a 500 nanosecond delay during which the input service line 1626 would have to be turned off. If this does not happen, there is a branch to "Stop" in the next microprogram step. If, on the other hand, the input service line 1626 switches off within the time allotted to it, the next program step checks the / T output using the mask 00000010. This checks the switching unit line of the I / 0 unit for the presence of the input mode on signal. The input service line 1629 should have been switched off together with the input service line 1626. When this has happened, the PA register 2300 in the coupling unit is set in the next microprogram step using the constant 00000. As a result, all the flag bits are switched off, ie the output service line 1623 and the selection output line 1627 are switched off. This completes the entire exchange of controls and information for a multiplex routine.

The next microprogram step causes the address of the unit control word the first byte is addressed again. This byte (the status byte) is transferred to the Ä register 139, bits 5,6 and 7 are cleared and the entire byte is entered into D register 132. Through the The next microprogram step is then the content of the 5-register 140 in OR form with that of the / ^ Register 132 and the result entered in the Α register 139 '. This takes the information which were previously contained in the S register (address of the I / 0 unit), transfers them to the assigned Bit positions in this ί / CW status byte and transmits the result in the Ä register. A transfer back to the unit control word now takes place from the i? Register 139 as status byte, d. i.e. after this operation The stored unit control word contains the address of the I / 0 unit in its status byte.

The next microprogram step checks the / T register using mask 01000000. This checks the channel for a signal on multiplex request line 2306. If there is no such request, the next operation will set the / ^ register 2304 on the coupling unit using the constants 01010. With this operation, the multiplex latch circuit 2303 is turned off. If, as before, it is assumed that there is no further request, that is, that the I / 0 unit has turned off the input mode-on line 1629, since it is a read operation, the computer will not address the I / 0 unit with respect to a second byte. In this case, the next step, REDC, starts the procedure for restoring the central processing unit to its previous status. The Γ register 141 is set to 10011010, which is a 910 address in CPtZ memory. This address is taken from the C / 'tZ memory, and the information stored there from the 5-register 140 before entering the multiplex routine is read out again and transferred to the 5-register 140 in the central processing unit. The corresponding information is also transferred to the V register 143, the i / register, the G register, the £> register and the L register. This is followed by the transfer of the content of the addressable memory location KQ \ into the T register 141. The content of the addressable / C memory location ATOO of the central processing unit is then entered into the register 139. Now the central processing unit has been completely restored to its previous state; all of the operational registers contain the information that was stored therein prior to entering the time division multiplex request. The computer now turns back to the main program stream, and the one-byte time division multiplex routine is ended.

Program command »Start I / O«
for selector channel operation

The first 27 microprogram words for the selector channel selection of the I / 0 unit are the same or, in the Case of the last few steps, similar to the preliminary selection in the multiplexing operation.

The first microprogram word XABA 0 addresses the main memory 2204 via the MV register from the // register 134, 135. The following microprogram word enters the information from the main memory into the G register 133. This is the op code.

The microprogram word XAEA9 saves the second byte in the “start I / O” command in the L register 136. The next two memory cycles or microprogram words XFCA 0 and XFDA add the next byte in the “start I / O” command to 0000 0011 and the result is introduced into the Γ register 141. The microgram word XFEA causes four low-order bits of the third byte to be entered into the {/ register 142. These processes are continued, as in the multiplexing operation, until the op code in the G register 133, the unit address in the L register 136 and the CCVV address are in the U and V registers 142, 143. Several cycles later, the microprogram word QABA 0 adds a 0 to the constant 10001000 with a forced input carry and the result is entered in the Γ register 141. As a result, an effective CP £ / address 88 (FIG. 39) gets into the Γ register 141 (FIG. 2c). The B register is now checked for the presence of 1 bits in the three lower bit positions. These must all contain a 0 and thus indicate a valid double word limit. The information in the CP £ / address 88 is transferred to the /? Register 139 ( FIG. 3c) in the next memory cycle QABA.

This information is now checked for the interruption process of external signals. The main memory is now addressed by the i / V registers 142 and 143, and in the next memory cycle QAFC3 the first byte or the op code of the channel control

word (CCW) in the Ä register 139 and in the Z> register 132 entered.

The contents of the / and / registers 194 and 135 are now entered in the CPtZ memory locations K 09 and K 10. The CPtZ storage location Ki 2 is deleted, and the four higher significant bits of the Qp-codes as well as a constant 0001 for the lower digits are input to the space K 12th This location is referred to as the Syllable Count PSV ^ bit. The 1 in bit 7 of the silver counting byte indicates that the content of the // register 194,135 is in the CPtZ memory. The bits in the two highest places of the Qp code indicate the length of the stored command. Several cycles later, the microprogram word PACCZ checks the L register 136, which contains a unit address, using the mask constant 1000 0000. A few more microprogram words PACF to PAFD 1 check the bits in the highest and second highest positions of the address for the presence of Zeros and ones out. These tests determine whether the instruction requires a multiplex operation or a selector operation. From here on the operations differ; that is, a selector channel operation now follows according to a routine which deviates from that according to which the multiplex channel operation would have been directed.

The presence of ones in the top two digits of the L register or the unit address indicates that a voter channel unit address is required. The following detailed description of the selector channel operation is made in connection with Figures 5a, 5b. Through the first microprogram word ZFBB the constant 010000 gets into the // ß-register 2287. This happens as follows: The HB = / ^ - line 568 enters the // B-block 2287 and allows the ET bus 2274, enter the constant in the register. This triggers the "time out" multivibrator, which emits its output signal for about 1 msec. This monostable multivibrator is included in the channel controls 2275.

The next microprogram word ZFGFi checks the // Γ register 2284 using a mask 00001000. As a result, the selector channel is scanned for the presence of the signal “channel or unit occupied”. The constant 00001 enters the HA register 2286 through the next microprogram word ZFDA 1. This is done through the line HA = K, 567, which enters the block HA 2286 and allows the / C bus 2274 to enter the constant to be stored in HA register 2286. This causes the voter channel to energize the select output line 1627 to the I / O unit. The next microprogram word ZFECi checks the HT register 2284 using a mask 0001 0000. For this purpose, the A = A T line 566 is energized and forwards the contents of the HT register to the .A bus. This will test the voter channel polling control.

The next microprogram word ZFFF checks the HS register 2285 using the mask 0000 0100. This checks for the presence of an output signal from the "time out" multivibrator.

The next microprogram word ZFGFO removes a byte from the CPiZ memory, which is addressed by memory location K 04.

K 04 is the voter channel unit address byte. The microprogram word ZFHF transfers the information or data from the R register 139, which contained the unit address, to the memory location K 04. This step also sets the λ / 5 register 2287 to the constant 10000, and thereby again the daisy chain interlock circuit is turned on.

With the microprogram words ZF] CO and ZFKC

the content of the {/ register 142 (FIG. 2b) is transferred to the memory location K 05. In addition, the step ZFKC clears the three lowest bit positions of the V register 143 (FIG. 2b). The contents of the V register 143 (FIG . 2b) are transferred to the memory location K 06 by the next two microprogram words ZFLCO and ZFKC. The latter microprogram words then have the unit address stored in K 04 and the CCW address in K 05 and K 06.

The microprogram words ZFLC 2 and ZFBH

transfer the content of the memory location K 5, which contains the data of the Ü register 142, to the ///? register 2283 (FIG. 5a) and then to the HP register 2277 (FIG. 5a).

With the microprogram words ZFCH and ZFDH

the content of the memory location K 06, which contains the data of the V register 143, is transferred to the ///? register 2283 and then to the // Q register 2278 (FIG. 5a).

In addition, this last microprogram word loads the HCHD registers 2279 and 2280 with the contents of the /// WQ registers 2277 and 2278 (FIG. 5a) by passing the data through the HZ (plus-8) adder 2288, the it increased by 8.

The content of K 06 is then transferred to the // Q register 2278 by the last two microprogram words and the same information is then increased by 8 and introduced into the HCHD registers 2279, 2280. The information in the // C / ZD registers 2279 and 2280 is the next CCW address because the previous CCW address has been increased by eight.

The next two microprogram steps ZFEH and ZFüH transfer the content of the // C register 2279 to the memory location K 05. These steps also load the HUHV registers 2281 and 2282 from the // P // (? Registers 2277 and 2278. This causes the address of the first byte of the current channel control word to go into the // t / Z / V register.These steps also set the // ß register 2287 to the constant 010000, thereby triggering the mini-stable »time out« multivibrator.

The next microprogram words ZFGH and ZFHH transfer the content of the HD register 2280 to memory location ΛΓ06. The next CCW address is then entered into memory locations K 05 and K 06 using the last four microprogram words. This information came from the registers HCHD 2279 and 2280 (Fig. 5a). The microprogram words ZFJH and ZFKH address the main memory 2204 ( FIG. 2c) from the registers HUHV228i and 2282. After the main memory 2204 has been addressed, the HUHV register is advanced by adding the contents of the HPHQ registers 2277 and 2278, this information is passed through the // V register 2288 to increase by 1. This increases the address of the channel control word by 1 and addresses the second byte of the channel control word. The information from the main memory 2204 ( FIG . 2c) which has been addressed by HUHV 2281 and 2282 (or the first byte of the channel control word) is transferred to the H /? Register 2283 and then passed on to the HC register 2279 -

709 611/411

passes, and the last three bits of that byte are passed to op register 2291. As a result, the first byte of the channel control word (identifier and op part) gets into // C register 2277 and the Ορ-Ίού of this byte into op register 2291. The next microprogram word ZGBC spray the HS register 2285 with a mask 0000 0010 This checks the three lowest bit positions of the // Ä register 2283 for a non-zero state. This is used to check the validity of the op-code contained in the HR register.

The main memory 2204 (FIG. 2c) from the // £ / V registers 2281 and 2282 is addressed by the next microprogram word ZGCC. As a result, the address of the second byte of the channel control word reaches the M / V registers 137, 138 (FIG. 2b) in order to address the main memory 2204. This word also checks the // Γ register 2384 using the mask 0000 0001. This checks the channel for a "transmission in channel" status. With the next microprogram word ZGDCQ , the second byte of the channel control word arrives in the ///? Register 2283. In addition, the information in the // Ä register is transferred to the main memory 2204 (F i g.2c) regenerated. This word also checks the HS register 2285 using the mask 0010 0000. This checks the HR register 2283 for a non-zero state. (This is used to test for significant data from the main memory-addressed by HUV 2204.)

The next two microprogram words ZGED 1 and ZGFB 1 cause the address of the I / O unit to be transferred from the memory location K 04 to the // Ä register 2283 (FIG. 5a) in preparation for its further development via the data output lines 2261. This happens in the same steps by setting the ///! register 2286 to the constant 10001, whereby the address from / C 04 is forwarded to the data output line 2261 and the select output line 1627 is switched on. The following micro program words ZGGC set the ///! Register 2286 to a constant 11001. This energizes data output line 2261 and select output line 1627 , as before, but also energizes address output line 1621. This corresponds to the specification for the coupling unit that the address must be on the data output lines 2261 before the address output line 1621 is energized. The next microprogram word ZGEJX checks the // Γ register 2284 using the mask 1000 0000. This is used to check the excitation of the input mode on line 1629 from the I / O unit. The // Γ register 2284 is checked by the next microprogram word ZGBJ using the mask 0000 0100. This is used to check the dial channel for the presence of the "No reaction" status. The next two microprogram words ZGCK 1 and ZGDHO both check the // 5 register 2285 using the masks 0000 0100 and 000 1000 respectively the microprogram word ZFFH has been triggered. This monostable multivibrator has a time constant of around one millisecond. The second test is the state of the daisy chain interlock circuit.

The memory location KH is read out by the next three microprogram words ZGDH, ZGGHi and ZGHJQ. The constant 0001 is inserted into the four highest bit positions of this mask by the status register and the mask and the byte is stored again in K 11. In addition, the latter microprogram word sets the HA register 2286 to a constant 00000. This switches off all license plate output control lines and thus makes all commands to the I / O unit ineffective. The next microprogram word ZHPDO

ίο checks the // T register 2284 using the mask 1010 0000. This checks the incoming control lines on the I / O unit for the excitation of the input operation on line 1629 and the status input line 1625. The next microprogram word ZHGG 1 checks the // 5 register 2285 using the mask 0000 0100. As with ZGCK 1, this checks the presence of the output signal of the monostable “time out” multivibrator.

If the result of the test for the input operation input and the status input line 1629, 1625 is equal to zero, a branch to the microprogram word ZHFDi is initiated . This microprogram word then branches off to AGBA 1, as a result of which the L register 136 is cleared and a branch to KABA 0 is effected. This means that a successful initial selection of an I / O unit has been made on the selector channel. The use of the registers in Fig. 5a, 5b can be summarized as follows: The CCW address entered in HPHQ 2277 and 2278 is passed on through // Z register 2288 in order to be increased by 8 and to the // C / / £> registers 2279 and 2280. These registers then contain the address of the next channel control word. Then the contents of HPHQ registers 2277 and 2278 are driven directly into HUHV registers 2281 and 2282. By means of the HUHV register is then addressed, the current channel control word in the main memory, and after each address circulation of the contents of HUHV is supplied to the registers HPHQ whose content increased by HY22.2 "by 1 and input to the // LWK registers 2281 and 2282 will. In this way, the bytes of the required channel control word are addressed from the main memory 2204 and processed via the HR register 2283. The state or status of the I / O unit and the selector channel control circuit is checked by reading either the // Γ register 2284 or the // S register 2285 using the mask necessary to carry out the test. These tests branch to the result if Z is zero or Z is one.

Channel status word

The Channel Status Word (CSW) tells the program the status of an I / O unit or the conditions under which an I / O operation has completed. It is created or parts of it are replaced in the course of I / O interruptions and by the commands "Start I / O" and "Check I / O". The channel status word is entered in memory location 64 of the main memory and is available to the program at this point until the next I / O interruption occurs or until a command "Start I / O" or "Check I / O" causes that its content is replaced by another.

If the channel status word is saved as the result of an I / 0 interrupt, the assigned

nete I / 0 unit identified by the I / 0 address in the old CSW . The information inserted into the channel status word by the "Start I / O" or "Check I / O" command always relates to the I / O unit to which the command was addressed.

The channel status word has the one shown in FIG Format.

The fields in the channel status word are allocated to the following purposes:

Sagittarius license plate

Bit positions 0 to 3 contain the memory contactor identifier, the sequence of operations initiated by the last "start I / O" command has been used.

Command address

Bits 8 to 31 identify the last used channel control word (CCW).

Status bits

Bits 32 through 47 identify the conditions in the I / O unit and the channel that is storing of the channel status word. Bits 32 to 39 are obtained via the I / O coupling unit and provided by the I / O unit or the I / O control unit determined conditions. Bits 40 to 47 are supplied by the channel and represent the Channel assigned conditions. Each of the 16 bits represents a kind of "condition. The with Conditions marked with an "I" cause I / O interruptions and are called interruption conditions designated. The bit distribution is as follows:

Bit 32 I. danger Bit 33 Leap Bit 34 Unit data check Bit 35 occupied Bit 36 I. End Bit 37 I. Unity made free Bit 38 I. Intervention required Bit 39 I. state of emergency Bit 40 I. Program-controlled sub chung Bit 41 Wrong length Bit 42 Program review Bit 43 Protection test Bit 44 Channel data check Bit 45 I. Channel control audit Bit 46 I. Coupling unit control test Bit 47 Chaining test Count

At this point in time, the channel status word can only be activated by an I / O interruption or by the »Check I / O« - Command to be saved. A channel status word, which is assigned to conditions that follow the Completion of the operation occur on the channel, contains a zero in each case in the tag, command address and Count field under the condition that the states are not cleared by the "Start I / O" command. These states include "respect" - and

ίο "Unity made free" status as well as the final status, if it occurs after completing an operation on the selector channel with "Stop I / O".

If the aforementioned states are canceled by the »Start I / O« command, only the Status bit part of the channel status word is saved, and the original content of the identifier command address and count fields in memory location 64 are retained. Likewise, only the status bits of the Channel status word changed if the command is rejected or the operation on the sub-channel is completed while the "Start I / O" command is being executed.

Errors discovered during the execution of the I / O operation do not affect the validity of the channel status word, except when the channel control check or the coupling unit control check status is indicated. The channel control test indicates that faults have been found in the components as a result of which any part of the channel status word may become invalid. The coupling unit control test indicates that the address identifying the I / O unit or the status bits received from the I / O unit may be invalid. The channel enforces correct parity on CS W fields that it has found invalid.

Bit positions 48 to 63 contain the remaining count of the last used channel control word.

Content of the channel status word

The content of the channel status word depends on the condition that caused its storage and on the method by which the status information was obtained If the channel status word is stored in the channel during execution or after completion of an I / 0 operation, the The contents of the license plate, command address and count fields are usually related to the current values of the corresponding sizes. The "shooter" mark

A channel status word that is stored to reflect the progress of an operation on the channel, contains the protection symbol used in the relevant operation. The content of this field is not carried through Programming errors affected by the channel or the conditions who brought about the completion of the operation.

Examples for the chaining of data addresses

RBKB 1

Set the / M coupling unit register 2300 using the constants 00001. Turn off S4 and 55.

Branch to RBBEO at 56 and 57.

(So far the same as for the time division multiplex routine.)

RBBEi

Check the / T register using the Mask 0001 0001.

Switch 54 on if all four highest bit positions of the addition output contain zeros. Otherwise turn off 54. Turn 55 on if all four lowest bit positions of the add output contain zeros. Otherwise turn 55 off. Branch to RFBB.

This is a check for the presence of the input operation and / or status input signal.

Delete

the D register 132 and turn off the transfer latch circuit. Branch to RFCB O at S 4 and 55.
(To RFCB 1 for input operating signal.)

RFCB 1

RGED

Same as the previous operation except that it applies to the higher places the "address of the next channel control word" happens.

RGFD

Check the G register 133 using the mask 1000 0000.

Branch to RFDD. '

This is a check for the presence of the CDA (data address concatenation) identifier.

3 °

RFDD

Check the G register 133 using the ' ⁵ mask QOLO 0000.

Branch to RFEDO at 0 and Zequals 0.

(Indicates the presence of CDA .)

RFEDO

Link the content of T-register 141 in OR form with 0000 0110 and save the result in T register 141.

Branch to A GBD.

As a result, the address of the seventh byte of the UCW gets into the T register 141. (lowest digit of the

next channel control word.)
RGBD

Take a byte from the i / C W memory 2204 addressed by the T register.

Increase the value of T-Register 141 and store the result in T-Register.

Turn off 5 7.

Branch to RGCD.

This causes the seventh byte of the unit control

word read out.
RGCD

Store information from memory in register 139 and delay memory write one round. Add the contents of the R register 139 to 0000 1000 and store the result in the λ register 139 and the carry out in the carry latch.
Branch to RGDD.

This adds 8 to the lower digits of the "address of the next channel control word", and the new "address of the next channel control word" is created.

RGDD

Save information from the memory in the / ^ register 139 and regenerate the memory 2204. Decrease the value of the R register 139 by 1000 and save the result in V.

Branch to RGED.

This will put the new "address of the next channel control word" in the unit control word introduced and the original "address of the next channel control word" again in the V register 143 saved.

Add the contents of the λ register 139 to zero with an input carry from the carry latch circuit and store the result in the i? Register 139 and the output carry in the carry latch circuit. Branch to RGGE 0 at 0 and 53. This corrects the higher digits by 1 if there was a carry over from the lower digits.

RGGEO Store information from memory 2204 in the Ä register 139 and regenerate the memory, transfer the content of the /? Register to the (/ register 142.

Branch to RGHD.

This saves the new "address of the next channel control word" in the unit control word and transfer the original "address 3 of the next channel control word" to the (/ register.

RGHD Take ... a byte from the main memory 2204 addressed by the U and V registers 142, 143.

Increase the value of V register 143 and store the result in V register 143.

Branch to RG] D.

(First byte of the channel control word.)

RGJD Transfer information from memory 2204 to /? Register 138 and regenerate memory. Connect the four lowest bits of the Ä register cross in or-but form with 1111 0000. Branch to RGBF.

As a result, the first byte of the channel control word is checked for the presence of zeros in the lowest Bit positions checked.

RGBF Takes a byte from the main memory 2204 addressed by the U and V registers 142, 143. Increase the value of the V register 143 by 0010 and store the result in the V register. Branch to RGCJO at 54 and 57. (Second byte of the channel control word.)

RGCJO Transfer information from memory 2204 to / ^ register 139 and regenerate memory. Add the contents of the Ä register to zero. Branch to RHBB.
This checks the second byte for zeros.

RHBB

Take a byte from the L / CW memory addressed by the T register 141.

Decrease the value of the T-register and save the result in the T-register.

Branch to RGFD.

Take a byte from the main memory 2204 addressed by U, V registers 142, 143. Decrease the value of V register 143 and store the result in the V register. Turn off 52. Branch to RHCCO at 56 and Z is 0. (fourth byte of the channel control word.)

RHCCi

Transfer information from memory 22041 to λ register 139 and regenerate the memory. Combine the content of T-register 141 in AND-form with the complement of 0000 0101 and save the result in the T-register.
Branch to RHDD.

Add the contents of the λ register 139 to zero.

Branch to RHCF.

Check the sixth byte of the channel control word

RHCF

RHDD

Take a byte from the i / CW memory addressed by T register 141.

Increase the value of T-register 141 and store the result in T-register 141.

Branch to RHED.

(Third byte of the standard control word.) '

Ignore information from memory 2204 and store information from λ register 139 in memory location. Add the contents of the i? Register to zero,
consists of all zeros.
Branch to RHFD.

Check the third byte of the unit control word for zeros and then delete the third byte.

Take a byte from the main memory 2204 addressed by the U, V registers 142, 143. Increase the value of the · V register 143 by 0011 and store the result in the V register. Branch to RHDG 0 at 5 6 and 1. (Third byte of the channel control word.)

RHGDO

Transfer information from memory 2204 to λ register and regenerate memory.

Add the contents of the λ register 143 to zero. Switch on S 2 if the adder output does not consist of all zeros.

Branch to RHHD.

Check the third byte of the channel control word for zero.

Take a byte from the main memory 2204 addressed by the U, V registers 142, 143. Decrease the value of the V register 143 and store the result in the V register.
Branch to RHDHO with S6 and Z equal to 0. (Eighth byte of the channel control word.)

RHDHl Store information from memory 2204 in R register 139 and regenerate memory 2204. Branch to RHEF.

RHEF Take a byte from the i / CW memory addressed by T register 141.

Increase the value of the Γ register 141 and save the result in the Γ register.

Branch to RHFF.

(Fifth byte of the unit control word.) "

RHFF

3 ° Ignore information from memory 2204 and store information from /? - register 139 in the memory location.
Branch to RHGF.
Delete the fifth byte of the unit control word.

RHGF

RHHD

Take a byte from the i / CW memory addressed by T register 141.

Increase the value of the T register and save the result in the T register.

Branch to RHJD.

(Fourth byte of the unit control word.)

⁵ °

Ignore information from memory 2204 and store information from /? Register 139 in storage space.

Branch to RHKD.

(Delete fourth byte of the unit control word.)

RHKD

Take a byte from the main memory 2204 addressed by the U, V registers 142, 143. Increase the value of the V register 143 by 0010 and store the result in the V register.

Branch to RHBFO.

(Sixth byte of the channel control word.) Take a byte from the memory addressed by the U, V registers 142, 143. Decrease the value of the V register 143 by 0010 and save the result in the V register.
Branch to RHHFO at S 6 and 1.

RHHFO Store information from memory 2204 in R register 139 and regenerate memory. Branch to RHJF.

RHJF Take a byte from the i / CW memory addressed by T register 141.

Link the content of the T register in AND form with the complement of 0000 0111 and save that Result in the T register.

Branch to RHKF.

RHKF Ignore information from memory 2204 and store information from Ä register 139 in memory location. Increase the value of T-register 141 and store the result in the T-register. Branch to RHLF.

RHLF

RHBFO

Store information from memory 2204 in / ^ register 139 and regenerate memory 2204.

Take a byte from the main memory 2204 addressed by the U, V registers 142, 144. Add the contents of the V register 143 to 0000 0100 and store the result in the V register 143 and the

Carry out in the carry latch.

Branch to RHFH 0 at S 6 and 0.

709 611/411

RHFHO

Store information from memory 2204 in register 139 and regenerate memory 2204. Combine the content of register in AND form with the complement of 0000 0111 and store the result in D register 132.
Branch to RHGH.

RHGH

RHEJO

RHFJO

RHEJl

Take a byte from the t / CW memory addressed by T register 141.
Combine the four lowest bits in the G register 133 in OR form with the content of the D register 132 and store the result in the /? Register 139. Branch to RHHH.

RHHH

Ignore information from memory 2204 and store information from R register 139 in memory location. Increase the value of T-register 141 and save the result in Γ-register 141. Branch to RHJHO at 52 and 1.

RHJHO

Combine the content of T-register 141 in AND-form with the complement of 0000 0111 and save the result in the Γ-register.
Branch to RHBJ.

Take a byte from the t / CW memory addressed by T register 141.

Add zero to 0001 0001 with a forced input carry and save the result in .D register 132 and the carry out in the

Carry-over latch circuit. Branch to RHCJ.

Combine the four highest bits of the A register 139 in OR form with the content of the D register 132 and store the result in the /? Register 139. Switch 54 and 55 off.
Branch to RHDJ.

Turn on 56.

Branch to RHHK 0 at 56 and 0.

RHHKO

Set the / M coupling unit register 2300 using the constants 00000.
Branch to RHJK 0 at 1 to Zequals 0.

RHJKO

ίο Check the PT register using the

Mask 0001 0001.

Turn 54 on if all four highest bit positions of the adder output contain zeros. Otherwise turn off 54.
Turn 55 on if all four lowest digits of the adder output contain zeros.

Otherwise turn off 55.

Branch to RHKK.

₂₀ RHKK Clear D register 132 and turn off the carry latch circuit.

Turn on 5 7.

Branch to RBJEO at 54 and 55?

RBHE 2

Clear D register 132 and turn off the carry latch.
Branch to RBJEO at 54 and 55.
(From here on, the same as for the time division multiplexing routine.)

The microprogram word RBKB 1 established that the "count" has been reduced to zero. This has caused a branch to check for a chain data address (CDA) , and if a CDA is found , the 48 steps just described have been initiated. These steps have replaced a step, RBBE2 , which would normally have been performed in a time division multiplexing routine if the count had now been zero.

45 Example of command chaining

Store information from memory 2204 in /? Register 139 and regenerate memory. Set the / M coupler register 2300 using the constants 00101. Turn off 5 7.
Branch to RHEJO.

RFBB

Clear .D register 132 and turn off the carry latch.
Branch to RFCBO at 54 and 55.

Check the FT register using the Mask 0001 0000.

Branch to RHFJO at 0 and 53.

55 RFCB 2

Transfer the contents of the D register 132 to the Z? Register and switch on the carry interlock circuit.
Branch to RHEJO at 1 and Zequals 0.

Combine the content of T-register 141 in AND-form with the complement of 0000 0111 and save the result in the T-register.
Turn off 54 and 55.
Branch to RFDCO.

RFDCO

Check the / ^ register using the Mask 0000 0010.

Take a byte from the i / CW memory addressed by T register 141.

Clear D register 132 and turn off the carry latch.

Turn off 5 2.

Branch to RFEC.

PFCB

Store information from memory 2204 in λ register 139 and regenerate memory. Combine the content of the Ä register 139 in AND form with the complement of 0000 0011 and save the result in the D register 132.
Branch to RFFC.

Take a byte from the by T register 141 ι ο

addressed t / CW memory.

Combine the content of the S register 140 in OR form with the content of the D register 132 and save the result in the Ä register 139.

Branch to RFGC.

Ignore information from memory 2204 and store information from λ register 139 in memory location. Transfer the contents of the i? Register 139 to the S register 140.
Branch to RFGB.

Link the content of the G register 133 in AND form with the complement of 0000 0001 and save the result in the G register 133.
Branch to RFHB.

Increase the value of the Γ register 141 by 0110 and save the result in the Γ register. Branch to RFJB.

RFKC

Transfer the contents of the / V register to the D register

Branch to PFDB 0 at 1 and Zequals 0.

PFDB \ Check D register 132 using mask 1001 0000.
Branch to PFEB.

PFEB Check 5 register 140 using mask 1101 0000.

Branch to PFAFO at 1 and Zequals 0.

PFAF \ Check D register 132 using mask 00110011.

Branch to PFGEO at 1 and Zequals 0.

PFGEX Check the D register 132 using the mask 0000 0100.

Branch to PFHCO at 1 and Zequals-0.

PFHC \ Check the D-Register 132 using the mask 0000 1000.

Branch to PFJA 0 at 1 and Zequals 0.

PFJAO Check the G register 133 using the mask 0100 0000.

Branch to PFKA 0 at 0 and Zequals 0.

35

Take a byte from the i / CW memory addressed by the Γ register 141. Increase the value of the Γ register and save the result in the Γ register.

Branch to RFKB.

Store information from memory 2204 in / Z register 139 and regenerate memory.

Transfer the contents of the /? Register to the V register 143.

Branch to RFLB.

Take a byte from the L / CW memory addressed by Γ register 141.

Combine the content of the Γ register in AND form with the complement of 0000 0111 and save that Result in the Γ register.

Branch to RFKC.

PFKAO Check the D register 132 using the mask 0100 0000.

Branch to PGBA 0 at 0 and Zequals 0.

PGBAO Set the PS register 2304 using the constant 00111.

Turn off 57.

Branch to PGABO at 0 and Zequals 0.

PGAB 1 Increase the value of the Γ register 141 by 0010 and save the result in the Γ register. Branch to PGCB.

PGCB

55 Clear the R register 139.

Turn off 56.

Branch to PGDA 0 at 0 and G 7.

Store information from memory 2204 in λ register 139 and regenerate memory.

Transfer the content of the Ä register to the (/ register 142.

Branch to QGJC2.

QGJD 2

Check G register 133 using mask 1000 0000.
Branch to PFCB.

PGDAQ Set / M register 2300 using constants 00011.
Turn on 5 7.
Branch to PGEA 0.

PGEAO Check the ΡΓ register using mask 0000 0001.

Branch to PGFA 0 at AC and 1.

69 70

the value of the V register 144 and store that

Increase the value of the / 7 register 139 and result in the V register.

save the result in the Ä register. Branch to QBCB.
Branch to PGEA O at 1 and Zequals 0.

PGBA 1 ⁵ Q ^BCB

cL Ii j η λ r> -4. „« Η ■ * \ r j Store information from memory 2204 in

Invoke PA register 2300 using ^ register 139 and regenerate memory.

of the constants 0001. Transfer the contents of the Ä register 139 to the Z> Regi-

ScnalteS2ab. sterl32

Branch to PGHA. o _Verzw EIGE _to QBDB. PGHA

Set the PS register 2304 using QBDB

of the constant 00110. Take a byte from the through the U, V register

Branch to QBBB. 15 142, 143 addressed main memory 2204. Subtra-

here 0000 1111 of the four lowest bits of the

^ ZT register 132 with a forced input

Take a byte from the transmitted through the U, V register.

142, 143 addressed main memory 2204. Increment branch to QBEB.

In addition 9 sheets of drawings

Claims (17)

Patent claims: 1. A method for transmitting represented by binary signals information between a central data processing unit and a plurality of terminal units, such as input and output units which can be coupled by transmission lines on a time division basis with the memory of the central processing unit, using in, ₀ Memory contained transfer control data (transmission control words) which specify the type of transfer operations and the addresses of the data to be transferred, characterized in that in response to a request supplied by a connection unit or from the central processing unit, a memory area (connection unit control word) which is contained in the central processing unit and is permanently assigned to the relevant connection unit is called, which has a first sub-area for receiving address data for information to be transmitted, a second sub-area for receiving address data for an operation of the concerned transmission control data relating to the connection unit and a third sub-area for receiving status display and control signals of the associated connection unit, and that by calling up this memory area, the transmission control data addressed by the relevant sub-area are transferred from the memory of the central data processing unit to the calling connection unit area, under which Influence then the transmission takes place in a single or several transmission cycles. 2. The method according to claim 1, characterized in that the connection units repeatedly the presence of a transmission request are scanned and that if there is a Transfer request the address of the requesting connection unit to the central data processing unit transmitted and using this address the assigned unit control word to control the transmission is read out. 3. The method according to claim 1 and 2, characterized in that depending on the machine program the central data processing unit one of the connection units by searching of their associated unit control word is selected that this unit control word to a Occupied or ready status is checked and that if a ready status is present, control data from other storage locations in the central processing unit into the unit control word for control the connection unit are transmitted. 4. The method according to one or more of claims 1 to 3, characterized in that for each unit control word at least one stored in a memory of the central processing unit Transfer control word is assigned to the unit control word by a command of the machine program (problem program) is called and the control and address data for contains the information to be transmitted or partial information, and that depending on the Ready state of the line unit assigned to the called unit control word of the transmission control word is used to fill in the unit control word. 5. The method according to claim 4, characterized in that the transmission control words are independent the content of the unit control words while the machine program is running (problem program) called and loaded. 6. The method according to any one of claims 1 to 5, characterized in that the commands of the Machine program (problem program) of the central processing unit to start Transfer operations to or from a line unit with a first address part which is based on a selected line unit is related, and with a second address part which refers to the transmission control word related to the operation to be performed. 7. The method according to claims 4 to 6, characterized in that in a transmission control word a concatenation identifier is stored, which indicates a link to another contains the transfer control word assigned to the same unit control word, and that at the end of the transfer operation determined by a transfer control word, the concatenation identifier queried and, depending on this, another transmission control word called and in the assigned unit control word is transmitted for further control of the relevant line unit. 8. The method according to claims 4 to 7, characterized in that a transmission control word denotes a memory area containing a number of information bit groups (bytes). 9. The method according to claim 8, characterized in that the addressing data in the transmission control word for the memory area from the address of a first information bit group in the memory area and the number in this Information bit groups contained in the area. 10. The method according to any one of claims 4 to 9, characterized in that by a transmission control word for the transmission of information to the central processing unit, a new memory area for storing a Number of information bit groups is determined. 11. The method according to claims 4 to 10, characterized in that the transmission control words linked to one another by a concatenation identifier control the same type of operation for related pieces of information. 12. The method according to claims 4 to 11, characterized in that the transmission control words linked to one another by a concatenation identifier control different types of operations. 13. The method according to any one of claims 7 to 12, characterized in that the address of the following transfer control words by incrementing one contained in the unit control word to the address of the first transfer control word transmission control word address field set is obtained. 14. Device for performing the method according to at least one of claims 1 to 13 with a central data processing unit that has a Main memory, a microprogram read-only memory, an arithmetic unit and several data and address registers, some of which are used as data input and data output registers for the Transmission lines to the connection units are used, characterized in that the microprogram read-only memory (150) contains information transfer routines and about these routines the assigned outputs are connected to a transfer register arrangement (2300 and 2304), those for controlling the connection paths between the main memory, the data and address registers and the arithmetic unit and for controlling the data transmission paths to the connection units serves, and has the memory stages, which control signal lines common to all line units are connected and the type of data on the data transmission paths and on them Mark data-related control states. 15. Device according to claim 14, characterized in that the connection units are connected to a scanning circuit (DLY, SS, 1627, 1627 ', 2322) and each have a selection circuit (1632, 1637, 1639) which responds to the scanning signals generated by the scanning respond and, if the line unit concerned is in the ready state, render the scanning circuit ineffective and cause the address of the line unit concerned to be transmitted to the central processing unit. 16. Device according to claim 15, characterized in that the scanning circuit (DL Y, SS, 1627, 1627 ', 2322) receives a signal to resume scanning after completion of a transmission or partial transmission from the transmission register arrangement (2300,2304). 17. Device according to claims 14 and 15, characterized in that the scanning circuit (DLY, SS, 1627, 1627 ', 2322) comprises a series connection of the connection units on which a scanning pulse passes through all connection units one after the other, and that the selection circuits (1632, 1637, 1639) when a scanning pulse occurs in the series link, in the case of a ready state, interrupt the series link and, in the case of a busy state, forward the scanning pulse to the next line unit and that a return line is provided from the last line unit to the central processing unit via which the returning sampling pulse initiates a repetition of the sampling.