DE1287158B - Method and circuit arrangement for querying connection lines for their operating status in a time division multiplex switching system - Google Patents

Description

In switching technology, many have gone over to this to set up switching systems working on the time division multiplex principle. In such Switching systems are known to be the messages to be exchanged temporally offset pulse sequences modulated on. The following as Pulse sequences called control pulses can be used to connect to the connections to be established be assigned.

In order to have a large number of connections in such a switching system establish or maintain between a corresponding number of participants to be able to, one often has a certain number of each for the respective Participants belonging to the switching system are grouped together. You can then a. Connection traffic between participants in the same group of participants or different groups. To maintain connection traffic between the participants of such a switching system are the individual participants electronic time channel switch permanently assigned, via which the participants with a to the respective group of subscribers belonging multiplex rail in connection stand. Due to the control pulses assigned to the connections, the individual Pulse phases simultaneously made those time channel switches transferable which belong to participants who are to be connected to one another.

Circulating memory is used to control the relevant time channel switch provided, in which the addresses of the participants concerned are in each case phage-appropriate enrolled and saved. In doing so, the addresses of each interfere with each other connected participants simultaneously in pulses and with the pulse repetition frequency of the control pulses to be generated repeatedly at the outputs of the circulating memory. The addresses run cyclically in the circular memories with specific pulse phases around. Since the addresses stored in the circular memories are usually several bits include, however, to operate the speech switch each time by a control pulse are, the circulating storage decoders have been connected through which a corresponding Implementation of the addresses is made.

In the manner indicated above, connection paths between each with each other in message exchange maintained participants. However, these connection paths must first be established and, if necessary can also be separated again. Requirement for a connection to be established is first of all the determination of connection requests and then the saving the addresses of the calling or called subscriber to the ones in question Circulating storage. For the determination of placement requests, it is known to use the individual Repeatedly query participants for their operating status.

It is Z. B. a circuit arrangement for a 10,000 subscriber comprehensive Time division switching system known (German Patent 905 380), in which 200 participants are combined in a group and for each Group has its own scanning and control device for querying the participants only of the group concerned are required to carry out the activities required for these participants Mediation processes is provided. Each group has its own pulse generator each time with the sampling period, a pulse is repeated on a 200 series-connected Delay line each having sections of equal length; on everyone of these 200 successive sections is each a participant of the Group connected. These participants are one after the other through such an impulse are queried and each give a character characterizing their loop state Criterion, on the basis of which, if necessary, by the group's own control device, to which, among other things, a group-specific call finder and a call finder downstream voters belong, a necessary operational process is carried out will. In this switching system, there is a correspondingly high level of circuitry Effort required.

The considerable outlay on devices to be provided individually for groups in the time division multiplex switching system mentioned above can be reduced in accordance with a further time division multiplex switching system (German patent specification 1 024 124) in which 10,000 subscribers are combined in 100 groups of 100 subscribers each: With help scanning circuits individually assigned to the individual groups of participants determine whether at least one subscriber in the relevant group of participants would like to set up or clear a connection, and a centrally located scanning circuit then interrogates these scanning circuits assigned to the individual groups of participants, whereupon the query result is fed to a selection circuit. This selection circuit emits a signal identifying such a group of subscribers in which at least one subscriber has a switching request. After the relevant group of connection lines has been activated and a switching process required due to switching requests has been carried out for only one participant in this group, the centrally provided selection circuit selects another group of participants in which there is also at least one participant who has a switching request. This known circuit arrangement, which, in contrast to the circuit arrangement mentioned above, does not use group-specific evaluation circuits but a central evaluation circuit, requires, in addition to the group-specific scanning circuits, a scanning circuit arranged in a line-centered manner. It also has the disadvantage that if there are a large number of switching requests in one and the same group of subscribers, these cannot be taken into account in a reasonable time, since, as stated above, the centrally provided evaluation circuit in every case, including the If there are a large number of switching requests in one and the same group of subscribers, another group of subscribers is immediately triggered after the first switching process for a subscriber of a group of subscribers has been carried out on the basis of a switching request.

The invention now shows a new way in one Time division switching system Interrogate connecting lines for their operating status.

The invention relates to a method for interrogating connecting lines their operating status in a connection line combined into groups having time-division switching system in which the individual groups of Connection lines one after the other through a required switching processes between Connection lines one and the same group or different groups of connection lines unwinding central control device are controlled. This procedure is characterized in that the central control device with the aid of one after the other the addresses of all connection lines to be queried for their operating status line address generator generating such addresses at each group of Connection lines associated and one after the other with the central control device interconnected ones that accept such addresses and those designated by these addresses Connecting lines activating devices emits that with each such activation a discharge of the respective existing at the respective connection lines Signals indicating operating states, possibly requiring operating processes trigger to the central control device.

Using the method according to the invention results in opposite the previously known, initially mentioned method for interrogating connecting lines on their operating status in a time division multiplex switching system is essential Advantage that only a single one assigned to a large number of participants and thereby In terms of circuitry, a relatively simple central control device is provided to become necessary, in order to nevertheless also with simultaneous occurrence of mediation requests a plurality of subscribers all of these switching requests in one for them Participants practically no inadmissibly long waiting time significant period of time to be able to recognize and take into account.

According to an expedient embodiment of the method according to the invention gives the designation of corresponding connection lines of different groups of connecting lines within the respective group of connecting lines one and the same address of the line address generator such connection lines descriptive address during a period of time during which all Groups of connecting lines interconnected one after the other with the central control device and the connection lines of the individual groups identified by this address of connecting lines are checked to see whether they have an operating process have required operating state, according to which from the line address generator in a corresponding manner further addresses for querying further connection lines be delivered. This measure has the advantage that the central Control device compared, for example, to a successive query each of all connecting lines of one and the same group of connecting lines with the individual groups of connecting lines, each at equally short intervals is often interconnected and therefore by in the individual groups of connecting lines each emitting information relating to the setting up and clearing down of connections Connection lines record such information at such short time intervals may that they are already in the context of the specified interconnection with the individual Groups of connecting lines for all switching process requirements from there, in particular the timely provision of electoral information recipients, can suffice.

According to a further useful embodiment of the invention The method is based on a comparison, known per se, from the line address generator generated address with the already in one to the respective group of connecting lines Addresses already written to the connections belonging to the circulating address memory the connecting lines involved each have an address for only one such connecting line, whose address has not yet been written into the relevant circulating address memory is, as the address of a connection line to be queried to the inputs of the to the relevant group of connecting lines belonging to; controlling the connecting lines Furnishing delivered. Because the addresses only of those not involved in connections Connection lines issued to control the connection lines to be queried in each case are obtained from a query of all connecting lines, their addresses are generated by the address generator, a time saving due to which such Connection lines, each requiring a specific operating process Have operating condition, can be determined in a particularly short time and the necessary operational processes are carried out in a correspondingly shorter time can be. Furthermore, this measure has the advantage that otherwise Interfering noises possibly caused by the (non-periodic) sampling pulses cannot affect the participants currently involved in connections.

It is now of particular advantage if, according to a further expedient Embodiment of the method according to the invention, an address of an address to be queried Connection line each with the phase position of a pulse for allocation each provided a connection, but in the relevant group of connecting lines control pulse not currently involved in a connection to the inputs of the supplies belonging to the respective group of connection lines device, since then on the one hand all control pulses can be allocated to connections and thus the number of each in the individual groups of connecting lines possible connections is as high as possible, so that the traffic load is high traffic loss that may occur in such a system is correspondingly small can be kept while on the other hand without any special circuitry Effort also made a query of the participants on connection requests to be carried out can be. The time spans required to process mediation are particularly short if, according to a further expedient embodiment of the method according to the invention a pending at the output of the line address generator Address of a connection line to be queried with the phase position of the next impulse of one intended for allocation to one connection in each case, but currently not a connection assigned control pulse to the inputs of the transmitted to the respective group of connection lines belonging device will.

With the phase position of a pulse one for allocation to one at a time Connection provided, but not currently assigned to a connection control pulse can according to a further advantageous embodiment of the method according to the invention also one required on the basis of the query of a connection line for its operating status Switching process can be handled in the respective group of connecting lines. According to a further advantageous embodiment of the method according to the invention can when interrogating a connection line not previously involved in a connection and detection of a loop closure the mediation process consist of that the address of the relevant connection line with the relevant phase position in the circulating memory belonging to the relevant group of connection lines is enrolled.

It can be of particular advantage to have such a switching process nor with the phase position of the same pulse one for allocation to one connection in each case provided, but not currently in the respective group of connecting lines a connection assigned control pulse with which the address of the relevant Connection line to the inputs of one to the respective group of connection lines belonging decoder provided as a device controlling these connecting lines is delivered, since then with one and the same control pulse two processes, namely on the one hand the interrogation of a connection line of a group of connection lines their operating status and, on the other hand, an operating process that may be required can be handled in the relevant group of connecting lines.

According to another expedient embodiment of the invention However, such a mediation process can also use the phase position of a method other impulse one intended for allocation to one connection, however control pulse currently not assigned to a connection as the pulse with its phase position the address of the connection line to be queried at the inputs that belonging to the respective group of connection lines than the connection lines this group of connecting lines controlling device provided decoder has been delivered, to be processed e.g. B. by occurring processing times otherwise possible faulty operating conditions to be avoided. There these processing times are usually not very long, if necessary advantageously those required in the relevant group of connection lines Mediation process with the phase position of the next pulse in each case relevant group of connection lines for allocation to one connection in each case the intended control pulse that is not currently assigned to a connection.

After comparing one generated by the line address generator Address with the addresses already written in a circulating address memory can also according to a further advantageous embodiment of the invention Procedure simultaneously with the delivery of an address of a connection line to be queried to the inputs of the belonging to the respective group of connection lines, as the device controlling the connecting lines of this group of connecting lines provided decoder this address in the to the relevant group of connecting lines belonging circulating address memory are written and depending on be deleted from the query result or left in the circulating address memory. Included For the sake of simplicity, one can optionally be assigned to the respective group by overwriting the address written in by connecting lines belonging to the circular memory another address to be queried in this group of connecting lines Connection line can be deleted. This again results in the advantage that with the phase position of one and the same control pulse within a group of Connection lines a connection line are queried for their operating state can and a handling of the operations required for this connection line can be made so that no further control pulse is provided for this must become.

The method according to the invention can also be expedient in this way be configured that a pending at the output of the line address generator Address of one to be queried in the relevant group of connecting lines, if necessary Connection line already during the address comparison with the phase position of the first Impulse one intended for allocation to one connection, but in the relevant group of connecting lines not currently assigned to a connection Control pulse then in those belonging to the relevant group of connecting lines Circulating memory with simultaneous marking of the pulse phase concerned If no address equality has been found up to then, that in the further In the course of the address comparison, the occurrence of an address match may occur is stored and that after the end of the address comparison, the for the marked Pulse phase at the circulating memory output of the address in the relevant group of connection lines to be queried connection line only if an occurrence of an address match is not stored as an address of a connection line to be queried for the marked pulse phase to the input of the in the relevant group of connecting lines as this controlling device provided decoder is delivered and otherwise deleted. By such a Measure is compared to the aforementioned expedient embodiment of the invention Procedure opens up the possibility, regardless of whether the address in question already in the circulating memory belonging to the respective group of connection lines is inscribed or not, in each case after each cycle of the in the Addresses written in the relevant circular memory have a new address for querying to be able to deliver a corresponding other connection line. from The advantage is according to a further advantageous embodiment of the invention Method that after a comparison of a generated by the line address generator, each a plurality of connecting lines designating base address with the corresponding Address parts of the straight in one to the respective group of connecting lines Address circular memory belonging to the addresses involved in connections Leads the addresses of all of those designated by the base address Connection lines whose addresses are not yet in one of the respective groups of Leads belonging to the circulating address memory are written, one after the other as addresses of connection lines to be queried of the respective group of connection lines each with the phase position of a pulse one for allocation to a connection provided, but not currently in the relevant group of connecting lines a connection assigned control pulse to the inputs of the respective Group of connecting lines belonging to the decoder are supplied. This will during a period of time during that in the previously known time division multiplex switching systems just a single address with those in one to a group of connecting lines Addresses written in belonging to the circulating address memory were compared, a Large number of connection lines to be queried, if necessary, for their operating status identifying addresses with those in the for the relevant group of connecting lines associated address circulation memory compared to written addresses, so that a and the same central control device in total within a certain period of time can serve a much larger number of connection lines than with a control device carrying out a purely serial interrogation of connecting lines would be the case.

It is according to another advantageous embodiment of the invention Method also possible after comparing one from the line address generator generated base address each designating a plurality of connecting lines with the corresponding address parts of the already in one to the respective group Addresses written in by connecting lines belonging to the circulating address memory in each case only the address of a single one of those designated by the base address Connection lines whose address is not yet in that of the respective group of Leads belonging to address circulation memory are written as an address a connection line to be interrogated, each with the phase position of a pulse intended for allocation to one connection, but currently in the relevant one Group of connection lines not assigned to a connection control pulse the inputs of the decoder belonging to the respective group of connecting lines to deliver. Such a procedure requires very little circuitry Effort for evaluating the results of the examination of the within each Groups of connecting lines each simultaneously designated connecting lines on their respective operating status, at the same time because of the special speed of the method according to the invention for the connecting lines not taken into account here there are still no inadmissibly long waiting times.

It is according to another expedient embodiment of the invention Method still possible after comparing one from the line address generator generated, a plurality of connecting lines designating base address with the corresponding base address parts of the already in one to the respective group Addresses written in by connecting lines belonging to the circulating address memory in each case also only the addresses of bevo_-zuuten connection lines of those through the base address in each case designated connecting lines, whose addresses are not yet in the address circulation memory belonging to the respective group of connection lines are written in as addresses of connection lines to be queried, in each case with the phase position of a pulse of one provided for allocation to one connection in each case, but currently not a connection in the group of connection lines in question assigned control pulse to the input of the relevant group of connection lines to deliver the associated decoder. This ensures that preferred for this Connection lines required operations in each case without special waiting times be performed.

In order to be allocated in the individual groups of connection lines intended for a connection but not currently assigned to a connection Control pulses for querying connection lines in the supervising group, Utilizing connecting cables to their operational status must first of all Information about the phase position of such control pulses can be obtained. These Information, i.e. information about the phase position of the pulses from to the allocation to one connection provided in each case, but in the relevant group of connection lines Control pulses that are currently not assigned to a connection are processed according to further expedient embodiment of the method according to the invention in each case from one in the respective group of connecting lines provided for generating this Addresses of the connecting lines involved in each connection, which are used for control pulses contained circulating address memory by determining the currently not with addresses used memory locations. As a result, it is with very little circuitry Effort possible, information about the phase position of impulses from the person concerned Group of connection lines intended for allocation to one connection each, but mon: ° ntan not receive control pulses assigned to a connection.

It is according to a further expedient embodiment of the invention Method also possible to get the information about the phase position of the pulses from to Allocation to one connection provided, but in the respective group control pulses currently not assigned to a connection by connecting lines to gain from a circulating address memory, in which the addresses of each involved in connections, from the multiplex rail of the relevant group of Connection lines to multiplex rails of other groups of connection lines or to enable traffic within one and the same group of subscriber lines Temporary storage facilities leading connecting lines or Time channel switches and the addresses of the relevant group of connection lines available central signal transmitters and possibly also central ones Signal receivers are each written in phase. By such a measure can possibly be checked in a very simple way whether in the respective Group of connecting lines of the control pulse to be allocated to a connecting line does not already assigned to an existing connection or a connection that is still being established is; if the relevant control pulse has already been assigned to a connection, then the mentioned connecting line to avoid disturbances another control pulse allot.

Finally, according to a further expedient embodiment of the method according to the invention the phase position of in the respective group of connecting lines each intended for allocation to a connection, but in the respective group control pulses currently not assigned to a connection by connecting lines in be marked in a special runtime memory. This makes it particularly easier Possible, the finite ones, which are otherwise noticeable under certain circumstances The working times of the switching devices involved must be taken into account from the outset. In this case, according to a further expedient refinement, needs in the relevant runtime memory of the method according to the invention, the phase position of only a single one in the respective Group of connecting lines intended for allocation to a connection, however not currently being marked for a connection assigned control pulse, if one in each group of connection lines during a circulation cycle provided, containing the addresses of the connecting lines involved in connections Circulating memory with these addresses only one from the line address generator generated address is compared and the connecting line designated by this address If necessary, their operating status is queried or if after one several Address comparison comprehensive addresses only one by a single such address designated connecting line is optionally queried for its operating state. On the other hand, the phase position of all of the allocation is made in the runtime memory to one connection each, but currently in the respective group of connecting lines not mark a connection of assigned control pulses, if it is to be assumed that within the individual groups of connection lines in each case multiple connection lines after one made during a single circulation cycle Address comparison of their addresses generated with the aid of the line address generator with the addresses written in the circulating address memory to their operating status are to be queried and, if applicable, are actually queried, or if z. B. operations to be carried out for a connection line after its query during the occurrence of several pulses for allocation to one connection each provided in the relevant group of connection lines, but not currently a connection of allocated control pulses are to be processed.

The invention is explained in more detail below with reference to drawings. In Fig. 1 is an embodiment of a circuit arrangement for implementation of the method according to the invention in a connection lines combined into groups showing time-division switching system, in which, among other things separate signal receivers are provided in each group of connecting lines, and in Fig. 2 is a further embodiment of a circuit arrangement for implementation of the method according to the invention in one connection lines combined into groups showing time-division switching system, in which, among other things central signal receivers can be assigned to all groups of connecting lines.

The following is the process shown in FIG. 1 illustrated circuit arrangement explained in more detail. The circuit arrangement shown in this figure shows the details necessary for understanding the invention of a time-division multiplex switching system which has connecting lines combined into groups. First, the description of one of the groups Grl ... Grrz of connection lines belonging to this time-division multiplex switching system begins; it is the group Gr1. The other groups Gr2 ... Grn of connecting lines can be constructed in the same way as the group Grl described below. The subscribers Tn1 belonging to the group Grl. . . Tnx are connected to a speech multiplex bus MS via subscriber circuits Ts1 ... Tsx and time channel switches ZS1 ... ZSx. The time channel switches ZS1 ... ZSx are periodically operated in pulses by control pulses which are phase-shifted from one another, namely the time channel switches of participants who are currently involved in a connection are made capable of transmission in the cycle of a control pulse assigned to this connection. The control pulses are supplied by a circulating memory Ua belonging to the group Grl, also referred to below as a circulating address memory, with an associated decoder Da . The addresses of the subscribers involved in connections in this group Grl of subscribers circulate in the circulating address memory Ua, so that they appear periodically at the circulating memory outputs. Each address circulating in the circulating address memory Ua has a specific circulating phase. The pulse phases of the control pulses actuating the time channel switches ZS1 ... ZSx correspond to these circulating phases. The pulses of the various control pulses have the same pulse repetition frequency; the control pulses are nested in one another in such a way that one pulse of each of the remaining control pulses occurs between two consecutive pulses of a control pulse. The decoder Da is connected to the outputs of the circulating address memory Ua and has as many outputs as there are subscribers belonging to the group Gr1. Each of these outputs is assigned to a specific participant. If the address of a subscriber of this group Grl is supplied by subscribers to the decoder Da, a pulse is emitted at the output assigned to this subscriber, which is used to control the time channel switch belonging to this subscriber.

The decoder Da is used in the in FIG. 1 now used both for controlling the time channel switches ZS1 ... ZSx belonging to this group Grl of subscribers and for querying the subscriber circuits Tsl ... Tsx of this group Grl for their respective operating status. This will be discussed in more detail below. First, however, the structure of the in FIG. 1 illustrated time division switching system further explained.

To the in F i g. Group represented 1 Gr 1 part of leads yet another, hereinafter also referred to as an address circular memory designated circular buffer Uw with a downstream decoder Dw. In this address circular memory Uw the addresses run from such a time channel switches Zw order, through the actuation of the above respective associated time channel switch ZS to the opening multiplex rail MS connectable subscriber Tn this group Gr 1 with other groups Gr 2 ... Gr n of leads or to a traffic within this group Gr 1 enabling of leads buffer means CO leading multiplex rails GM and with this group Grl of leads available signal receivers ( e.g. Zix) and central signal transmitters (e.g. Wbz) can be connected. The to the in F i g. 1 of the group Gr 1 of subscribers belonging to intermediate storage devices CO are only indicated by a capacitor, the address of which may circulate in the circulating store Uw belonging to this group Grl of connecting lines.

The participants Tzz 1 ... Tn x the group Gr 1 associated subscriber circuits Ts 1 ... Ts x are connected to a group of its own monitoring multiplex line YM, will be explained on the, as follows, a the loop condition indicating when the query of a connection line criterion is transmitted.

All groups Grl ... Grn of connecting lines are connected to a set of connecting rails AS 1 ... AS 11; The same devices of all groups Gr1... Grn of connecting lines are connected to one and the same connecting rail via their own connecting line. For example, the connection rail AS 1 shown in FIG. 1 connecting bars AS1 ... AS11 shown the monitoring multiplex lines YM of all groups Gr 1 ... Grn of connecting lines connected.

Like F i g. 1 shows, switches S 11 ... S 17 or S n 1 ... S n7 are inserted into such connecting lines leading to the connecting rails AS. The switches S belonging to a group Gr of connecting lines are actuated by output signals emitted by group-specific unlocking circuits Gg; these unlocking circuits are shown in FIG. 1 formed by gates each having four inputs and each responding to a different bit combination. As in Fig. 1 is shown schematically, the inputs of these gates Gg are connected to the connecting rail AS11 . This connecting rail can, for example, comprise four individual lines if a parallel code containing 4 bits each is used to unlock the gates.

After the essential structure of one of the functions shown in FIG. 1 has been explained, the structure of the central control device SEZ1 common to all groups Grl ... Grn of connecting lines will now be described. To a query of the in F i g. 1 to their operating state, ie whether the subscriber loop is closed or not, is shown in FIG. 1 b, the central control device SEZ 1, a line address generator AG which successively generates the addresses of all the connecting lines to be interrogated for their operating status is provided. This line address generator AG outputs such addresses to a group of connection lines, which are connected one after the other to the central control device SEZ1, receive such addresses and control the connection lines identified by these addresses, namely the above-mentioned decoders Da , which with each such activation an output of cause the signals to the central control device SE Z 1, which indicate the operating states present in the respective connection lines and may require operating processes. In the case of the in FIG. Shown central control device SEZ 1 1, the delivery of such addresses from the line address generator AG to such addresses and receiving the leads which drives decoder designated by these addresses affected, since by comparing means and one of said downstream storage stage. With the aid of the comparison device, comparisons are made between the addresses output by the line address generator AG and the addresses of the connection lines involved in connections in this group of connection lines, which are written in a circulating memory Ua belonging to the respective groups of connection lines. carried out. The comparison result output by this comparison device is fed to the aforementioned memory stage, which outputs at its output the addresses of those connection lines subjected to the comparison, the addresses of which have not yet been written into the circulating address memory belonging to the relevant group of connection lines. Since the connection lines of the relevant group of connection lines identified by these addresses are not involved in connections, it is precisely these lines that have to be queried for their loop status in order to determine new connection requests.

The devices downstream of the line address generator AG are considered in more detail below. In the case of the one shown in FIG. The line address generator AG contained in the central control unit SEZ 1 shown in FIG. 1 may be an address generator emitting a base address common to a plurality of connection lines. The addresses circulating in the circulating address memories Ua belonging to the individual groups of connection lines each consist of a first part, which corresponds to the basic addresses given by the line address generator AG and which is to be referred to here as the basic address part, and of a second part, which is the additional address part should be designated. For example, the basic address part comprises the first 5 bits and the additional address part the last 3 bits of an address consisting of a total of 8 bits.

On the one hand, a comparison device having two inputs and one output, namely the comparison device VGa with its one input, is connected to the output of this line address generator AG; on the other hand, a switch Sc is connected to the output of the line address generator AG. The other input of the comparison device VGa is connected to a connection rail, to which on the other hand the circulating memory Ua provided in the individual groups Gr of connection lines and containing the addresses of the connection lines involved in these groups with their outputs each via one of the above-mentioned unlocking circuits actuatable switches S12 ... Sn 2 are connected. The comparison device VGa receives, on the one hand, the base address given by the line address generator AG and, on the other hand, the addresses of subscribers involved in connections in the respective group of connection lines that occur at the outputs of the groups of connection lines connected one after the other with the central control device.

The in the in F i g. 1 shown central control device SEZ 1 provided comparison device VGa consists of a switch Sa and this switch controlling the actual comparator Va. This comparator Va has two inputs, one of which is supplied with the base address given by the line address generator AG and the other the respective base address part of the output of the circulating address memory Ua is supplied to the group Gr of connecting lines which are connected one after the other with the central control device SEZ 1. In case of equality between which may be formed straight from the line address generator AG emitted base address and a base address portion just occurring at the output of the address circular memory, the comparator Va, the corresponding through one of the number of members of the base address bits number of equivalent gates, a the Sa switch operating pulse from. The additional address part following the basic address part of the address just occurring at the output of the circular address memory is then entered into a memory device Spa via the switch Sa actuated in this way. In this memory device Spa, this results in a marking of a memory location assigned to this additional address part. This is now achieved in the following way: The input of the memory device Spa is followed by a decoder Ds, to which the additional address part transmitted via the actuated switch Sa of the comparison device VGa is supplied with an address that corresponds in its base address part to the base address supplied by the line address generator AG. The decoder Ds has a number of outputs which is equal to the number of possible additional address parts; If the additional address part of an address consists, for example, of 3 bits, the decoder Ds can have eight outputs. If a certain additional address part occurs at the input of the decoder Ds, the decoder Ds emits a signal at its output assigned to this additional address part. Each output of the decoder Ds is followed by a 1-bit memory K1 ... Kn. These 1-bit memories K1 ... Km are thus individually assigned to a possible additional address part. Occurs at an exit de; When the decoder Ds receives a signal, the associated 1-bit memory K is marked by switching from its one operating state to its other operating state, so that the associated additional address part in code 1 of m is stored in the memory Spc.

At the output of each 1-bit memory K1 ... Km activated during said one operating state, one input is in each case a; connected to the 1-bit memory K1 ... Km downstream encoder Cs. This listening to an output circuit AS, the storage device Spa overall Cs encoder is used to convert the 1-bit memories K 1 ... Km each in the code of 1 m stored additional address parts in the original code. The further function of the output circuit As, which, like the line address generator AG, leads to the switch Sc, is described in the following functional description of the function shown in FIG. 1 shown central control device SEZ 1 will be explained with.

This switch Sc leads to that connecting rail to which the inputs of the circulating storage Ua contained in the individual groups Gr1 ... Grn of connecting lines are connected via unlocking circuits Gg 1 .. provided in the individual groups Grl ... Grn of connecting lines. . Ggn released unlocking signals actuatable switches S13 ... Srz3 are connected. Via the switch Sc , the addresses of those subscribers identified by the base address given by the line address generator AG , whose addresses are not written into the circulating memory Ua belonging to the group Gr of connecting lines connected to the central control device SEZ1, are given.

Besides the previously described devices, the central controller SEZ1 comprises smelled an address encoder WAg to write the addresses provided for in each group Gr 1 ... Grit of leads time channel switch Zw, the traffic from the voice multiplex rail Ms of the group of leads to multiplex rails other groups of connection lines or traffic within one and the same group of connection lines via buffer storage devices and connections to the signal receivers and central signal transmitters available to the group of connection lines in question. The input of the address generator WA.- is connected to a central control unit E belonging to the central control device SEZ 1. From this central control unit E, the address giver WA g receives information about which address it has to output in each case. Such an address comes from the output of the address generator WAg via a switch Siv belonging to the central control device SEZ 1 to a connecting rail, namely the connecting rail ASe, and from this via a further switch, namely the switch S14 ... S n4 to the input of the in the currently connected to the central control device SEZ 1 group Gr of connection lines contained circulating memory Uw, in which the addresses of the respectively involved in connections, from the speech multiplex rail of the relevant group of connection lines to multiplex rails of other groups of connection lines or to a traffic within one and the same Group of connecting lines enabling intermediate storage devices and connecting lines and the - addressers of the relevant group of connecting lines available - signal receivers available - and central signal transmitters each = are written in phase. If the switch (S 14 in group Gr 1) upstream of the input of the circulating memory Uw receives a signal enabling it to be transmitted from the unlocking circuit Gg belonging to the relevant group of connection lines, the signal from the central control device SEZ1 or from the one in the Central control device SEZ 1 contained -Addressengeber WA- each delivered address reach the input of the relevant group Gr of connecting lines belonging to the circular memory Uw.

The central control device SEZ1 now includes further devices available to all groups GY1 ... Grzz of connection lines; ' These devices are the central signal transmitters Wbz, F4, Bz: From these central signal transmitters, the signal transmitter WL9z gives the busy signal, the signal> ender Fz the dial tone and the signal transmitter Bz the busy signal. A single connecting rail AS8 is connected to the central signal transmitters Wbz, Fz, Bz. . . AS10 connected. The time channel switches Ziv 3, Zw 4 and Zw 5 belonging to the group Gr 1 of connection lines, the addresses of which can be written into the address circulation memory Uw belonging to this group Gr 1 of connection lines, are connected to these connection rails; In a corresponding manner, the time channel switches corresponding to these time channel holders Ziv in the other groups of connecting lines are connected to these connecting rails.

Zz between the central control device SEZ1 and all groups Gr 1 ... Gr of Anschlußfeitun (yen exist except the previously described compounds, other compounds. These include, of the water contained in the central control device SEZ 1 control unit E via corresponding connecting rails and Tiber in the individual groups respectively provided by the group-individual Entriegelungsschaltungen emitted in each case unlocking signals operable switch to the information contained in each group Gr 1 ... Grn of leads signal receivers Z! leading compounds which g in F i. 1, only two, namely BR x and Zi y . Via these connections, the control unit E contained in the central control device SEZ1 is supplied with the dialing information output by the subscribers setting up a connection and received by the group's own signal receivers; . These processes will be discussed further below in connection with the functional description of the FIG. 1 will be discussed in more detail.

A further connection now exists between the central control device SEZ 1 and all groups Gr 1 ... Gr> z of connecting lines; to a group-specific switch S15 ... Sfz5 connected to the outputs of the circulating memory Uw contained in the individual groups Grl ... Grn of connecting lines and which can comprise a number of individual lines corresponding to the number of bits forming a line address; a gate Gf designed as a NOR gate is connected to its inputs. "The gate Gf is designed as a transit memory runtime memory UI downstream of the transit time of the duration of a revolution cycle of the each of the addresses of the individual in en groups Grl ... Grn of leads to compounds involved leads containing circulating memory Ua and, as the, in each the duration @ äuch a circulation cycle of the Adressenümläufspeicher Vw corresponds; each address circular memory contained 1`iv has groups Grl ... Grn of leads a circulation cycle of equal duration.

The output signals emitted in each case by the transit time memory UI control the one input of an AND gate GU which has two inputs. The other input of this gate is supplied by the control unit E contained in the central control device SEZ 1, during certain periods of time, with a control signal which may lead to the unlocking of the AND gate. The output signals emitted in each case by the gate GU are used to actuate the aforementioned switches Sc and Sw, via which, as already mentioned; from the central control device SEZ 1 addresses are given to the individual groups Grl ... Grzz of connecting lines.

In order to interconnect the individual groups Gr l ... Gr zz of connecting lines one after the other with the central control device SEZ 1 , another; The address generator GAg, hereinafter referred to as the group address generator, is provided which, controlled by the control unit E, sequentially stores the individual groups Grl. . Grn gives group addresses identifying connecting lines. The group addresses given by the group address generator GAg are transferred to the connecting rail AS11; The unlocking circuits Ügl ... Ggzz contained in each of the groups Grl ... GYZZ of connecting lines are connected to this connecting rail with their inputs. As already stated at the beginning, each of these unlocking circuits Gg 1 ... Ggzz gives an output signal to the respective group Gr of connecting lines when an input signal formed by a certain bit combination occurs, ie when the group address identifying the relevant group Gr of connecting lines occurs included switch S. Since each unlocking Gg to another bit combination, that is a different group address, responds and emits an output signal, thus during the time period during which it is given a group address from the group address generator GAB, in each case only one group Gr of connecting lines with the central control device SEZl interconnected.

After the structure of the in F i g. 1 has been described to the extent necessary for further understanding, the function of the circuit arrangement shown in FIG. 1 illustrated circuit arrangement explained in more detail. For this purpose it is assumed that the group address generator GAg is outputting a new group address, for example the group address designating the group Gr1 of connecting lines, by a control signal output by the control unit E contained in the central control device SEZ1. As a result, the unlocking circuit Ggl belonging to the group Grl of connection lines emits a control signal which actuates the switch S11 ... S17 belonging to this group Gr1 of connection lines, so that the central control device SEZ1 is interconnected with the group Gr1 of connection lines. At a later point in time, in the course of cyclical switching of the group address generator GAg contained in the central control device SEZ1, a further group Gr of connection lines is connected to the central control device SEZ1 until finally the group Grl of connection lines is connected again to the central control device SEZ 1 . In the following, the state is first considered in which the group address generator GAg is currently outputting a group address designating the group Grl of connecting lines, the aim being to examine how the group Grl of connecting lines cooperates with the central control device SEZ1. For this purpose, it is assumed that the line address generator AG has also been advanced by one step through further control signals emitted by the control unit E, so that from now on it emits a new line address and all 1-bit memories Kl ... Km have been brought into their starting position and a delay element T has also been activated, the duration of which is equal to the cycle period with which the addresses written in the address circular memories Ua circulate, and whose output signal emitted after such a cycle period can be used to trigger control processes as described below.

For the duration of a period of circulation of the addresses written in the address circulation memory Ua of the group Gr1 of connection lines, a check is now carried out to determine whether and which addresses in their basic address part match the basic address given by the line address generator AG, that is to say, it is checked which of the addresses given by the line address generator AG connection lines of this group Grl of connection lines designated by this base address are involved in a connection or which of the connection lines of this group Grl of connection lines designated by this base address are not involved in a connection. Only if a connection line in this group of connection lines is not yet involved in a connection is it in an operating state that makes it necessary to check this connection line for its loop status from time to time and, if necessary, to carry out the necessary switching processes when a new connection request is established to handle. During the duration of the mentioned circulation period, every time an address that corresponds in its base address part with the base address supplied by the line address generator AG occurs at the output of the circulating address memory Ua contained in the group Grl of connection lines, an additional address part is then transferred to the decoder Ds via the switch Sa, which is then capable of transmission the memory device Spa contained in the central control device SEZ1, whereupon the decoder Ds a transition of the 1-bit memory of the 1-bit memory K1 assigned to this additional address part. . . Km from its initial state to its working state. After expiration of the period of revolution of the address circular memory Ua all written in the address circulation storage Ua addresses have been compared in their respective Grundadxessenteil with the just delivered base address, and there are now only have a 1-bit memory K1 ... Km in its initial state, the Associated address parts are not written into the circulating address memory Ua as part of an address whose basic address part corresponds to the basic address just sent by the line address generator AG. The connection lines identified by these latter additional address parts together with the base address just issued, which are thus not currently involved in a connection, should now be queried for their loop status in order to be able to identify new connection requests in this group Grl of connection lines. This now happens as follows: The 1-bit memories K1 ... Km , which have remained in their initial state, indicate the additional addresses of those connection lines identified by the current base address, which are to be checked for their loop status, in code 1 of m. As already mentioned, these additional address parts in code 1 of m are converted back into the original code by the coder Cs; the relevant additional address is then combined with the basic address still supplied by the line address generator AG as the address of a connection line of the group Grl of connection lines, which is to be queried for its loop status. The output circuit As, to which the encoder Cs belongs, has the effect that the additional addresses to be combined with the basic address output by the line address generator AG are output one after the other from the memory device Spa. The connection line Ts identified by such an address combined from a base address and an additional address is controlled via the decoder Da connected to the output of the memory device Spa and downstream of the address circulation memory Ga associated with the group Grl of connection lines.

Selected from the from the line address generator AG to be existed before supplied base address and the additional address respectively outputted by the encoder Cs node address is the input of the address circular memory Ua contained in the group Gr 1 of leads downstream decoder supplied Da via the switch Sc. The switch Sc was blocked by the control unit E contained in the central control device SEZ 1 during the period in which the basic address parts of the addresses written in the address circulating memory Ua of the group Grl of connection lines were compared with the basic address supplied by the line address generator AG; After the comparison time span has expired, ie after the cycle period T has elapsed, the control unit E emits an unlocking signal. This unlocking signal arrives at one input of the AND gate GU, which has two inputs and whose output signals, if any, make the switch Sc capable of transmission. In order to feed the subscriber address which can now be transmitted to the input of the decoder Da, which belongs to the group Grl of connecting lines, downstream of the decoder Da, a signal must also be fed to the second input of the AND gate GU. This signal is fed to the AND gate GU from the NOR gate Gf via the transit time memory Ul. The transit time memory Ul contains information obtained from the circulating address memory Uw provided in the group Grl of connection lines about the phase position of the pulses of control pulses intended for allocation to one connection but currently not allocated to connections in this group Grl of connection lines during the mentioned comparison period. As already mentioned, the addresses of time channel switches Zyv circulate in this circulating address memory Uw, via which multiplex rails GM leading to other groups Gr of connecting lines or to intermediate storage devices CO enabling traffic within the group Grl of connecting lines and the relevant group of connecting lines are available Signal receivers and central signal transmitters can be connected to the speech multiplex rail MS of this group Grl of connecting lines. By determining the phase positions with which no addresses are written in the circulating address memory Uw, information is also obtained at the same time about the phase positions with which no addresses are written in the circulating address memory Ua and thus, in a simple and advantageous manner, information about the phase position of the pulses from to the allocation a connection is provided in each case, but control pulses are not currently assigned to a connection in this group Gr1 of connecting lines, as will be explained in detail below. First, however, the observation that has already been started should be continued, according to which a pulse is just being emitted from the abovementioned transit time memory Ul, by means of which the AND gate GU emits an output pulse which makes the switch Sc capable of transmission. Thus, with the phase position of a control pulse that is provided for allocation to one connection in each case but is currently not allocated to a connection in the group Grl of connecting lines, the address combined from the base address output by the line address generator AG and one of the additional address parts stored in the memory device Spa is combined with an address Loop state to be interrogated connecting line to the input of the address circulation memory Ua of this group Grl of connecting lines downstream decoder Da . From the output of the decoder in question, Da , the relevant connection line of this group Grl of connection lines on its subscriber circuit Ts is then queried for its loop status. If a loop closure is found in the connection line, this means that the subscriber. to which this connection line belongs wants to establish a connection. Before the subscriber in question or his connection line, the facilities required to establish a connection, such. B. a digit receiver are assigned, it is first necessary to transmit the dialing start sign to the subscriber. However, the start of dialing characters may only be transmitted with the phase position of a pulse of a control pulse that is intended for allocation to a connection in each case, but not currently allocated to a connection, so that impairment of existing connections is avoided.

For this purpose, on the one hand, the address of the relevant connection line with the phase position of a pulse of a control pulse provided for allocation to one connection in each case, but currently not allocated to a connection in the group Gr1 of connection lines, is written into the circulating address memory Ua, and on the other hand, the phase position of the same is used Pulse of a control pulse provided for allocation to one connection in each case, but not currently allocated to a connection in the group Gr 1 of connection lines, the address of the start-of-dial generator Wbz which emits the start-of-dialing character is written into the circulating address memory Uw. The phase position of a pulse used for this purpose of a control pulse provided for allocation to one connection in each case, but not currently allocated to a connection in the group Grl of connection lines, can still be the same phase position with which the address of the connection line in question is connected to the input of the Circulating address memory Ua downstream decoder Da is supplied. However, it is also possible to write the address of the relevant connection line and the address of the dialing start character generator Wbz into the address recirculation memory Ua or Uw provided for this purpose with the phase position of another pulse of one provided for allocation to one connection in each case, but in the group Grl of connection lines control pulse currently not assigned to a connection as that pulse with whose phase position the address of the connection line to be interrogated was delivered to the input of the decoder Da. As already mentioned, the address which is to be written into the address circulation memory Uw with the phase position of the pulse in question of a control pulse intended for allocation to one connection, but currently not allocated to a connection in the group Gr 1 of connection lines, is assigned to the starting dial generator Wbz the address generator WAg controlled by the control unit E via the switch Sw. Since the switch Sw as well as the switch Sc is supplied with a signal enabling it to be transmitted by the AND gate GU , it is therefore provided in each case to the phase position of pulses from for allocation to one connection in each case, but in the group Grl of connection lines = Control pulses not currently assigned to connections can be transmitted. Thus, addresses are given to the group Grl of connecting lines simultaneously via the two switches Se and Sw.

= For a further explanation of the in F i g. 1 is now assumed that the address of a connection line, whose associated subscriber Tn would like to set up a connection, with the phase position of a certain control pulse in the address circulation memory Ua and that with. the phase position of the same control pulse in the address circulation memory Uw the address of the dial start character generator Wbz contained in the central control device SEZ1 to the speech multiplexing rail MS. switching switch Zw 3 rotates. As a result of the synchronous actuation of the time channel switch ZS or Zw connecting the relevant connection line and the dialing start sign generator Wbz to the speech multiplex rail MS , the relevant subscriber Tn thus receives the dialing start sign. If this subscriber now begins to dial, a signal receiver which receives the dialing information and which is referred to below as the signal receiving device ZE must be provided. This signal receiving device ZE is only assigned individually to the individual groups Gr of connecting lines; it contains, among other things, a number of signal or digit receivers Zix :. 'in the group Grl of connecting lines. Z! y, - which are used for the actual recording of the election information and which for this purpose can be connected to the speech multiplex rail MS via time channel switches Zw 1 ... Zw 2. The allocation of such a signal or digit receiver Z! is now carried out with the phase position of the control pulse with which the address of the relevant, -with the election beginning subscriber in the address circulation memory Ua circulates, in such a way that the finite phase position of the control pulse in the address circulation memory Uw circulating address of the to the The speech multiplex rail MS connected dialing character generator Wbz is replaced by the address of a digit receiver Zi or the time channel switch Zw connecting it to the speech multiplex rail MS. The implementation of these - processes takes place under the influence of the control unit E contained in the central control device SEZI, the provision of the addresses of the respective required devices (signal generators, signal receivers) by the already on corresponding information received from the subscriber line via the signal multiplex line YM mentioned; Initiates address giver WAg and enables the retrieval of the address provided in each case via the switch Siv. After the required selection information has been recorded and processed, the address of the time channel switch Zw that is relevant for the connection to be established to another group of connecting lines or to a group of memory devices C is finally written into the address circulating memory Uw with the phase position of the relevant control pulse 0 leading multiplex rail GM connects to the speech multiplex rail MS. It should be pointed out at this point; - that for the delivery of the addresses generated by the address generator WAg to the group Gr of connecting lines to be summed up with the central control device SEZ l. in the central control device, switches Sw contain only during the occurrence of the control pulses in question capable of transmission; must be, including additional, the transmission capability of this switch controlling, in F i g. 1, not further: control devices shown can be provided. For each connection to be set up in the direction going out from a subscriber of the group Grl -will -in the in FIG. 1 circuit arrangement shown -also with the phasing one and the same with control pulse: both- in the address circulation memory:;. Ua as well as in. The address circulating memory Uw each one address is written, so that with the - phase position of a -a connection allocated control pulse with which one address circulates in the address circulating memory Uw, always also in the address K circulating memory Ua . Address circulates. At vice. The reversed connection establishment direction is also with the phase position of one and the same control pulse `sö. probably -in dem_Adressenumlaufspeicher-Uw as well as in the address circulating memory Ua each written an address. In order to ensure for each connection to be established that the. If the control pulses to be allocated are not yet allocated to other connections, it is therefore possible to retrieve the information about the phase position of the pulses from one connection provided for allocation to each connection, in: the respective group Gr of connection lines but not currently allocated to a connection control pulses from only one the circulating memory -zu-win, as has been indicated above for the circulating memory Uw.

For a better understanding of the in F i g. 1, to summarize it again, the case was considered above; - that the line address generator AG contained in the central control device SEZ1 issued a base address common to a plurality of connecting lines and -that the addresses of those connecting lines designated by this base address which in a comparison carried out accordingly were determined not to be involved in a connection, each with the phase position of a pulse of a control pulse intended for allocation to one connection in each case, but not currently allocated to a connection in the relevant group of connection lines to query the relevant connection lines for their loop status' were issued. The addresses of the relevant connection lines were then either with the same phase position of the pulse. a control pulse provided for allocation to one connection in each case, but not currently allocated to a connection in the relevant group of connection lines, with which the address of the connection line in question was supplied to the input of the decoder Da downstream of this address circulation memory Ua, or with the phase position of a. Another impulse of one provided for allocation to one connection in each case, but momentarily in the relevant group of connection lines. not to write a connection allocated control pulse .in -to the relevant circulating address memory Ua. The combined address of a connection line, which consists of the basic address and additional address part, is used in the case under consideration is now issued until the switching processes required for the connection line in question have been completed on the basis of the query regarding its operating status; then further such combined addresses may be issued in a corresponding manner.

In the case of the in FIG. The circuit arrangement shown 1, it is now also possible to simultaneously Since enroll with the delivery of an address of a queried terminal line to the inputs of belonging to the respective group of leads decoder this address in the belonging to the relevant group of connection lines address circular memory Ua and the function of To delete the query result or to leave it in the circulating address memory. This is expediently done in such a way that an address written in the circulating address memory Ua provided in the respective group of connecting lines is erased by overwriting a further address of a connecting line to be interrogated in the relevant group of connecting lines. As already mentioned at the beginning, it is also possible to transfer an address pending at the output of the line address generator AG of a connection line to be interrogated in the relevant group of connection lines during the address comparison with the phase position of the first pulse of a connection provided for allocation to one connection in each case, but in then to write the control pulse currently not assigned to a connection to the group of connection lines in question in the circulating memory Ua belonging to the group of connection lines in question, with simultaneous marking of the pulse phase in question, if no address equality has been found up to then, in the further course of the address comparison, if an address equality occurs to store and after the end of the address comparison, the address occurring for the marked pulse phase at the circular memory output of the address in the relevant group of connecting lines, if necessary, is deducted ufragenden connecting line only if an occurrence of an address match is not stored, to be supplied as the address of a connecting line to be queried for the marked pulse phase to the input of the decoder Da provided in the relevant group of connecting lines and otherwise to be deleted, which makes it possible regardless of this whether to let make a new address from the line address generator AG, the address in question, which may be one of a plurality of leads common base address is already enrolled in the circulating memory Ua or not after each rotation cycle of enrolled in the relevant circular buffer Ua address or to operate a different group of connection lines.

If at the same time as the delivery of the address of a connection line to be interrogated to the input of the decoder belonging to the respective group of connection lines Since this address is written into the circular memory Ua connected to this decoder and, depending on the query result, is deleted or left in the circular memory Ua and while an address written in the circular memory Ua is deleted by overwriting a further address of a connection line to be interrogated in the relevant group of connection lines, the information about the phase position of each connection is provided for allocation to a respective connection, but not currently in the respective group of connection lines Control pulses assigned to a connection are expediently obtained from that circulating memory of the respective group of connection lines in which the addresses of the respective connections involved from the multiplex bus MS of the respective group the other of leads to multiplex rails GM groups of connection lines or a traffic within the same group of leads enabling temporary storage devices leading time channel switches Zw and the addresses of the relevant group of leads available signal receivers and central signal transmitters are each inscribed phase manner. In the circuit arrangement according to FIG. 1 this is the circulating memory Uw. To mark the phase position of such control pulses is shown in FIG. 1 of the central control device SEZ1 shown, the transit time memory U1 is provided, which can also be designed as a circulation memory with a circulation time corresponding to a circulation cycle of the circulation memories provided in the individual groups of connection lines.

If the operating process required for a connection line queried by connection lines in group Grl has been completed, the output circuit As contained in memory device Spa emits the additional address of a further connection line to be queried for its operating state in the relevant group Grl of connection lines which is pending combined with the basic address still pending from the line address generator AG at the switch Se. This switch Se is in turn, as described above, made transferable with the phase position of a pulse of a control pulse provided for allocation to one connection in each case, but currently not allocated to a connection in the relevant group of connection lines, whereby the now provided address of a control pulse in the relevant group of connecting lines to their operating state to be interrogated connecting lines is output to such a phase position. The subsequent processes are analogous to the processes described above, which is why they will not be discussed further here.

Are now completed each required switching procedures for those connecting lines whose addresses than with the central control device SEZ1 just interconnected group have not been determined enrolled of leads in the circulating memory Ua, it can from the line address generator AG another, a variety characteristic of leads Base address are issued, while the group address generator GAg continues to issue the previous group address. Preferably, however, in the case of the one shown in FIG. 1, proceeded in such a way that when corresponding connection lines of different groups of connection lines within the respective group of connection lines are designated by one and the same address of the line address generator AG, such connection lines designating address is issued during a period of time during which all groups of Connection lines are interconnected one after the other with the central control device and the connection lines of the individual groups of connection lines identified by this address are checked to see whether they are in an operating state that requires an operating process, and that further addresses are then output in a corresponding manner by the line address generator for querying further connection lines. This measure has the advantage, as already mentioned at the beginning, that the central control device SEZ1 is often interconnected with the individual groups of connection lines at regular, short intervals of time, for example in comparison to a successive query as a result, connection lines emitting information relating to the establishment and disconnection of connections in the individual groups of connection lines can receive such information at such short time intervals that they can receive all requests from there within the scope of the specified interconnection with the individual groups of connection lines Mediation processes, in particular the timely provision of election information recipients, can be sufficient; furthermore, group-specific storage devices that are otherwise to be provided for receiving electoral information are saved.

With regard to the in F i g. Central control device shown SE21 1 does this mean that the line address generator AG further outputs the given base address, but that now is discharged Gr of leads designating group address from the group address generator GAG a another group. As a result, an actuating signal for actuating the switch S belonging to the relevant group Gr of connecting lines is then fed via the unlocking circuit Gg to another group Gr of connecting lines, whereupon another group Gr of connecting lines is connected to the central control device SEZ1. The line address generator AG only emits a new base address indicating a different plurality of connection lines when the connection lines identified by the previously output base address in all groups Grl ... Grrc of connection lines have been queried for their operating status.

It is now the in F l g. 2 shown circuit arrangement considered in more detail. This circuit arrangement, which is like that in FIG. 1 shows an exemplary embodiment of a circuit arrangement for carrying out the method according to the invention in a time-division multiplex switching system which has connecting lines combined into groups. 1 shows, among other things, the peculiarity that here signal receivers serving to receive dialing information are not provided individually for groups, but centrally, for all groups of connecting lines together, in the central control device SEZ2. By replacing the group-specific signal receivers with a central signal receiving device, the one in FIG. Groups Gr1 ... Grn of connection lines belonging to the time division multiplex switching system shown in FIG. 2 only insofar as the time channel switches Ziv1, 2w2 which are connected to the speech multiplex rail MS of the respective group Gr of connection lines and lead to the signal receiving device directly to the switches S 16, S 17 ... S n 6, S n 7 are connected, which can be actuated by signals emitted by the unlocking device Gg belonging to the respective group Gr of connecting lines; For example, a connection leads from the speech multiplex rail MS of the group Gr 1 of connection lines via the time channel switch 2w 1 controllable by the decoder Dw to the switch S16, which can be made transferable by output signals emitted by the unlocking circuit Ggl.

After the structure of the in F i g. 2, apart from the difference that, compared to the circuit arrangement shown in FIG. 1, a central signal receiving device is provided here, corresponds to the structure of the circuit arrangement shown in FIG. 2 largely corresponds to the mode of operation of the circuit arrangement shown in FIG. 1, only an explanation of the circuit part which differs from the circuit arrangement shown in FIG. 1 is given below. As noted above, this circuit part is the central signal receiving device ZE2 contained in the central control device SEZ2. The in F i g. 2, the central signal receiving device 2E 2, shown only schematically, is connected on the input side to two connecting rails AS6, AS7 serving for the transmission of dialing information, via which respective dialing information is fed to it. This selection information reaches the actual signal receivers 2i x and Ziy via time channel switches Six and Si y contained in the signal receiving device 2E2. From these signal receivers 2i, the information required in each case to set up connections is fed to the control unit E contained in the central control device SEZ 2. To the one shown in FIG. 2 shown central control device SEZ 2 provided central signal receiving device 2E2 also lead to control lines, namely on the one hand from the address transmitter WAg, which outputs the addresses to be stored in the circular memory Uw of the group Gr of connecting lines connected to the central control device SEZ2, and on the other hand from the group address generator GAg which emits the respective group address.

After the structure of the in F i g. The central control device SEZ2 shown in FIG. 2 and containing a central digit receiving device 2E2 to the extent still required for further understanding, namely to the extent that deviations from the structure of the control device according to FIG The specifics of the function of this control device resulting therefrom are briefly explained. For this purpose, it is assumed that the actual signal receivers Zi contained in the central signal receiving device ZE2 and used for recording dialing information only receive dialing information given by one subscriber. For this purpose, the circuit arrangement according to FIG. 2 each signal receiver Zi is preceded by its own switch Si, which can be controlled by a memory device not shown in the drawing, which only outputs a signal that makes the relevant switch Si transferable when the group address generator GAg receives the group address of that group Gr is issued by connecting lines in which the connecting line of the relevant subscriber sending the dialing information is located. For each switch Si, this memory device can include a number of 1-bit memories corresponding to the number of groups Gr of connection lines, the operating position of which defines through which the group addresses output by the group address generator GAg can bring the relevant switch Si into the state of transmission capability. Before it is determined in this way with the aid of the switch Si when a signal receiver is activated in each case, such a signal receiver must first of all be assigned to the relevant subscriber providing dialing information. This can be done with the help of the address generator W'Ag, which optionally outputs the address of a signal receiver that is currently free, so that the required control of the switch Si connected upstream of the relevant signal receiver can be effected by storing this address in the memory device mentioned. The signal receivers Z! Upstream switches Si are thus made transferable when a certain group address issued by the group address generator GAg occurs, so that the relevant signal receiver Zi is controlled by a subscriber during the period during which the central control device SEZ2 is connected to the relevant group Gr of connecting lines Group Gr can receive dialing information given by connecting lines. Since every signal receiver Z! is connected via its own switch Si to its own connecting rail AS , to which only one time channel switch Zw leads from each group of connecting lines, and the address of one in a group Gr of connecting lines is a connection between the respective speech multiplex bus MS and one in the central Control device SEZ2 contained signal receiver Zi enabling time channel switch Zw is only written with the phase position of a single control pulse in the circulating address memory Uw belonging to the respective group Gr of connecting lines, it is ensured that the signal receiver Zi contained in the central signal receiving device ZE2 is assigned to only one participant are.

Then it should be noted that instead of the signal receivers which are used to receive dialing information and which are common to the individual groups of connecting lines and which receive the necessary dialing information from the respective group of connecting lines via switches operated by the group address generator GAg, for receiving Choice information the multiplex rails MS of the individual groups Gr1 ... Grn of connecting lines each via a time channel switch with the multiplex rail of a group of the individual groups Gr 1.. . Gr n common by connecting lines are connectible signal receivers, which also can be connected via a time channel switch on this multiplex rail respectively. A separate circular memory can be provided for this group of signal receivers, in which the addresses of the signal receivers currently assigned to a connection line circulate with that phase position with which the address of the respective connection line emitting dialing information in the connection line belonging to the respective group Gr of connection lines Circulating storage Ua circulates.

Using such a group of signal receivers then needs for the transmission of selection information in each of the to the in FIG. 2 belonging groups Gr1. . . In each case only a single connection line needs to be provided via a connection rail AS, which is controlled by the respective decoder Dw.

Claims (7)

Claims: 1. A method for querying connection lines for their operating status in a time division multiplex switching system comprising connection lines combined into groups, in which the individual groups of connection lines are controlled one after the other by a required switching process between connection lines of one and the same group or different groups of connection lines are, characterized in that the central control device (SEZ) with the help of a line address generator (AG) which successively generates the addresses of all the connection lines to be queried for their operating status, such addresses are associated with a group (Gr) of connection lines and one after the other with the central control device (SEZ ) interconnected, such addresses receive and the connecting lines designated by these addresses control devices (Da) emits that with each such control cause signals to be issued to the central control device (SEZ) which indicate the operating states present in the respective connection lines and may require operating processes. 2. The method according to claim 1, characterized in that when designating mutually corresponding connecting lines of different groups (Gr) of connecting lines within the respective group (Gr) of connecting lines by one and the same address of the line address generator (AG) such a connecting lines identifying address during one Time period during which all groups (Gr 1 ... Gr n) of connection lines are connected one after the other with the central control device (SEZ) and the connection lines of the individual groups (Grl ... Grn) identified by this address of connection lines are checked for it, whether they have an operating state that requires an operating process, and that the line address generator (AG) then outputs further addresses in a corresponding manner for interrogating further connection lines. 3. The method according to claim 1 or 2, characterized in that after a per se known comparison of an address generated by the line address generator (AG) with the addresses already written in one of the respective group (Gr) of connection lines belonging to the address recirculation memory (Ua) Connection lines involved in connections each have an address only for one connection line, the address of which has not yet been written into the relevant circulating address memory (Ua), as the address of a connection line to be interrogated at the inputs of the device controlling the connection lines belonging to the relevant group (Gr) of connection lines (Since) is delivered. 4. The method according to claim 1, '2 or 3, characterized in that an address of a connection line to be queried each with the phase position of a pulse of a connection provided for allocation to each connection, but currently not a connection in the relevant group (Gr) of connection lines assigned control pulse is supplied to the inputs of the device (Da) belonging to the respective group (Gr) of connecting lines. 5. The method according to claim 4, characterized in that one at the output of the line address generator (AG) pending address of a connection line to be queried with the phase position of the next pulse of a connection provided for allocation to each connection, but in the relevant group (Gr) of connection lines control pulse currently not assigned to a connection is transmitted to the inputs of the device (Da) belonging to the relevant group (Gr) of connecting lines. 6th Method according to claim 4 or 5, characterized in that with the phase position an impulse one intended for allocation to one connection in each case, but currently not a connection in the relevant group (Gr) of connecting lines assigned control pulse also on the basis of the query of a connection line their operational status required switching process in the group concerned (Gr) is handled by connecting lines. 7. The method according to claim 6, characterized in that such a switching process still with the phase position of the same pulse of a provided for allocation to a connection, but in the relevant group (Gr) of connecting lines currently not allocated to a connection control pulse with which the address the relevant connection line is supplied to the inputs of a decoder (Da) belonging to the relevant group (Gr) of connection lines and provided as a controlling device. B. The method according to claim 6 or 7, characterized in that such a switching process with the phase position of another pulse of a control pulse provided for allocation to one connection in each case but not currently allocated to a connection in the relevant group (Gr) of connection lines than that pulse , with the phase position of which the address of the connection line to be interrogated was supplied to the inputs of the decoder (Da) which belongs to the relevant group (Gr) of connection lines and is provided as the controlling device. 9. The method according to claim 8, characterized in that the switching process is handled with the phase position of the next pulse of a control pulse provided for allocation to one connection in each case, but not currently allocated to a connection in the relevant group (Gr) of connection lines. 10. The method according to any one of claims 6 to 9, characterized in that with the relevant phase position upon detection of a loop closure of the interrogated connection line not previously involved in a connection, the address of which is stored in the address circulation memory belonging to the respective group (Gr) of connection lines ( Among other things) is enrolled. 11. The method according to any one of claims 6 to 9, characterized in that simultaneously with the delivery of an address of a connection line to be interrogated to the inputs of the respective group (Gr) of connection lines belonging to the decoder (Da) provided as a controlling device, this address in the circulating address memory (Ua) belonging to the relevant group (Gr) of connection lines is written and, depending on the query result, is deleted or left in the circulating address memory (Ua). 12. The method according to claim 11, characterized in that an address written in the address circulation memory (Ua) belonging to the respective group (Gr) of connection lines is deleted by overwriting a further address of a connection line to be interrogated. 13. The method according to any one of claims 3 to 12, characterized in that after a comparison of a line address generator (AG) generated, each a plurality of connecting lines designating base address with the corresponding address parts of the currently in one to the respective group (Gr) of connecting lines associated address circulating memory (Ua), the addresses of all those connecting lines identified by the base address whose addresses are not yet written in the address circulating memory (Ua) belonging to the respective group (Gr) of connecting lines, one after the other as addresses of the connecting lines to be interrogated Connection lines of the respective group (Gr) .of connection lines each with the phase position of a pulse of a control pulse provided for allocation to one connection in each case, but not currently allocated to a connection in the respective group (Gr) of connection lines s are supplied to the inputs of the decoder (Da) belonging to the respective group (Gr) of connecting lines. 14. The method according to any one of claims 3 to 12, characterized in that after a comparison of a line address generator (AG) generated, each a plurality of connecting lines designating base address with the corresponding address parts of the already in one to the respective group (Gr) of connecting lines associated address circulating memory (Ua) each with only the address of a single one of those connecting lines designated by the base address, the addresses of which have not yet been written in the address circulating memory (Ua) belonging to the respective group (Gr) of connecting lines, as the address of a connecting line to be interrogated the phase position of a pulse of a control pulse provided for allocation to a respective connection but currently not allocated to a connection in the respective group (Gr) of connection lines to the inputs of the decod belonging to the respective group (Gr) of connection lines ers (Da) is delivered. 15. The method according to any one of claims 3 to 12, characterized in that after a comparison of a line address generator (AG) generated, each a plurality of connecting lines designating base address with the corresponding address parts of the already in one to the respective group (Gr) of connecting lines associated address circulation memory (Ua) only the addresses of preferred connection lines of those connection lines designated by the base address, the addresses of which have not yet been written in the address circulation memory (Ua) belonging to the respective group (Gr) of connection lines, as addresses of to be queried Connection lines each with the phase position of a pulse of a control pulse which is provided for allocation to a connection in each case but is currently not allocated to a connection in the respective group (Gr) of connection lines to the input of the to the relevant group (Gr) of Connection lines belonging to the decoder (Da) are supplied. 16. The method according to any one of claims 4 to 15, characterized in that the information about the phase position of the pulses of intended for allocation to a connection, but in the respective group (Gr) of connecting lines not currently allocated to a connection control pulses each from one provided in the respective group (Gr) of connection lines, the addresses of the respective connection lines involved in the connection, which are used to generate these control pulses, are obtained by determining the memory locations currently not occupied with addresses. 17. The method according to any one of claims 4 to 15, characterized in that the information about the phase position of the pulses of intended for allocation to a connection, but in the respective group (Gr) of connecting lines not currently allocated to a connection control pulses each from one Circulating address memory (Uw) can be obtained in which the addresses of those involved in connections, from the multiplex rail (MS) of the relevant group (Gr) of connection lines to multiplex rails of other groups (Gr) of connection lines or to traffic within one and the same group ( Gr) time channel switches (Zw) leading from connecting lines enabling intermediate storage devices (CO) and the signal receivers (Zi) and central signal transmitters (Wbz, Fz, Bz) available to the relevant group (Gr) of connecting lines are each written in phase. 18. The method according to claim 17, characterized in that this information is obtained from a circulating address memory (Uw) in which the addresses of those involved in each connection. from the multiplex rail (MS) of the relevant group (Gr) of connecting lines to multiplexing rails of other groups (Gr) of connecting lines or to a traffic within one and the same group (Gr) of connecting lines enabling buffer devices (CO) leading time channel switch (2w) and the addresses of all groups (Gr1 ... Grn) of connecting lines available central signal transmitters and receivers (Wbz, Fz, Bz and ZE2) are each written in correct phase. 19. The method according to any one of claims 4 to 18, characterized in that the phase positions of each intended for allocation to a connection, but in the respective group (Gr) of connecting lines not currently allocated to a connection control pulses in a special delay memory (U1) be marked. 20. The method according to claim 19, characterized in that in the transit time memory (U1) in each case the phase position of only a single control pulse provided for allocation to one connection, but not currently allocated to a connection in the respective group (Gr) of connection lines is marked. 21. The method according to claim 19, characterized in that in the delay memory (U1) in each case the phase position of all control pulses provided for allocation to one connection, but currently not allocated to a connection in the respective group (Gr) of connection lines is marked. 22. Circuit arrangement for carrying out the method according to claim 1 or 2, characterized by two connecting bars (AS3, AS1), to one of which on the one hand a connecting lines emitting the addresses for their operating state and provided in the central control device (SEZ) are connected to a line address generator (AG) and on the other hand, via a holder (S13 ... S n. 3), the connecting lines belonging to the individual groups (Gr 1 ... Gr n) of connecting lines which control the connecting lines. Devices (Da) are connected and to the second one on the one hand each via a switch (S11 ... Snl) the individual groups (Gr1 ... Grn) of connecting lines associated signals indicating the respective operating state of such exclusion lines indicating signal multiplex lines (YM) are connected and on the other hand, a control unit (E) which receives such signals and controls the respectively necessary switching processes and provided in the central control device (SEZ) is connected, and in that each group (Grl ... Grn) of connecting lines is connected to one of the aforementioned switches (S ) controlling unlocking circuit (Gg) is provided, which responds to a certain of the group addresses issued by a group address generator (GAg) and by unlocking the switch (S) contained in the relevant group (Gr) of connecting lines, interconnection of the relevant group (Gr ) from connecting lines to the central control device (SE Z) causes. 23. Circuit arrangement according to Artspruch 22, characterized in that the individual for receiving election information. Groups (Gr 1 ... Gr n) of connecting lines individually associated signal receivers (Zi) are provided, which receive the respective recorded dialing information during connections to the central control device (SEZ) to the control unit (E ) hand over. 24. A circuit arrangement according to claim 22, characterized in that the individual groups (Gr 1. ... Gr n) of connecting lines common signal receivers (Zix, Ziy) are provided in the central control device (SEZ2), which are transmitted via the from the group address generator (GAg) output addresses actuated switches (S 16, S 17 ... S n6, S n7) receive the required selection information from the respective group (Gr) of connecting lines. 25. Circuit arrangement according to claim 24, characterized in that the signal receivers (Zi x, Zi y ) contained in the central control device (SEZ2) are preceded by individual switches (Si x, Si y) with respective associated memory devices, into each of which the group addresses of Groups (Gr) of connecting lines containing dialing information emitting connecting lines are written in and which emit a signal which makes the associated switch (S1) capable of transmission with each occurrence of the relevant group address. 26. Circuit arrangement according to claim 22, characterized in that for receiving selection information, the multiplex rails (MS) of each group (Gr1... Grn) of leads each have a time channel switch with the multiplex rail of a group of the individual groups (Grl... Green) can be connected to common signal receivers by connecting lines, which can also be switched off on this multiplex rail via a time channel switch. 27. Circuit arrangement according to claim 26, characterized dadurali that for the group of signal receivers. a separate circulating memory is provided in which the addresses of the signal receivers currently assigned to a connection line circulate in each case with that phase position with which the address of the respective dialing information. supplying connection line in the one to the respective: Group (Gr). of .connection lines, associated circulating memory (Ua) circulates,. 28. Circuit arrangement according to a. of claims 22 to 27 for carrying out the method according to claims 3 and 4, characterized in that with the output of the line address generator (AG) and. the respective output of circulating address memories (Ua), each of which stores the addresses of the connection lines involved in the individual groups (Grl ... Grn) of connection lines on connections in the correct phase and each of which is followed by a decoder (Da) as the device controlling the connection lines Address comparator (Va) is connected, which in each case compares the address given by the line address generator (AG) with the addresses written in the address belt memory (Ua) belonging to the respective group (Gr) of connecting lines and which is followed by a storage device (Spa), in which at address equality a marking is effected in each case and one from the output of the line address generator (AG) provided for the one with the irr all groups (Gr l ... Gr n) of leads decoders (Da) together switchable connecting rail (AS 3) hinführendenSchalter (Sc ) controls in such a way that this only turns on if there is no it is transferable for the address output by the line address generator (AG) during an address comparison in the memory device (Spa) after the address comparison has ended. 29. Circuit arrangement according to claim 28, characterized by two further connecting bars (AS4, AS5) which on the one hand each have the addresses of the connecting lines in the relevant group (Gr) of connecting lines provided in all groups (Grl. .. Grn) of connecting lines Connections involved, from the multiplex rail (MS) of this group (Gr) of connecting lines to multiplexing rails of other groups of connecting lines or to a traffic within one and the same group (Gr) of connecting lines enabling intermediate storage devices (CO) leading time channel switches (Zw) containing circulating memories (Uw ) via switches (S14, S15 ... 8n4, Sn5) that can be operated by the addresses issued by the group address generator (GAg) and, on the other hand, with an address generator (WAg) that outputs the addresses to be written into these circular memories or with information about the phase position of the in the respective group (Gr) of connecting lines to the allocation ung an- each a connection provided but not currently assigned to a connection control pulses each receiving and temporarily storing runtime memory (U1) are connected, the output of which is connected to the control input of the after the end of the address comparison only if there is no during. the address comparison in the memory device (Spa) effected marking, the address transmitting switch (Sc) sent by the line address generator (AG) is connected. 30. Circuit arrangement according to claim 29, characterized in that the transit time memory (U1) is designed as a transit memory, the transit time of which is the duration of a circulation cycle containing the addresses of connecting lines involved in connections in the individual groups (Grl ... Grn) of connecting lines Circulating storage (Ua, Uw) corresponds. 31. A circuit arrangement according to claim 29, characterized in that the transit time memory (U1) is designed as a circulating memory, the circulating time of which is the duration of a circulating cycle containing the addresses of the connecting lines involved in connections in the individual groups (Grl ... Grn) of connecting lines Uumlaufspeicher (Ua, Uw) corresponds. 32. Circuit arrangement according to one of claims 22 to 31, characterized by a line address generator (AG) contained in the central control device (SEZ) and each emitting a base address common to a plurality of connection lines, by one to the output of the line address generator (AG) and the other Address recirculating memory (Ua) which stores the addresses of the respective connection lines involved in connections in the correct phase via switches (S12 ... Sn2) which can be actuated by addresses issued by the group address generator (GAg) connected to the address comparators in all groups (Grl ... Grn) of connection lines (Va), which has such a base address with the respective base address parts of the address circulation memory (Ua) written in the relevant group (Gr) of connection lines, each consisting of the base address part and additional address part of the addresses in this group (Gr) of connection lines ungen involved in connections compares connection lines, and by a memory device (Spa) with the possible additional address parts individually assigned memory locations (K), in which in each case if the same between the output from the line address generator (AG). Base address and the base address part of an address written in the address recirculating memory (Ua) belonging to the relevant group (Gr) of connecting lines, the additional address part of which causes the memory location (K) assigned to it to be marked and the base address supplied by the line address generator (AG) after comparison with the base address parts of all the addresses from at least one unmarked memory location (Ua) written in the relevant group (Gr) of connection lines from at least one unmarked memory location: (K) its associated additional address output and combined with the basic address supplied by the line address generator (AG) as the address of a connection line of the relevant group (Gr) of connecting lines to their query for their operating status at the input of the via a corresponding connecting rail (AS3) to the input of the decoder (Da) belonging to the relevant group (Gr) of connecting lines nden, is supplied in its transmission capacity by a switch (Sc) which is controlled by a switch (Sc) connected to the output of a circulating address memory (Uw) provided in the respective group (Gr) of connection lines. 33. Circuit arrangement according to claim 32, characterized in that such a combined address of a connection line is issued until the switching processes required for the connection line in question due to the query of this connection line for its operating state are ended, whereupon further, if necessary, in a corresponding manner such combined addresses are given. 34. Circuit arrangement according to claim 33, characterized in that after the completion of the switching processes to be processed for a connection line, a group (Gr) of connection lines interconnected with the central control device (SEZ) based on the query result, the memory location (K) assigned to the additional address part of an address the memory device (Spa) is also marked and the associated additional address is output from the next, unmarked memory location (K) and combined with the base address supplied by the line address generator (AG) as the address of a connection line to query its operating status at the input of the relevant Group (Gr) of connecting lines belonging decoder (Da), whose transmission capability is controlled by a gate (Gf) connected to the output of a circulating address memory (Uw) provided in the respective group (Gr) of connecting lines rs (Sc) is supplied. 35. Circuit arrangement according to one of claims 32 to 34, characterized in that the comparator (Va) controls a switch (Sa) via which, if the base address provided by the line address generator (AG) is equal, and the base address part of one in the group concerned (Gr) of connecting lines belonging address circulation memory (Ua) whose additional address part is fed to the input of a decoder (Ds) which consists of 1-bit memories (K1 ... Km), each of which is individually assigned to a possible additional address A memory is connected upstream, which in turn is followed by a coder (Cs) which, if necessary, outputs the additional address to be combined with the basic address supplied by the line address generator (AG). 36. Circuit arrangement according to one of claims 32 to 35, characterized in that the line address generator (AG) outputs the additional addresses of the relevant connection lines in addition to the basic address common to a plurality of connection lines, each of which is stored in its own memory location (K) of the memory device (Spa) and during the comparison between the base address output by the line address generator (AG) and the base address parts of the addresses written in the address circulating memory (Ua) belonging to the respective group (Gr) of connection lines are compared with their respective additional address parts and - with simultaneous base and additional address equality to mark the memory location (K).