DE1269198B - Circuit arrangement for dialing character transmission in a two-way, multichannel message transmission system - Google Patents

Description

Circuit arrangement for dialing character transmission in a two-way multichannel message transmission system Addendum to patent: 1230 069 The invention relates to a circuit arrangement for dialing character transmission in a two-way multichannel message transmission system, in which two trunk line end sets are connected via a four-wire voice band transmission device and each end set has a plurality of can send and receive independent data messages and provide corresponding hook switch states, with a plurality of narrow-band frequency multiplex channels derived from each half of the four-wire transmission device being provided, on which an independent data message is modulated in each of the long-distance line end sets, and with each end set of hook switch states being checked one after the other, in order to form a sequence of pulses representing these states, which is given in the time division multiplex method on a further channel, according to patent 1230 069 .

In the final set of carrier frequencies for a multi-channel data transmission network for use in connection with telephone transmission equipment are up to to six data channels together with a time division multiplex supervisory character channel in the Frequency division multiplexing combined.

The problem remains, however, of dialing characters, i. H. To transmit information that results from dialing a called telephone number from the calling to the called exchange and to give dialing progress signals and a dialing start signal from the called to the calling exchange. Dialing characters are usually generated in the form of DC pulses. However, as is well known, DC signals cannot be transmitted directly over trunk lines.

In known solutions to this problem, single-frequency and multi-frequency systems have been used. The single frequency system uses a pulsed on-off keying of either a 2400-11z or a 2600 Hz tone in the voice frequency band. The single-frequency signals are also transmitted in the form of on-off amplitude modulation with dial pulse speed in the order of ten pulses per second. Due to transient processes, it is not possible to increase the transmission speed to the value achieved according to the present invention.

In the multi-frequency system, on the other hand, combination pairs of odd multiples of 100 Hz between 700 and 1700 Hz are used. Accordingly, at least one third of the voice frequency band is required for the transmission of such signals. The multi-frequency system therefore does not match the narrow-band channels of the data transmission network. Rather, what is required is a dialing system that allows rapid operation and matches the bandwidth requirements and frequency distribution plan of the data trunking network.

To solve this problem, the invention is based on a system of the type mentioned and recommends that a large number of outgoing and incoming trunk circuits are connected to the trunk end sets, that the outgoing trunk circuit is connected to a known transmission register in which subscriber numbers in In the form of dialing digits, a coder is provided which checks successive digits of the dialing digits stored in the transmission register for the stored subscriber call numbers and forms a continuous sequence of pulses "the binary on and off determined in advance by a special start pulse code -Impulse contains that a modulator is provided which forms dialing characters in the form of a data message in response to the individual pulses of the pulse train, and that the fine line end set can transmit the dialing characters on the assigned data channel in response to the data message.

According to one embodiment of the invention, an outgoing transmitter circuit is arranged at the end of the calling remote speech exchange of a telephone telecommunication network and an input register at the called telephony exchange of a telephony trunk network in order to convert subscriber call numbers from a 2-out-of-6 parallel code into a synchronous 2-out -6 binary data sequence in serial form without loss of intermediate digit time and back again and to transmit the binary data sequence as a frequency-shifted coded signal. In addition, a single-frequency tone is returned from the called end of the transmission network as a dial start and error signal. The frequency shifted pulse train and the . Single-frequency tones are suitable for transmission in opposite directions over each of the narrow-band channels of the trunk line network.

The transmission circuit, which is an outgoing transmitter circuit of the in crossbar no. 5 switching systems includes a serial encoder and a modulator. The serial encoder alternately scans two groups of six lines each that emanate from the transmitter circuit. Each group of six lines contains an encoded dialing digit in the 2-of-6 parallel code. The encoder examines each group of transmitter lines in turn to form a serial binary data sequence with no spaces between digits. The encoder also prepares the data sequence, which represents a complete call number with a unique start identifier, which is given as the first digit by the transmitter. In order to achieve the maximum scanning speed, the encoder scans one group of digit lines while the transmitter circuit puts a new digit onto the other group of lines. The scanning process is precisely timed by a local clock source.

The modulator in the transmission circuit converts the binary data sequence from the encoder into a frequency-shifted signal whose center is on one frequency lies within the voice frequency band. The modulator contains a detector for the single-frequency dialing start character.

The receiver circuit assigned to an input register circuit comprises a demodulator, a serial decoder including a start flag detector and an error detector and a single frequency tone generator. The demodulator converts converting the incoming frequency shifted signals into a binary data sequence a splitting technique. The decoder processes the demodulated data sequence and forms DC digit representations in 2-of-6 parallel code on two alternating ones Groups of six lines each for connection to the register circuit. Included key signals are recovered from the data sequence to control and gate relays in the register circuit to control. It also does an error check for each digit carried out. The single-frequency tone generator is designed in such a way that it signals the start of dialing can send to the calling end of the trunk line network. The start of dialing character is until the complete dial number is registered. If no errors are found the signal at the end of the dialing number is removed. An error is caused by Continuation of the transmission of the sound is displayed.

The invention is described in detail below with reference to the drawings. It shows F i g. 1 is a high level block diagram of an embodiment bungs-pulse system in accordance with the invention of the frequency shift of particular 'alia benefit is F i g. 2 is a block diagram of the transmission side of the frequency shift pulse system according to the invention, FIG. 3 is a block diagram of the register or reception side of the frequency shift pulse system according to the invention, FIG Testing on the transmission side of the frequency shift pulse system according to the invention, FIG . 5 is a more detailed block diagram of the timing and decoding circuits on the receiving side of the frequency shift pulse system according to the invention, FIG . 6 is a diagram of the curve shapes to explain the function of the in FIG . 4, FIG . 7 a diagram of the curve forines to explain the function of the in FIG . 5 decoder shown.

General Fig. 1 shows as a block diagram an embodiment of the data transmission network according to the main patent, in which the frequency shift pulse system can be used with particular advantage for dialing signaling. The data trunking system contains the elements necessary to derive six narrowband data channels from a single four-wire telephone telecommunication facility. Such a device, shown here as a four-wire line 15 , enables independent east-west and west-east transmission between wireless exchanges. All elements to the left of the center of the FIG. 1 are advantageously arranged in a switch in the west and all elements on the right-hand side in a switch in the east.

Individual trunk lines 10 run to the left over a conventional two-wire telephone switching system (not shown) to a data subscriber station and each occupy a full voice band. Similarly, trunk lines 20 on the right lead to data subscriber stations or trunk lines via another conventional telephone switching system (not shown). Conventional trunk circuits (Ge telecommunication facilities are shown six) 11 and 17 connect to trunks 10 and 20, respectively. A composite monitoring signaling E and M is carried out via the line marked as a “monitoring connection”. The (calling) West Exchange is also assigned the outgoing transmitter circuit 13 , which operates all connection circuits 11 on request and which receives the information relating to the called subscriber number from a calling subscriber and converts this information into a form for establishing and controlling a connection to the called subscriber. The transmitter represents a common piece of equipment which can be connected via transmitter connection elements (not shown) under the control of a marker (not shown) to any trunk circuit that requests service via the line marked as a "dial-up connection". The dashed part of this line indicates the switching and control links. The (called) eastern exchange is assigned the input register circuit 18 , which receives the information relating to the called subscriber number and monitors the connection to the called subscriber. The register also represents a common piece of equipment which can be connected to each connecting line circuit via register connection elements (not shown) and via the line marked as a "dial-up connection"; the dashed part of this line indicates the switching and control links.

The data carrier frequency end sets 12 and 16 multiplex the frequency shift data characters from each trunk circuit into narrow frequency bands on the four-wire line 15. The lines labeled "voice connection" carry the data characters that are to be multiplexed. There is one for each trunk circuit. The term "voice connection" is only a superficial explanation and, strictly speaking, is only valid for viewing from the trunk circuit. It indicates the connection over which message signals are transmitted, since speech cannot be compressed into a frequency band with a width of 200 Hz with the current state of the art.

The data carrier frequency end sets 12 and 16 also derive a monitoring signal channel from the voice-frequency band of the line 15 , which is adjacent to the data channels and multiplexed information relating to the line status (on-hook and off-hook) in both directions. For this purpose, E and M line connections lead to each connection line circuit on the lines marked with "monitoring connection".

The data transmission network is intended to work with data facilities as they have already been proposed. At the calling end of a connection, these data devices work on 1170 Hz (so-called fl-band) and receive on 2125 Hz (so-called f2-band). At the called end of a connection, the data devices swap the bands and transmit on 2125 Hz and receive on 1170 Hz. Transmitter 13 and register 18 normally require the entire voice frequency band to transmit dial pulses and line characters. It is, however, an object of the invention to adapt the characters transmitted between the transmitter and the register to the nominal bandwidth of 200 Hz available in each channel of a multichannel data transmission network. As in Fig. 1, the transmitter 13 includes, for this reason a frequency shift pulse means 14 and the register 18 is a frequency shift receiver 19. This frequency shift units contain coding and decoding elements for processing complete phone number information as binary data sequences, wherein the marks and spaces as positive and negative frequency shifts by 100 Hz be carried by the nominal channel carrier frequencies of the data transmission network. In this way, the call number information can be sent independently of one another over the narrowband data channels during the connection setup time.

The outgoing transmitter 13 uses a high-speed control circuit in which digits to be emitted in pulse form appear in binary coded form on alternating line groups or rails.

The input register 18 uses the same control system with alternating rails for receiving incoming dialing digits as the transmitter. In addition, both the register and the transmitter perform all of the basic logic decisions and clocking functions of conventional registers and transmitters.

An identical transmitter can be placed on the east side and an identical register on the west side so that both the east and west end sentences can initiate calls. 'Frequenzverschiebungsünpulseiniichtung F i g. FIG. 2 is a block diagram of the circuit diagram in FIG. 1 as the frequency shift pulse means shown in block 14. The transmitter circuit 13 is shown only generally as a source of dialing characters transmitted over groups of parallel lines generally designated 22 and 23 at the command of the frequency shift pulse means. A progression character on the line designated ADY requires the alternating appearance of successive digits on lines 22 and 23. The frequency shift pulse device. consists of a serial encoder with test gates 24 and 25, output gates 26, a timer oscillator 27, a clock synchronizer 28 and em'em '. Clock generator 29, furthermore from a frequency shift modulator 30 and the smdefilter 31 assigned to it and finally from a return identifier with a filter 34 and a 'rectifier trigger 35. A directional connection between the modulator 30 and the character tone filter 34 to the lines 33 of the connecting line circuit' is made via a conventional fork gate 32 ' . The lines 33 represent a connection to a trunk circuit 11 in FIG. 1 for baseband signals to and from the data carrier frequency end sets. The lines 33 are shown in FIG. 1 generally as a dial-up connection. In the trunk circuit, the signals on lines 33 are passed to the "speech" trunks of the inter-exchange set, which may contain the data carrier frequency set, where conversion to the appropriate data channel is performed.

The Seriencodierer takes dial tone on the two groups of six lines 22 and 23 of the transmitter circuit and brings the information for the entire dial number in serial form; the serial information is scanned out synchronously by the oscillator modulator 30 at a rate of 200 bits per second in successive blocks of 6 bits per character. Each block contains 6 bit intervals of 5 milliseconds in duration, and by choosing the correct level for these bits (either earth for "one" or +5 volts for "zero") each digit from 0 to 9 and a number of special characters based on 2 -of-6 coded. The first character transmitted for each address is labeled KP in accordance with the nomenclature of multi-frequency signaling. The last character is labeled ST (start, since this signal starts the register for the free selection of a free connection line). It can consist of one of two characters, for example to indicate normal or special operation. Up to ten dialing digits can be transmitted, so that there can be up to twelve dialing digits. This corresponds to a pulse time of 0.36 seconds for a number with ten digits.

All characters are generated in the transmitter as stated in the main patent.

The code used in an actual running system is shown in the table below. It is similar to that used in multi-frequency pulse sensing systems. Bit-bit characters transmitted 1 to 10 7 to 10 position Evaluation 0 1 2 3 4 5 6 7 8 ST ST 1 0 xxxxx 2 1 xxxxxx 3 2 xxxxx 4 4 xxxxx 5 7 xxxxx 6 10 xxx An "x" in the table means earth or "one" in the special bit interval of a signal block with six intervals. According to the bit designation, each digit except zero (chosen arbitrarily) is obtained by adding the bit designations containing an earth signal. All characters except KP only need two bits. Only the characters KP and ST have a bit in the sixth position.

The KP character is unique and prepares the recipient for the incoming synchronous data sequence. The two characters ST indicate that all digits have ended. With the help of the two available characters ST , two different types of operation can be displayed.

The operation of the serial encoder is initiated when the transmitter circuit gives earth ("one") to the line ST. At this point in time, the continuously running clock oscillator 27 is applied with a 200 Hz square-wave output voltage to the clock synchronizer 28 , which has kept the clock 29 in the reset idle state. - When the clock 29 has started, it delivers test pulses to the even and odd test gates 24 and 25 and to the output gates 26. The test pulses bring the digit information on the parallel lines from the transmitter in serial form. The output gates couple the series information to the oscillator modulator 30.

The clock 29 also provides ADY signals to the transmitter so that each of the successive digits is put on the correct set of lines 22 or 23 . The first character (KP) is counted as a straight section (zero digit) and is always present at the transmitter on the overall raden group or rail lines. The following digits are accordingly odd or even. The oscillator modulator 30 receives the binary serial sequence from the output gates and converts it into a frequency shift symbol which deviates at the binary data rate by ± 100 Elz from a center frequency of 1170 Hz and which matches the frequencies used in the connection line circuit for data symbols. Therefore, the data carrier frequency end set can convert this character into the correct data channel as if it were message data. The oscillator modulator 30 can advantageously be a Hartley oscillator with a tank circuit in which an additional inductance can be switched on depending on whether the character bit to be transmitted is earth potential or positive to earth. The transmission filter 31 is conventional and restricts the frequencies in the output of the oscillator to the symbol band.

The character filter 34 and the rectifier trigger 35 together form a detector for a tone of 2025 Elz, which is returned by the register circuit as an alternating current dial start indicator on the basis of an off-hook signal from the calling office. The filter 34 is tuned to the expected frequency and may include a limiting amplifier. The output voltage of the filter is int rectifier trigger 35 with the aid of customary Licher means including the known Schmitt trigger rectified. The output represents either ground or an open circuit for the transmitter circuit on line F 2, depending on the presence or absence of the character tone.

The hybrid circuit 32 consists of a conventional transmitter with three windings and suitable simulations, which divides oppositely directed characters on a two-wire line into two one-way character paths without interfering with one another.

Frequency shift receiver F i g. 3 shows a simplified block diagram of a frequency shift receiver according to the invention and shows a practical embodiment of the block circuit 19 according to FIG. 1. The frequency shift receiver receives synchronously coded characters from the frequency shift pulse device according to FIG. 2 generated in the form of frequency-shifted coded signals from a trunk circuit, such as that at 17 in FIG. 1 and converts these signals into direct current pulses for actuating suitable relay combinations in a register circuit. The input of this receiver is via the in F i g. 1 line labeled "dial-up connection" and then connected via the internal connections of the connection line circuit to one of the "voice connection" lines at the east end of the inter-exchange transmission equipment, which can contain the data carrier frequency end set. A character tone generator controlled by the register circuit is also provided for backward signaling.

The frequency shift receiver according to FIG. 3 consists of a demodulator with a limiter discriminator 43, a separator 44 and an amplifier 45, furthermore of a series decoder with an error detector 46, a start detector 47, a synchronizer 48, an odd-even checking device 49, a timer source 50 with odd and Even call distributors 51 and 52 and furthermore from a character tone generator 41 and a hybrid circuit 40.

Characters from the connecting line circuit are given to the hybrid circuit 40 via the lines 55. The hybrid circuit 40 which corresponds to the hybrid circuit 32 in FIG. 2, separates incoming and outgoing characters in two separate paths and provides the former to the limiter discriminator 43. The input to the limiter consists of a frequency shift character in which 1270 Hz indicates a space or zero and 1070 Hz indicates a mark or one. The limiter part avoids amplitude fluctuations of the input symbol in a conventional manner. The discriminator part converts frequency changes into voltage fluctuations in any known manner. The discriminator can contain, for example, resonance circles for both the marking frequency and the spacing frequency. The output voltages of the resonance circuits are rectified and combined in such a way that they generate a positive voltage for an input frequency of 1270 Hz and a negative voltage for an input frequency of 1070 Hz. In this way, a clean square wave for application to the separator 44 is generated. The separator essentially locks this square wave to earth using the known Schmitt trigger. The output voltage of the isolating device accordingly consists of a square wave with a positive value for "zero" signals and earth for "one" signals. The amplifier 45 essentially represents a buffer arrangement for dividing the output voltage of the separating device to the error detector 46, the start detector 47, the synchronizer 48 and the odd-even checking device 49.

The serial decoder acted upon by the demodulator described above receives the synchronous binary data sequence at a rate of 200 bits per second. This data sequence is divided into two consecutive blocks, each of which contains six bit intervals of 5 milliseconds in duration. Each coded block represents a coded character with a duration of 30 milliseconds. For each bit interval, the data is in the marker or "one" state, which is indicated by earth potential, or in the distance or "zero" state, which is indicated by a positive voltage of 5 volts is indicated. The successive bit intervals are designated in accordance with the table above.

The functions of the serial decoder are: first, derivation of timer signals for controlling control and gate relays in the register circuit, so that the Digit information is given to the correct register location. Second, recovery the digit information in the synchronous binary data sequence from the demodulator and output of this information to the register circuit on alternating odd numbers and even groups of six lines as parallel DC signals. Third Check the data sequence for impermissible code characters.

The decoder is normally switched off until ground potential is applied to the RST line by the register circuit 18 after it has given a start of dialing signal to the transmitter circuit. The start detector 47 is excited as a result and searches for a marking state that lasts for at least 3.5 bit intervals. However, this property only has the character KP. Upon detection of this character, the detector 47 energizes the synchronizer 48 which progressively generates test pulses in the middle of each bit interval on the line SA. The synchronizer itself is synchronized by the spacing mark transitions at the end of the character KP and in the incoming data sequence. A further output voltage OS of the synchronizer is applied to the timer source 50, which generates control signals to control the odd and even call distributors 51 and 52 and to achieve the correct series-parallel allocation to the odd and even line groups 53 and 54. Another output voltage from the timer source is applied to the register at the end of each character on the ADV line so that it can read the correct odd or even digit. At the end of the complete number , the character ST is taken from the register, which separates the ground potential from the line RST and switches off the start detector 47 and the synchronizer 48.

Each character is checked in the error detector 46 for the presence of two and only two marker bits per character. If an error is detected during this test, an output voltage appears on the ER line, which informs the register of this error. The register is arranged to respond to this signal by turning off the character tone generator 41, provided that no error has been found in any digit of the dial number. In the event of an error, however, the character tone generator is not switched off, and the transmitter circuit interprets this as a sign to transmit the complete call number again. At the same time, in the event that an error has been indicated, the ground potential is switched off from the RST line, so that the decoder waits for another KP character and all storage relays in the register are reset. If an error is found on the second attempt, the register switches off the character tone generator, but detects the error and does not use the incorrect dial number. After the second error has been detected, the sender requests a new command.

The character tone generator 41 is a single frequency oscillator which can be connected to the connecting line circuit via the hybrid circuit 40 in a conventional manner. Serial encoder F i g. FIG. 4 shows a more detailed block diagram of an exemplary embodiment of the serial encoder which has already been described above generally in connection with FIG. 2 has been explained. The serial encoder advantageously uses functional logic transistor-resistor circuit units such as binary cells, monopulsers and coincidence gate circuits. The basic circuit unit is the coincidence gate using a single npn transistor whose emitter is grounded. The collector is connected to a positive voltage source via a load resistor. One or more input signals are applied to the base via isolating resistors. A positive voltage from any input saturates the transistor, thus grounding the collector. When all inputs are at ground potential, the transistor is blocked and the collector is at positive voltage. A single transistor with only one input can therefore serve as an inverter. A single transistor with multiple inputs can perform a negative AND or coincidence function that creates an output voltage when all inputs are open. The negative OR or buffer function can also be implemented, whereby the initial state is interpreted differently, i.e. h., the waste being an output voltage indicates that at least one input voltage is present. The gate circuits that satisfy either the negative AND or OR function are symbolized by a semicircle. The OR function is indicated by the fact that the lines extend into the interior of the semicircle.

A binary cell is created when two of the transistor gates just described are cross-coupled between collector and base and a diode pulse control network is added to the basic circuits so that negative-going pulses block the saturated transistor and reverse the state of the previously blocked transistor. The binary cell represents a circuit that divides by two when a continuous pulse train is applied to it. Such a cell is shown in FIG. 4 referred to as "binary circuit".

In these cells, additional input voltages can also be applied directly to each of the two base electrodes (independent of the control network). These input voltages are called set (S) and reset (R) voltages. The collector output voltages are arbitrarily designated with "one" (unprimed letters) and "zero" (primed letters).

A monopulser is a monostable multivibrator that produces an output pulse Preselected duration generated if it is corrected by an input pulse of correct polarity is triggered. It consists of two gate transistors with a capacitive coupling between the collector of one transistor and the base of the other transistor. The remaining collector and base electrodes are like the binary cell coupled to one another via a resistor. When triggered by a positive Pulse you get a positive output voltage at the collector of one transistor. The duration of the output voltage is determined by the value of the capacitor.

These logical units are well known and the above are brief The transistor exemplary embodiments described represent only one group of several for the execution of these units.

The oscillator 27 in the serial encoder according to FIG . 4 runs freely with a nominal frequency of 200 Hz. It contains an amplifier for converting into a square wave so that its output voltage has a square waveform. This oscillator defines the bit intervals of 5 milliseconds in which the conversation digits are coded. The oscillator output voltage is connected to the remaining parts of the encoder via a clock synchronizer, which includes the binary circuit 64, also denoted by G , and the coincidence or AND gates 62 and 63 .

The binary circuit G has a complementary input I and a reset input R and also complementary outputs G and U. Line A continuously supplies a diagram according to FIG . 6 shown square-wave output voltage A, which is applied to one input of the two gates 62 and 63 . Once handover of the transmitter circuit ground potential to the terminal 60 as a signal for the pulse-shaped waste created by Zifferninfixmationen, the gate 62 is partially energized and the binary circuit G reset, so that an output voltage G 'is ensured. The gate is fully excited by oscillator 27 on the next positive transition in wave A. The binary circuit G changes its state and the output voltage G ' blocks the gate 62 until the symbol ground potential SP is switched off. However, the changed output voltage G excites the remaining binary circuits and gates in the encoder. The gate 63 is also excited by the output voltage G , and the output voltage of the oscillator 27 is supplied to the clock circuits as wool B, the value of the wave A corresponding to FIG. 6, given.

The in F i g. 2 clock shown as block 29 consists of the four binary circuits 65 to 68, which are also designated for ease of reference to their complementary outputs with C, D, E and F, and the FB monopulser 70. Each binary circuit has one complementary input I and at least one reset input R. The binary circuit D has two independent reset inputs R1 and R2. The four binary cells and the feedback loop with the FB monopulser form a declining counting circuit. The cells are arranged in a chain so that an output of each higher order is connected to the complementary input of the next lower order, as in FIG. 4 shown. In addition, each reset input is controlled by output G of the clock synchronizer. The FB monopulser is acted upon by the output voltage of the coincidence gate 69 , the input voltages of which consist of the output voltages C, D and E 'of the binary circuits. The binary circuits would normally count to 16 without the monopulser, but the feedback from the FB monopulser to the reset input R 1 of the binary circuit D must be taken into account. This feedback causes the clock to repeat twelve cycles of the input shaft B in a known manner. F i g. Figure 6 shows that the waveform C is a continuous wave at half the frequency of wave B, while the waveform D is interrupted every other cycle. As shown, wave forms E and F are then one sixth and one twelfth the frequency of wave B.

The downward counting circuit does not respond to wave B until line G receives ground potential. The output voltages of binary circuits C, D and E control the odd and even test gates in a logical manner to be discussed below. The output voltage of the binary circuit F operates incremental relays (not shown) in the transmitter circuit, so that successive digits are given alternately on the even and odd line groups 22 and 23 .

The even and odd checking gate units 24 and 25, of which unit 24 is shown in detail, check the parallel coded digits on the digit lines from the transmitter and send them for output to the in FIG . 2 shown oscillator modulator 30 in series.

The even check gates 24, which are arranged in the box shown in dashed lines, comprise ten coincidence or AND gates 71 to 76 and 79 and 80 and the buffer or OR gates 77 and 78. The gates are arranged as shown to limit the number of input voltages for each gate and avoid overloading. The gates 71 to 76 receive their input voltages via connections to successive lines of the even line groove 22. Two additional inputs are supplied by the output voltages of the binary circuits C and D and are combined so that each of these gates is continuously energized alternately at successive intervals of 5 milliseconds . The gates 71 to 76 are energized one after the other and sequentially test the digit lines EV0 to EV10. The output voltages of each gate, for which the corresponding digit bit is earth potential, also consist of earth potential. The output voltages of the gates 71 to 73 are applied to the buffer gate 77 and the output voltages of the gates 74 to 76 are applied to the buffer gate 78 in that an inverted output signal is obtained.

A second pre-stage is provided by the coincidence gates 79 and 80 , the input voltages of which consist of the output voltages of corresponding buffer gates 77 and 78 . The gates 79 and 80 are alternately energized by the output voltages of the binary circuit E during each digit interval. They are excited by the output voltage F 'of the binary circuit F in alternating digit intervals. The second test stage increases the actual test repetition rate to twelve bits for each complete counting cycle.

The odd test gates 25 are connected to the odd line # group 23 from the transmitter and are identical to the even test gates 24 with the exception that the output gate pair corresponding to the gates 79 and 80 at alternating digit intervals through the output voltage F of the binary circuit F and not through the complementary output voltage F is excited.

The output voltages of both test groups are applied to the oscillator modulator via the buffer gate 81.

The state of the odd and even line groups from the transmitter is in the form of a diagram in the first twelve lines of FIG. 6 for a typical seven-digit dialing number 775-9971. The sender first creates the number KP as an even number. All lines except EV7 are at ground potential. The even lines are checked one after the other in gates 71 to 76 , determined by the selected output voltages of the binary circuits C and D applied to them. The first three gates are connected to the buffer gate 81 via the coincidence gate 79 , which is determined by the output voltage E. 'the binary circuit G is energized during the first three bit intervals. The last three gates are similarly connected to the buffer gate during the last three bit intervals via the coincidence gate 80 which is excited by the output voltage E of the binary circuit E. While the even lines are checked for the number KP, the first odd number is given to the odd line group. This digit is checked in the same way in the next digit interval by the odd check gates. The state of the binary circuit F has changed, and the second digit is given to the line group that is in progress. This process is repeated until the transmitter sends the digit ST to indicate that the complete call number has been transmitted. The complete data sequence is in the last line of FIG. 6 shown.

Transmitter Decoder The serial decoder of the frequency shift receiver is shown in more detail in the form of a functional block diagram in FIG . 5 shown. The decoder receives the demodulated data sequence from the demodulator according to F i, g. 3 via the buffer amplifier 45 on the data line. It processes the data sequence in order to recognize the number KP, to synchronize an internal clock generator and to distribute the encoded numbers to two groups of register input lines.

The serial decoder uses the same logic circuit units, like binary circuits, monopulsers and coincidence gates, which are also used in the serial encoder be used. In addition, a bistable multivibrator or a flip-flop circuit is used used. The flip-flop circuit is identical to the binary cell described above, however, the pulse control input arrangement is omitted. It contains separate Setting and reset inputs and only changes its state when the input voltage changes from one kind to another.

The in F ir g. 5 series decoder shown consists of a KP detector with the coincidence gate 90, the delay unit 91 and the flip-flop 92, further from the synchronizer with the monopulser 93, the coincidence gate 94, the oscillator 95 and the monopulser 96, further from a binary counter chain with the binary circuits 100 to 103, the coincidence gate 106 and the monopulser 107, from an error detection with the binary circuits 104 and 105, the coincidence gates 97, 98, 99 and 127, the monopulser 108 and the flip-flop 120, from the distributor 51 for odd digits, with the coincidence gates 121 to 126 and from a distributor 52 for even digits.

The figure KP, which leads the data sequence for each dialing number, is received on the data line from the demodulator and, together with the signal RST from the register, reaches the coincidence gate 90. The character M, which is also given to the gate 90 , blocks the gate when the The rest of the data sequence is checked. The gate is therefore effectively energized when the RST character is received from the register. It should be remembered that the figure KP is led by four marker bit intervals. The delay unit 91 integrates this interval and generates an output voltage if the awning input voltage is longer than 3.5 bit intervals. This is achieved in a simple and known manner with the aid of a resistance-capacitance-constant network. The RST signal is also used to reset the KP flip-flop 92 if it has not already been in this state. When the output voltage of the delay unit appears, it sets the KP flip-flop, thus energizing the coincidence gate 94. You. also switches off the reset character KV from the binary counters.

The clock is recovered from the data sequence by actuating the data monopulse 93 at each negative transition. The first transition occurs at the end of the CP pulse. The oscillator 95 is advantageously a free-running multivibrator which generates a square-wave output voltage. An output voltage of the data monopulser brings the oscillator multivibrator into a correct reference state, and it then continues to run freely with a new reference condition. The square-wave output voltage OS of the oscillator s95 is applied to the test pulse monopulser 96 in order to generate the test pulse SA for each oscillator cycle.

The oscillator 95 also supplies a drive voltage for the counting chain, which comprises the binary circuits A, B, C and, D in cascade. The oscillator 95 is connected to the complementary input of the binary circuit A. One output of each binary circuit is connected to the complementary input of the binary circuit of the next lower order. These binary circuits would normally count down by sixteen if the feedback arrangement with the monopulser107 between 'the output A' of the binary circuit A and the reset input R 2 of the binary circuit B were not present. This arrangement is similar to that in the encoder of FIG . 4, with the count chain being prematurely reset once for each cycle in order to perform a downward count of twelve instead of sixteen. The outputs of these four binary circuits are logically combined by the distributors for odd and even digits in such a way that they give test values of the data sequence to suitable storage relays in the register.

The distributors 51 and 52 for odd and even digits are essentially identical. It is just the odd digit distributor in FIG . 5 shown in full. It consists of six coincidence gates 121 to 126. The gates have outputs labeled 00, 01, 02, 04, 07 and 010 , which correspond to an output voltage on any of these lines leading into the register. See associated relative evaluation of a cocherten digit. from the other input voltages of the gate of the binary counters follows that each gate is energized sequentially for an interval of 5 milliseconds. F ig. 7 shows the waveforms of the output voltage of all the binary counter, and it turns out that these waveforms are similar to those of the serial encoder.

The data sequence. itself is given to the coincidence gates 109 and 110 , which are also excited alternately in each digit interval by the output voltages D and D 'of the binary circuit D. The output voltage SA of the test generator 96 is also given to these gates. An output voltage therefore appears for each marker or "one" data bit. The output voltage of gate 109 goes to distributor 51 for odd digits and the output voltage of gate 110 goes to distributor 52 for even digits. The gate 110 receives an additional input voltage from the output M of the flip-flop M, which prevents the distributor from responding to the number KP for even digits. The flip-flop M is set by the pulse KP and in this way energizes the gate 110 of the distributor for even digits and switches off the gate 90 of the KP digit detector.

The data sequence is also given to an error detector counting circuit via the coincidence gate 97 , which is also denoted CM. This detector contains two binary counters 104 and 105, which are also designated G and H for convenience. The binary circuit G is acted upon in its complementary input I by the data output voltage of the gate 97 , which is excited by the test pulse on the line SA and via a 3M gate 98 when both binary circuits are reset, which corresponds to their initial state. Both reset inputs R 2 are actuated when the figure KP is determined. The 3M gate has the usual reverse effect. The output voltage G 'of the binary circuit G acts on the complementary input of the binary circuit H. The binary circuits G and H can count up to four together. The first marking of the digit code represents the binary circuit G --in and has no effect on the binary circuit H. The second Mar-Idexung resets the binary circuit G and sets the binary circuit H. The output voltages C and H excite the 2M gate 99, the output voltage of which in turn excites the error gate 127. The gate 127 is checked at the end of each digit interval by a frame pulse FP from the F monopulse sex 108 , which generates a pulse with each setting of the binary circuit C in the counting sequence. This coincides with the end of the digit interval, as can be seen from the waveforms of FIG . 7 results. If no error occurs, the output voltage of error gate 127 is positive and the register interprets this as an indication that there is no error. The pulse, FP also resets both binary circuits at the inputs R 1 .

On the other hand, if binary circuits G and H count to three before pulse FP arrives, both binary circuits are set and gate 98 provides a blocking input to gate 97 and the counter output is held. The gate 127 then generates a ground potential output voltage when the pulse FP is applied. The register responds to this by switching off the RST signal, which resets the flip-flop KP and prevents further operations by the receiver. The register also continuously samples the character tone generator. The continuation of the character tone of 2025 IU for a time-determined interval after the transmission of the digit ST is indicated by the transmitter as. Request for retransmission of the complete dialing number interpreted. However, the frequency shift receiver will be deferred and begin looking for the digit KP as part of the retransmitted dial number.

This case is shown in FIG. 7 where the digit R + 1 has three marker bits. The error is indicated when the flip-flops M and KP are reset and an error output voltage is generated simultaneously with the pulse FP. The right, part of the waveforms shows the last three digits received on retransmission. The first five digits are received as before. The number K + 1 now contains two Maxkier bits. The tail bit-ST is received and given to the register. After the register has recognized the end of the call number, it switches off the RST signal, and the frequency shift pulse receiver is reset to its idle state. Line signaling In a multi-channel data transmission network, a new type of method for line signaling is made possible by the combination of the posting monitoring system described in the main patent with the frequency shift pulse system according to the invention. The special signaling combination significantly reduces the call setup time and leads to a more adaptable system. In addition, there is a requirement for an automatic repetition of the transmission of any number that does not stand up to a simple test at the called end of a trunk network.

The line character sequence described here enables the frequency shift pulse system to work with both telephone and data connection lines. Both hook switch states and in-band tones are used to transfer line characters between offices. The use of this character string significantly reduces the call setup time and the sender and register allocation time. It also enables a timely display in the event that offices at both ends of a double-directional. Remote connection line a simultaneous, try occupancy. In accordance with the currently usual method, the calling connection line goes off-hook when a call is initiated and the called connection line also goes off-hook to output a dialing start character. It is clear that in this system any trunk can be assumed to be originating a call. However , no register is switched on at either end of the connection and both calls are lost.

The string in case no error is displayed and, the case where an error is indicated shall be described.

In the error-free case, the calling trunk circuit at one end of the transmission device places an off-hook signal on the line M when it has gained access to a marker circuit. The signal on the line M is checked in the data carrier frequency end set and in the monitoring signal band in a time division multiplex sequence together with the status of other connecting lines connected to the same carrier frequency end set. transfer. At the called end of the transmission device, the character on line M is demodulated and a corresponding line E is grounded. In a departure from current practice, the called connection circuit remains in the on-hook state. However, it occupies a register. This immediately samples the tone generator assigned to it at 2025 Hz in the frequency shift receiver, as described above. As described, the 2025 Hz tone is recorded as the start of dialing character in the frequency shift pulse device assigned to the calling transmitter. The 2025-Elz tone replaces the DC off-hook signal from the called office that is currently used as the start of dialing code.

After a short time interval, the transmitter sends out the number in pulses and at the same time monitors the incoming 2025-11z tone. The register switches off the 2025 Hz tone on receipt of the digit ST at the end of the called subscriber number if no error has been displayed in any digit. The called V-connection line does not go off-hook until the called subscriber answers. The calling sender and the called register have both been released together.

In the event of an error, the character sequence is the same as just described, with the exception that after the digit ST has been determined by the register, the 2025 Hz tone is not switched off and the called connection line remains suspended. The transmitter expires after a predetermined interval following the digit ST and immediately repeats the transmission of the complete call number from the 7ifferKP to the digit ST. After receiving the newly transmitted dialing digits, the register switches off the 2025-1U tone on the second attempt. The transmitter is released when the hang-up signal is received in the calling trunk circuit on its line E. In the case of related errors, further timers in the transmitter and register may cause the connection line to issue a new command in accordance with the usual procedures. Protection against simultaneous seizure is ensured by the fact that only the calling connection line goes off-hook during the call setup interval. When both trunk circuits. go off-hook at the same time, a simultaneous occupancy is immediately detected in each connection line. Action can then be taken to capture at least one, and possibly both, calls before either of the markers is released.

The invention has been described with respect to a specific embodiment of a narrow-band data trunk line network. For a person skilled in the art, however, it is clear that the invention can generally be used for the rapid transmission of selected remote telephony digits over any trunk lines, regardless of whether the trunk lines are narrow-band or for the full voice band.

Claims (4)

Claims: 1. Circuit arrangement for dialing character transmission in a two-way multichannel message transmission system, in which two long-distance line end sets are connected via a four-wire voice band transmission device and each end set can send and receive a large number of independent data messages and provides corresponding GabeI switch states, with a multitude of narrow-handed ones , frequency multiplex channels derived from each half of the four-wire transmission device are provided, to which an independent data message is modulated in each of the trunk end sets, and hook switch states are checked one after the other in each end set in order to form a sequence of pulses representing these states, which in the time division multiplexing on a further channel is given, according to patent 1230069, characterized in that a large number of outgoing (11) and incoming (17) trunk circuits each to the F & -nleit ungsendsätze (12, 16) is switched on, that the outgoing connection line circuit (11) is connected to a known transmission register (13) in which subscriber numbers are stored in the form of dialing digits that a coder (14) is provided, which is based on the stored Participate-ufnumnier toward successive digits of the data stored in the transmission register (13) Wählziffem checks and forms a continuous sequence of pulses containing binary, by a particular in start pulse code determined in advance on and off pulses that a modulator (30) is provided, which forms dialing characters in the form of a data message in response to the individual pulses of the pulse train, and that the long-distance line end set (12) the dialing characters in response to the data message. can transmit on the assigned data channel. 2. Circuit arrangement according spoke 1, characterized in that is on the incoming trunk circuit (17) to a loading kanntes se input register (17) that leg demodulator to the received dial tone in the form of a data message, a binary (43, 44) Forms pulse train and that a decoder (49) is provided, which stores the dialing digits of the subscriber number in the input register on the pulse train. 3. Circuit arrangement according to claim 2, characterized in that the decoder (49) contains a test arrangement (46) which is responsive to the decoded digits. Registration of an invalid number in the entry register prevented and causes the transmission register to retransmit the dialing characters. 4. Circuit arrangement according to claim 2, characterized in that the decoder (49) contains a start detector (47) which reacts to the first digit of the pulse train responds and transmits a character to the encoder (14) until the complete subscriber number transfer. is.