DE1266350B - Circuit for a presettable counter that is counted forward in a binary code from the preset value to a limit value - Google Patents

Description

Circuit for a presettable counter that is counted up in a binary code from the preset value to a limit value. It is known to count a presettable number n (0: 9 n <N) of steps or intervals with the help of a counter that Counter content is set to count up by counting pulses and emits a signal when it has reached the highest possible count for its number of digits. Usually, it is ensured that the counter is initially stopped after it has reached its maximum level. In the case of a purely binary way of counting the counter, it must have at least as many stages - let their number be p - as are necessary for the binary representation of the value N + 1; the highest count is reached when all levels are on "L". The presetting can be effected in that the binary elements, e.g. B. flip-flops, the counter stages can be controlled individually via setting inputs from a transmitter that sets the selected elements to the desired binary value.

The invention now seeks to construct a counter of the aforementioned type in such a way that the internal counting connections of the counter and the transmitter devices required for the presetting become particularly simple. Such a simplification can - except in the cases where the number N is a power of 2 reduced by 1 - be achieved according to the invention in such a way that the binary elements or flip-flops of the lower p - 1 stages of the counter are in normal binary frequency divider circuit, on the other hand that the highest level can only be switched from 0 to L from the penultimate level and that means are provided to automatically supply a counting pulse to the lowest counter level after the counter has been set to the limit value.

May this be an example with reference to the drawing explain in more detail.

In the circuit diagram of the drawing, four bistable flip-flops F1, F2, F3, F4 form the four stages of a counter.

The table below the circuit diagram shows the positions that the counter should assume. These are the nine counter positions "8" to "0" entered from top to bottom, which can be preset so that the counter can execute a maximum of eight steps by counting impulses given to the input of stage Fl in the forward direction, i.e. the table values downwards can until it reaches its end position LLLL. The digits on the left in the table indicate the number of steps that the counter carries out in order to get from the relevant line to the end position. It can be seen that the counter positions, read from top to bottom, are numerical values 7 to 15 shown in the binary system.

To produce these counter positions, the circuit works as follows: The flip-flops F1 to F3 work in JK mode, i. In other words, they change their position when an "L" is applied to both inputs at the same time. The drawing shows the positions that the flip-flops have when the counter is in the rest position. The partially hatched lower fields indicate the logical meaning of this position.

If the other input A is set to "L" at an AND gate TE, at one input of which a continuously running counting pulse tl Regt, the counting pulses or the correspondingly clocked logic value L reach both inputs 1 and 1 'of the first flip -Flops Fl; this changes its position with each impulse. By connecting the one output al of Fl with both inputs 2 and 2 'of the flip-flop F2, this flip-flop changes its position after every second input pulse or, in other words, every time the flip-flop FI is in the position shown tilts back. Correspondingly, the one output a2 of F2 is connected to the inputs 3 and 3 'of the flip-flop F3 , i. That is, F3 changes position when F2 tilts back into the position shown, and that would be with the assumed starting position of the counter after the fourth input pulse. The flip-flops F1 to F3 are therefore in a normal binary frequency divider circuit for the counting process.

The one output a3 of F3, however, is only at a set input 4 of the flip-flop F4, via which, when F3 is reset, the flip-flop F4 changes position if and only if it was previously at logic "0" . After the counter has taken the position according to line 1 of the table, it reaches the end position LLLL of line 0 with the next counting pulse going into the input via gate TE. This end position has the advantage that only a single flip-flop is required to reach it , namely the "fastest" flip-flop in the form of the input flip-flop Fl, which is knocked over immediately by an incoming counting pulse, must be switched. The AND gate TA located at the b outputs of all flip-flops responds very quickly when the counter reaches the end position LLLL.

The control device, which ensures that a counting process takes place when the logic value "L" is applied to input A , and which can be organized differently depending on the use of the counter, is designed for the present purpose in each case so that, after reaching the counter end position LLLL still allows a counting pulse or a clock edge active for counting to pass through the gate TE to the inputs 1 and l 'of the flip-flop Fl. This sets FI to "0", thus also F2 and thus also F3. F4, however, remains in the "L" position, so that the already mentioned rest position of the counter results from line 7 of the table.

This rest position, which is reached with a normal counting pulse to the input of the counter, which is internally extremely simply switched, has the advantage, on the other hand, that the counter can be preset with very simple means based on it. And gates T1 to T4 are provided, which, clocked with a clock pulse t2, forward a logic value "L" applied to the other input B or C or D or E. Gate T1 is connected to set input 1 of F1, gate T2 to set input 2 of F2 and gate T3 to set input 3 of F3. In contrast, gate T4 is connected to the reset input 4 'of F4. It can be seen from the table that the Fhp-Flop F4 via gate T4 is only set in one single case of the possible default settings, namely to default the line # step number A " , namely must be reset to" 0 ", stands for all other default settings it is already at the correct value when the counter is reset. On the other hand, since the flip-flops F1 to F3 are in the basic position at "0" , only individual ones of these flip-flops have to be set to "L" to preset these levels.

If the maximum number N of counter steps up to the end position #, i.e. the number N + 1 of possible counter positions, is to be greater than described above, the table given on the drawing sheet can be expanded by adding more lines at the top corresponding to the binary values »6«, » 5 ", " 4 "etc. can be increased as preset values. The stated advantages continue to apply with a gradual gradation and only no longer exist if the number of counter digits used is a power of 2. In this case, the circuit complexity is essentially the same if the counter is allowed to switch back from the maximum value LLLL (...) normally to 0000 (...) .

Claims (1)

Claim: Circuit for a presettable counter, which is counted up in a binary code from the preset value to a limit value under the effect of counting pulses and then reaches an idle position for counting n steps (0 < n : #g N) has a number p of counter stages, as required by the purely binary coding of N + 1 , and the maximum binary value that can be set in these stages is the limit value, characterized in that the binary elements (flip-flops Fl ... F3) of the lower p - 1 Levels of the counter are in a normal binary frequency divider circuit, whereas the highest level (F4) can only be switched from "0" to "L" from the penultimate level and that means are provided to switch to the lowest counter level after the counter has been set To automatically add a counting pulse to the limit value.