DE1263832B - Arrangement for converting a pure binary code into a binary decimal code - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. Cl .:

H 03 k

German class: 21 al -36/20

Number: 1 263 832

File number: St 23816 VIII a / 21 al

Filing date: May 13, 1965

Open date: March 21, 1968

Digital technology is increasingly being used in the development of new navigation systems. In order to transmit angular values by radio with the lowest possible number of pulses get by, which also has a high angular resolution and frequent output stages with a low duty cycle Allows information renewal, one uses a less redundant code, z. B. the pure Binary code that is secured with a few test steps. However, this code usually has to be used for evaluation to be converted into the appropriate binary coded decimal values, for which most data processing machines are designed and which allow a numeric display in a simple manner. Particularly A simple structure of such a code converter is very important for on-board devices. This code implementation is not limited to navigation systems, but can be used wherever digital information needs to be converted.

The invention is based on the object of an arrangement for converting a pure binary code in creating a binary decimal code that is very simple. According to the invention, this is thereby achieved achieves that a first binary counter is provided, the counter reading with the binary input signal is compared in a basically known comparison device that the counter according to the Comparison is set via a clock to the value of the binary signal present and that A decimal counter is provided in parallel to this first counter as a second counter, the coding of which is arbitrary (z. B. 8-4-2-1 or 4-2-2-1), and that the setting pulses for the first counter also the second Counters are supplied, whereby pulses in a fixed sequence are suppressed or replaced by logic circuits. are fed to other counter inputs in such a way that the difference between the binary and decadic series of numbers resulting error is kept within specified limits.

According to a further embodiment of the invention, the comparison device contains two comparison circuits, one of which checks the more significant digits and the other checks the less significant digits, and if there is an inequality in the more significant digits, the setting pulses for the first counter are applied to a more significant digit. This has the particular advantage that the setting is quicker. Advantageously, auxiliary counters are provided as logic circuits for suppressing pulses, which only pass on every «th pulse, or the criterion for suppressing a pulse is derived from the position of the arrangement for converting a pure one
Binary code to binary decimal code

Applicant:

Standard Elektrik Lorenz Aktiengesellschaft,
7000 Stuttgart-Zuffenhausen. "
Hellmuth-Hirth-Str. 42

Named as inventor::

Dipl.-Ing. Manfred Böhm, 7120 Bietigheim

decimal counter itself derived. To make the comparison circuits and the counters simpler to be able to, according to the invention, when an inequality occurs, the counters are reset and only then controlled to equality. In the comparison device there is no need to distinguish between whether the count is higher or lower, and the counters do not have to switch to up or down be set up. In addition, counting errors cannot accumulate.

The invention will now be explained in more detail using the exemplary embodiment shown in the drawing.

If a digital signal with ten digits is used to resolve an angular range of 360 °, then the entire angular range can be broken down ^{into 2 10 = 1024 parts.} Each angle value can therefore be represented in coded form with an error of 360 °: 1024 = ± 21.0936 '.

If you want to achieve a resolution with an error of = 0.1 °, you have to use twelve digits work. The coding error of any angle is now ± 360 °: 4096 = ± 5.2734 '.

In the selected exemplary embodiment, twelve digits are used.

The binary signal present at input E is used in the basically known comparators VgIl'und Vgl! compared with the position of the binary counter Z: The comparator Vgl! the eight more significant digits are checked and the four less significant digits are checked with the comparator cf. If an inequality is found in a comparator, a criterion is output which actuates the control circuit ST via the OR circuit 0 1. In this control circuit, when such a criterion occurs, first the

809 519/568

All counters are reset via the lines Rü and then the clock generator TG is started. If the comparator VgIt was also activated when the inequality was determined, i. H. If the inequality was only in one of the four lowest digits, then as a result of resetting the counter when a large binary signal is present, the comparator Vgl! appeals to. This comparator switches the gate circuit gate so that the pulses from the clock through the OR circuit O 2 get equal to the counter position of the counter Z 2 ^2. At the same time, these pulses are sent to a three-digit auxiliary counter HZ1 and a two-digit auxiliary counter HZ2 . After every third pulse, the auxiliary counter HZ2 receives a pulse via the AND circuit U2 , which reaches the decade D 2 (one-decade) of the decade counter DZ via the OR circuit 06 and advances it by one unit. This pulse resets the auxiliary counter HZ2 via a delay device V and the OR circuit O 4 and can again count three pulses. After every fifth pulse from the clock, the auxiliary counter HZl receives a pulse via the AND circuit Ul and the OR circuit 03, which reaches the counter decade Dl (0.1 decade) of the decade counter DZ . At the same time, this auxiliary counter is reset again via the OR circuit 05. After every fifth correction pulse via the OR circuit 03 to the decade Dl , the pulse suppressor PU is actuated via the AND circuit U3 , which suppresses the next, the sixth correction pulse.

After eleven correction pulses, ten of which have come to the decade Dl, this is via the OR circuit 06 a pulse to the decade D 2. The binary working in itself decade counter are shown only schematically; the details required for the delivery of a pulse after ten input pulses and for resetting are assumed to be known and have therefore not been shown. The type of code is arbitrary and depends solely on the structure of the decade counter. The 8-4-2-1 code is shown.

When the eight more significant digits of the counter Z match the corresponding digits of the input signal E , the comparator Vgl2 no longer emits a signal, and the control circuit ST is kept actuated only via the comparator Vgl1. Since the criterion from the comparator Vgl2 is missing, the gate circuit Tor is now switched so that the pulses from the clock to the last digit (2 °) and via a delay element V to the OR circuit O 3 and from there via the pulse suppressor PU to the decade Dl arrive.

At the same time, the AND circuit U2 is blocked so that no more pulses can be delivered to the decade D 2. When the last four digits are set, the auxiliary counter HZl is also actuated via the OR circuit 02 and, depending on its setting, emits a maximum of one pulse to the decade Dl . If the last four digits are also the same, the arrangement is stopped by the comparator VgIl , and the position of the decimal counter DZ can be displayed or further processed in the desired manner.

The following errors occur in this way of working. Before the gate switchover by the comparator Vgl2 , each counting pulse is weighted with 21.0936 '. After every third pulse, 1 ° is counted into the decade counter. An error of 3 · 1.0936 '= 3.2808' thus occurs. This error is corrected by a correction pulse reaching the last decade (D 1) of the decade counter after every five pulses.

The correction pulse has the value 5-1.0936 '= 5.4680', eleven of these pulses then have the value 60.148 '. Since after every eleventh correction impulse the last decade sends an impulse to decade D 2 , an error of -0.148 'arises. A maximum of counting pulses are required to fill the binary counter up to the eighth digit. This results in 1020/5 = 204 correction pulses and 204/11 ^ 18 1 "pulses. The maximum error is therefore 18 · 0.148 '^ -2.7'.

After switching the gate, each counting pulse is evaluated with 5.2734 '. For complete replenishment the last four digits require a maximum of fifteen pulses. After eleven pulses, a "-Pulse delivered from the last decade, although eleven impulses only correspond to 58 ' Error of +2 '.

The third source of error is the last decade of the decade counter. It receives eleven pulses before emitting an output pulse. The pulses are somewhat different from one another, depending on whether they are correction or counting pulses. The largest display error in this decade is +3.6 'or —2.8'. The total error occurring during the conversion is thus between 5.6 'and -5.5'. With a 10-bit signal this results in an error of about ^ z ¹ UBk and with a 12-bit signal a maximum error of about ± 1 bit.

Claims (5)

Patent claims: 1. Arrangement for converting a pure binary code into a binary-decimal code, characterized in that a first binary counter (Z) is provided, the counter reading of which with the binary input signal (E) in a basically known comparison device (VgIl, Vgl2 ) is compared, that the counter is set according to the comparison via a clock (TG) to the value of the binary signal present and that parallel to this first counter (Z), a decimal counter (DZ) is provided as the second counter, the coding of which is arbitrary , and that the setting pulses for the first counter are also fed to the second counter, with logic circuits (HZ1, HZ2, PU) suppressing pulses in a fixed sequence or feeding other counter inputs in such a way that they see from the difference between the binary and decadic Series of numbers resulting error is kept within specified limits. 2. Arrangement according to claim 1, characterized in that the comparison device contains two comparison circuits, one of which (Vgl2) the more significant digits and the other (VgIl) checks the less significant digits, and that if there is an inequality in the more significant digits, the setting pulses for the first counter (Z) can be applied to a higher-order position (V) . 3. Arrangement according to claim 1, characterized in that auxiliary counters (HZl, HZ2) are provided as logic circuits for suppressing pulses, which only pass on every κ-th pulse. 4. Arrangement according to claim 1, characterized in that the criterion for suppression of a specific correction pulse derived from the position of the decimal counter (Z> 1) itself will. 5. Arrangement according to claim 1, characterized in that the counter is reset in the comparison device and only then controlled until equality will. Considered publications: indicates that if an inequality occurs, German Auslegeschrift No. 1152 441. 1 sheet of drawings 809 519/568 3.68 © Bundesdruckerei Berlin