DE1253321B - Circuit arrangement for controlling the input and output of buffer memories - Google Patents

Description

Circuit arrangement for controlling the input and output of buffer memories The invention relates to a circuit arrangement for controlling input and output of buffers in which the order of input and output is the same, but the time of input and output depends on various external events, preferably for memory counters.

In the case of numerical encoders, it is known to store and remove the in Entered in the form of multi-digit series of digits and corresponding in the form of these digits To record the information to be saved in multi-digit memory, in which each digit of a specific digit of the relevant overall information is equivalent to. The order in which this information is stored is also known by switching means, such as counting magnets or counting chains, to control the input and also automatically advance by one step when saving.

These switching means are expensive and their switching speed is not always high enough to meet today's requirements.

The invention is based on the task of reducing the effort in the individual Reduce buffers and provide for one common for several buffers To create control device that can only be occupied by one buffer memory at the same time and is only occupied for a very short period of time, and the input and / or output of those to be recorded or recorded in the digit memories Information controls.

The invention achieves this by having storage elements in each buffer memory arranged as position marker for input or as position marker for output are, whose switching state (charge state) determines at which point a multi-digit memory, the next digit is to be written in or from which Place in the multi-digit memory, the next digit is to be saved, and that in a common control device for several buffer memories switching means are arranged, which corresponds to each occupancy by a buffer memory the marking of the position marker of this buffer memory can be set and control the desired input or output and after performing the desired Input or output the switching status (charge status) of the corresponding position marker change so that the in the order of input or. Output of the next buffer storage location is preset.

This applies to numbers with a maximum of ten digits. If phone numbers with more than ten digits are to be selected, then the switching status (charge status) corresponds to of those storage means that send out the priority of the first, second, etc. Identify digits, including the eleventh, twelfth, etc. digits of the phone number from which first sent digit of the phone number to be counted.

These measures are suitable to simplify the structure, as in each Buffer memory only cheap storage means with a very short access time which indicate which position in the multi-digit memory next has to take up or release information, while the complex Devices for switching these position markers in the central control are arranged. During the short access period in which a buffer memory has occupied the common control device, the preset position in the Numbers store their information or a pending storage Record information, then the location marker for input and / or output newly set, i.e. prepared for the next injection or withdrawal process. Information can also be recorded and a Information to be given. Because the buffer memory and the common control device are essentially made up of electronic components, so high operating speeds can be achieved be achieved that safe operation is guaranteed.

In the circuit arrangement according to the invention, therefore, at the beginning the switching means arranged according to each occupancy of the common control device the switching status (charge status) of the storage device of the just connected Buffer memory set. In a further embodiment of the invention the storage means provided for each buffer store are designed as capacitors. This measure brings a significant reduction in price compared to the use of others Storage means.

Another embodiment of the invention provides that in the common Control device test switching means are provided, which by means of a multistable Switching in two successive time cycles in the position marker for the Input recorded information with that recorded in the output location marker Compare information, and that further switching means are provided in a third time cycle when the two pieces of information are the same, the buffer memory is switched off effect and only allow withdrawal if the two pieces of information are inequality. This measure serves to overtake the output of the stored information to prevent and ensure through the input by the common control device, that no incorrect information arising in this case is stored out can. This is achieved by the fact that the storage process is automatic in this case is blocked.

The exemplary embodiment described below shows the application the invention to a numerator. The principle of operation is shown in FIG. 1 and 2, the circuit arrangement of the control device in FIG. 3 shown.

In Fig. 1 shows a number of buffer memories 1, 2 ... B. may be numeric in a telephone exchange. Each of these buffer memories can be connected for a short period of time by a connection device 3 to a control device 4 common to all buffer memories.

A multi-digit number memory 5 is provided in each buffer memory, in which one of the ten digits 0 to 9 can be stored in each position. Further is a position marker 6 in each buffer memory for entering the into the digit memory 5 digits to be stored and a position marker 7 for the output of the Digit memory 5 digits to be saved are arranged.

In the chosen example of a numeric encoder is the one to be stored Information in front of decimal places as keypad code characters is stored in binary and output as a pulse train. There are numerous conversions that are required for this central or individual payers facilities are known that are not here are described in more detail. In the case of the numerator, however, as with everyone else other buffer storage, at the input and at the output after each storage or can be advanced by one position each time it is withdrawn. In known arrangements A buffer-specific counter is used for this purpose.

If in one of the numerators one of the ones not shown in the drawings Numeric keys are operated, then in a manner not explained in detail here pending digit information is transformed and transferred to the position marker 6 designated point of the digit memory 5 is stored. According to the invention switches this numerator by means of a known way automatically the connecting device 3 exerted incentives via the connecting device 3 to the common control device 4, if this is currently free, and stops there is a short period of time in the pause between two keystrokes, in order to advance the position marker 6, if necessary to save it, and also to advance the position marker 7.

If the common control device 4 is not free, then the incentive for the connection device 3 remains until the control device 4 becomes free and the connection device 3 relies on the stimulating buffer memory, e.g. B. Buffer 1, sets. This is possible because the occupancy time of the control device 4 is in each case only so short that the described process leads to the goal without problems even after a waiting time. During the connection existing between a buffer memory and the common control device 4, a new marking is stored in the position marker for input, and immediately afterwards an extraction can be initiated, after which the position marker for output can be reset. For this purpose, the common control device 4 is kept occupied via the connecting device 3 within the pause between two storage processes, and it then also determines which digit must be stored next from the digit memory 5.

In order to prevent a position in the digit memory in which information has already been recorded from being accessed again when the dialing information is entered very quickly and is output very much more slowly, the position marker 6 and the position marker 7 in the buffer memory 1, 2 . .. compared with one another in terms of their information content when the storage chain and the storage chain of the central controller are set to the two position markers in the same buffer memory.

If, according to the display of the position marker, a position in the digit memory has already saved its information content, then the withdrawal is allowed take place in the same place; but point the spot marker for the on and off Output the same status, then there was information that has not yet been saved overwritten, and the result would be a malfunction in the unloading process. The buffer memory must therefore be switched off. All the dialing information must be re-entered.

In Fig. 2 shows an overview circuit diagram of the comparison device which is accommodated in the control device 4. The control device is assigned for three time cycles ZT 1, ZT 2 and ZT 3 . In the timing ZT1 the upcoming location marker in the marker 6 via the AND circuits Xe, Ye, 1 e is transferred to 5 e to caching ZS, wherein it remains stored. In the following time cycle ZT2, the marking pending in the position marker 7 is transmitted via the AND circuits Xa, Ya, la to 5a to the buffers ZS, Xa, Ya, la to 5a, where it also remains stored. The information stored in the buffers ZS (e) is forwarded together with the information stored in the buffers ZS (a) to the AND circuits X, Y, 1 to 5, which when coincident an output signal to the sevenfold AND circuit V. give. When the markings of the two position markers coincide, the gate circuit V emits an output signal which is sent to a further AND circuit S, which sends a blocking signal to the through-flow memory in time cycle ZT3.

In Fig. 3 shows the circuit of the common control devices and part of the circuit of a buffer memory, in particular its location marker for input and output and the above comparison device. Two position markers are provided to identify the position of the digit memory that is to receive or output the dialing information next, each of which is made up of seven capacitors, Xe, Ye, 1 e to 5 e for storing and Xa, Ya, 1 a to 5 a for withdrawal.

If a buffer memory is occupied, a relay B , not shown, responds, the contacts b 1 to b4 of which close the charging circuits for the capacitors Xe, 1 e, Xa and 1 a. The capacitors mentioned are charged, and it is characterized in that the first digit of the digit memory 5 - not shown in the drawing - is the first to be activated for storage when the common control device is occupied and the first to be queried for the withdrawal.

In the buffer memory, a relay EA, also not shown, responds and closes its contacts eal and ea2. Via the contact eal, the potential of -48 V reaches the resistor Wil of the voltage divider composed of the resistors bVi 1, Wi 2 and Wi 3 , whereby the potential at the base electrode of the transistor TrE drops, so that the transistor previously in the off state TrE becomes conductive and the relay E + A connected to its collector electrode via the diode Di 1 responds. As a result, the common control device is occupied by the buffer memory. Other buffer stores that have just been activated go into a brief waiting state. In the connected buffer memory, the relay E connected via the diode D12 to the collector electrode of the transistor TrE also responds and closes its contacts e1 to e7 in the buffer memory. The relay E + A in the control device closes its contacts (e + a) 1 to (e + a) 7. Via the contact e6, the resistor Wi 4 and the diode Di 3, the ground potential applied to the capacitor Xe reaches a bistable flip-flop circuit made up of the transistors TrX and TrY with the relays X and Y. The transistor TrX becomes conductive, the transistor TrY will be blocked. The relay X responds. In a similar way, the ground potential from the capacitor 1e passes through the contact el, the resistor Wi 5 and the diode Di 4 and the further diodes Di 5 to Di 8 to the voltage divider resistors leading to the base electrodes of the transistors TrII to TrV and blocks the transistors TrII to TrV of the multistable trigger circuit, which is made up of the transistors TrI to TrV.

The transistor TrI goes into the conductive state and the relay I responds. In the buffer storage, relay 1D responds via contact L2 and relay XD via contact x2 . The relays 1D and XD mark the position (not shown) of the digit memory in the buffer memory as ready to receive the first dialing information. The contact x3 closes and applies the potential of -48 V via the contact (e + a) 8 to the winding II of the relay X and at the same time via the diode Di 9 and the resistor Wi 6 to the base electrode of the transistor TrXH, making it conductive and the relay XH responds. This applies earth potential with its contact xh to the still closed contact (e + a) 6, whereby the capacitor Xe is recharged via the also still closed contact e6.

via the closed contact 1/1 and the also closed Contact (e + a) 2 as well as contact e2 becomes ground potential at capacitor 2 e im Buffer memory placed so that it is loaded. This is the second digit of the digit memory is preset in the connected buffer memory. If the same Buffer memory is the common control device for a new storage process occupied, then the storage takes place in the now preset position of the digit memory just as it was described in the first digit of the digit memory.

After the position of the position marker for the input has been saved, it will now be described how the position marker for the withdrawal is handled accordingly. In the buffer memory, a relay AA, not shown, responds and closes its contacts aal and aal. Through the contact aal , the potential of -48 V is applied in a similar way to the voltage divider belonging to the base electrode, as was described in the preparation of the storage through the contact eal for the transistor TrE. The transistor TrA becomes conductive, the relay E + A responds, and the pending buffer store thus keeps the common control device for the withdrawal. Relay A in the buffer memory responds and closes its contacts a 1 to a7. When the common control device is first occupied by the buffer memory, the capacitors Xa and 1 a are charged, as has already been described in detail for the capacitors Xe and 1e in the description of the allocation process for the storage. In the manner already described, the transistors TrX and TrI become conductive, as a result of which the relays X and I respond. In the buffer memory the relay 1D respond via the contact 1/2 and the relay XD via the contact x 2, and in the drawing according to FIG. 3 contacts, not shown, of these relays switch the first digit of the digit memory in the buffer memory in a manner not shown to a storage chain that z. B. immediately emits the number of pulses corresponding to the stored digit.

As already described above for the storage process, the transistor TrXH becomes conductive, as a result of which the relay XH responds and recharges the capacitor Xa in the buffer memory; the capacitor 2a in the buffer store is also charged, as already described in a similar manner for the storage process, in that its charging circuit is closed by the contact 1/1. As a result, the second digit of the digit memory is preset for storage. After the first digit has been saved, the buffer memory is again separated from the common control device.

Further injection and withdrawal processes proceed in the same way, wherein in the multistable trigger circuit, the transistors TrII, TrIII, TrIV and TrV one after the other go into the conductive state, all other transistors of the same but always go into the blocked state or remain in it. When the transistor TrV becomes conductive, then the transistor TrY in the from the transistors TrX and TrY formed flip-flop conductive, and the transistor TrX goes into the blocking state. This switching state of the bistable multivibrator is determined together with the same positions of the multistable tilting stage, the next five Set the digit memory for storage and retrieval processes, so that the relay Y in the attracted state together with one of the relays I to V in a known manner forms an identifier for the digits six to ten of a digit memory. if Numbers with more than ten digits are to be dialed, then corresponds to the charge status of those capacitors that take the place of the first, second, etc. to be sent out Identify digits, including the eleventh, twelfth, etc. digits of the phone number from which first sent digit of the phone number to be counted.

If the storage processes follow one another very quickly and cannot be stored as quickly for any reason, then it could happen that the information content from a location in the digit memory that is preset for storage has not yet been stored, which leads to incorrect selection. The same can also occur if the position marker was not advanced due to an error. To avoid the false choice, the charge states of the location marker acting for the storage capacitors Xe, Ye, 1 e and 5 e are those of a location marker acting for Aasspeicherung capacitors Xa, Ya, la compared to 5a, and equality of Markings, the relevant buffer memory is switched off. This switching state is indicated by a character that is not shown.

The comparison of the position markings given by the charge states of the capacitors Xe, Ye, 1 e to 5 e and Xa, Ya, 1 a to 5 a takes place in three time cycles ZT1, ZT2 and ZT3 given by a known, not further described time clock device. In the buffer memory, a relay UPD, not shown, closes a contact iipd which applies the potential of -48 V to the voltage divider arrangement belonging to the base electrode of the transistor TrüP. the transistor TrüP becomes conductive, and the relay üP in the common control device responds. Relay ZT1 responds in the first "storage" cycle and causes relay E in the buffer memory to respond through its contact zt 1. The position marking given by the charge states of the capacitors Xe, Ye, 1e to 5e for storing is, as already described, taken over into the control device by the corresponding switching states of the relays X, Y, I to V, the relay ZT1 drops out.

The relay ZT2 responds in the second time cycle, "Aasspeichern", and the position marking given by the charge states of the capacitors Xa, Ya, la to 5a for the Aassvorpeicher is also transmitted via the multistable circuit consisting of the transistors TrI to TrV and the bistable, The circuit consisting of the transistors TrX and TrY is taken over by the corresponding switching states of the relays X, Y, I to V. If the markings of the position marker for storing and the position marker for storing are different, i.e. two relays from relays I to V or both relays X and Y have responded, then in the first case the transistor TrÜ2, in the second case the transistor TrÜ 1 conductive, relay ü2 or relay 0 1 respond. If the relay ZT3 responds in the third time cycle »Set off«, then one of the two contacts ü 1 or ü2 has cut the blocking line to the buffer tank and this is not triggered. If, however, equality is found when comparing the markings, i.e. neither relay ü1 nor relay t72 have responded, then relay ZT3 triggers the relevant buffer memory through its contact zt3, locks it against the storage of further digits and switches it off. In the third time cycle, the relay ZT3 still disconnects the connection between the common control device and the buffer store holding it occupied, whereupon another buffer store can occupy the control device.

Claims (3)

Claims: 1. Circuit arrangement for controlling the input and output of buffer memories, in which the order of input and output is the same, but the time of input and output depends on various external events, preferably for memory counters, characterized in that in each buffer memory Storage elements (Xe, Ye, 1 e ... 5 e or Xa, Ya, 1 a... 5a) are arranged as position markers (6) for input or as position markers (7) for output, the switching status of which ( State of charge) determines at which point of a multi-digit memory (5) the next digit is to be written or from which position in the multi-digit memory (5) the next digit is to be stored, and that switching means (TrI .. . TrV, I ... V, TrX, TrY, X, Y) are arranged, which with each occupancy by a buffer memory (1,2 ... ) according to the marking of the position nmarker (6 or 7) of this buffer memory can be set and control the desired input or output and change the switching state (charge state) of the corresponding position marker (6 or 7) after carrying out the desired input or output so that the in The next buffer storage location in the order of input or output is preset. 2. Circuit arrangement according to claim 1, characterized in that the storage means provided for each buffer store as Capacitors are formed. 3. Circuit arrangement according to claim 1 or 2, characterized in that in the common control device test switching means (üP, E + A, ZT 1, ZT 2) are provided, which in two successive clocks (ZT1, ZT2) in the position marker for input Compare the pending marking with the marking pending in the position marker for the carrion storage by means of a multistable circuit (Trl ... TrV, I ... V, X, Y) , and that further switching means (Tröl, Ü1, TrÜ2, Ü2, ZT 3, ü l, ü2, zt 3) are provided which, if the two markings are identical, cause the buffer storage to be switched off, but if they are not identical, they allow further Ausspeichentng. References considered: U.S. Patent No. 3,060,270.